A/D, D/C Converters for Image Signal Processing MN65761T Low Power 9-Bit CMOS A/D Converter for Image Processing Features Maximum conversion rate: 18 MSPS (min.) Linearity error: ±1.3 LSB (typ.) Differential linearity error: ±0.6 LSB (typ.) Power supply voltage: 3.6 V or 2.6 V Power consumption: 60 mW (typ.) (fCLK=18 MHz) Applications Digital television receivers N.C. N.C. D6 D5 D4 DVDDL AVSS D3 D2 D1 N.C. N.C. 36 35 34 33 32 31 30 29 28 27 26 25 N.C. N.C. D7 D8 N.C. AVSS AVDD CLK NOE POWD N.C. N.C. 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 The MN65761T is a high-speed 9-bit CMOS analogto-digital converter for image processing applications. It uses a half flash structure based on chopper comparators and achieves both high speed and low power consumption with multiplexing. It provides separate power supply pins for the circuits driving the low-voltage digital output pins. Pin Assignment N.C. N.C. D0 TEST AVDD AVDD AVSS VRBS VRB AVSS N.C. N.C. N.C. N.C. AVSS VRTS VRT AVSS AVDD VRM AVDD VIN N.C. N.C. Overview Digital video equipment Digital image processing equipment (TOP VIEW) TQFP048-P-0707 1 2 POWD 46 45 44 43 42 31 Clock generator 31 Upper encoder (5 bits) 5 Lower encoder B (4 bits) Lower encoder A (4 bits) Lower comparator B (4 bits) Lower comparator A (4 bits) 31 NOE CLK AVDD AVSS 40 39 34 33 32 31 30 29 28 27 22 21 Upper comparator (5 bits) D8 D7 D6 D5 D4 DVDDL AVSS D3 D2 D1 D0(LSB) TEST SS AVDD VRM AVDD VIN 3 AV SS 5 V RT 4 VRTS AVDD 6 AV SS 7 8 9 10 AVDD 18 AV SS 17 VRBS 16 VRB 15 AV 19 20 MN65761T A/D, D/C Converters for Image Signal Processing Block Diagram 31 31 31 5 Error correction and data latch 5 A/D, D/C Converters for Image Signal Processing MN65761T Pin Descriptions Pin No. 1 Symbol N.C. Function Description No connection 2 N.C. No connection 3 AVSS Ground for analog circuits 4 VRTS Reference voltage power supply (TOP) 5 VRT Reference voltage input (TOP) 6 AVSS Ground for analog circuits 7 AVDD Power supply for analog circuits 8 VRM Intermediate reference voltage 9 AVDD Power supply for analog circuits 10 VIN Analog signal input 11 N.C. No connection 12 N.C. No connection 13 N.C. No connection 14 N.C. No connection 15 AVSS Ground for analog circuits 16 VRB Reference voltage input (BOTTOM) 17 VRBS Reference voltage power supply (BOTTOM) 18 AVSS Ground for analog circuits 19 AVDD Power supply for analog circuits 20 AVDD Power supply for analog circuits 21 TEST Test mode selection 22 D0 23 N.C. No connection Digital code output (LSB) 24 N.C. No connection 25 N.C. No connection 26 N.C. No connection 27 D1 Digital output 28 D2 Digital output 29 D3 Digital output 30 AVSS 31 DVDDL Ground for analog circuits 32 D4 Digital output 33 D5 Digital output Power supply for low-voltage digital outputs 34 D6 Digital output 35 N.C. No connection 36 N.C. No connection 37 N.C. No connection 38 N.C. No connection 39 D7 Digital output 40 D8 Digital output (MSB) 3 MN65761T A/D, D/C Converters for Image Signal Processing Pin Descriptions (continued) Pin No. 41 Symbol N.C. Function Description No connection 42 AVSS Ground for analog circuits 43 AVDD Power supply for analog circuits 44 CLK Sampling clock 45 NOE Digital output enable 46 POWD 47 N.C. No connection 48 N.C. No connection Power down mode selection Absolute Maximum Ratings Ta=25˚C Parameter Power supply voltage Symbol VDD Rating – 0.3 to +7.0 Power supply voltage for digital output circuits DVDDL – 0.3 to VDD +0.3 V Input voltage VI – 0.3 to VDD +0.3 V Output voltage VO – 0.3 to VDD +0.3 V Operating ambient temperature Topr –20 to +70 ˚C Storage temperature Tstg –55 to +125 ˚C Recommended Operating Conditions VDD=AVDD=3.6V, DVDDL=2.6V, VSS=AVSS=0V, Ta=25˚C Parameter Power supply voltage Symbol VDD Power supply voltage for digital output circuits Digital input min 3.15 typ 3.60 DVDDL 2.50 2.60 VIH AVDD × 0.55 AVSS "H" level voltage "L" level VIL Reference "H" level VRT voltage "L" level VRB AVSS Clock "H" level pulse width tWH 25 "L" level pulse width Analog input voltage Electrical Characteristics Parameter Power consumption tWL 25 VAIN AVSS Unit V 3.70 V AVDD V AVDD × 0.20 V AVDD V 1.30 V ns ns AVDD V VDD=AVDD=3.6V, DVDDL=2.6V, AVSS=0V, Ta=25˚C Symbol Conditions PC fCLK=18 MSPS min typ max Unit 60 100 mW RES VDD=3.5V, DVDDL=2.5V 9 Linearity error EL fCLK=18MSPS, VDD=3.5V ±1.3 ±2.5 LSB Differential linearity error ED VRT=3.3V, DVDDL=2.5V ±0.6 ±1.0 LSB VRB=1.3V, CLKDuty=50±5% Maximum conversion rate 4 max 3.70 3.30 (not including reference current) Resolution Unit V bit FC(max.) VDD=3.5V, DVDDL=2.5V 18 Clock frequency fCLK VDD=3.5V, DVDDL=2.5V 1 18 MHz Analog input dynamic range DR VDD=3.5V, DVDDL=2.5V 2 VRT –VRB V Output "H" level IOH VOH=DVDDL– 0.8V current "L" level IOL VOL=0.4V 1.5 10 Output delay time td Ta=70˚C, CL=100Ω+10pF Analog input capacitance CI VIN pin MSPS –1.5 mA mA 20 26 35 ns pF A/D, D/C Converters for Image Signal Processing MN65761T Timing Chart The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital output 2.5 clock cycles later at the rising edge of the clock signal. tWH tWL Clock Analog input Data output N N–3 N+1 N–2 N+2 N+3 N–1 N N+4 N+1 td(20ns) Note: The circles indicate analog signal sampling points. 5 MN65761T A/D, D/C Converters for Image Signal Processing Package Dimensions (Unit:mm) TQFP048-P-0707 9.00±0.20 7.00±0.10 36 25 24 0.10 6 SEATING PLANE (1.00) 0 to 10° +0.10 12 +0.10 0.20 -0.05 0.125 -0.05 0.50 1.20max. 1 (0.75) (1.00) 13 0.10±0.10 48 9.00±0.20 7.00±0.10 (0.75) 37 0.50±0.10