A/D, D/C Converters for Image Signal Processing MN65771F Low Power 10-Bit 5 V CMOS A/D Converter for Image Processing Pin Assignment Maximum conversion rate: 18 MSPS (min.) Linearity error: ±1.3 LSB (typ.) Differential linearity error: ±1.0 LSB (typ.) Power supply voltage: 5.0 V or 3.3 V Power consumption: 115 mW (typ.) (fCLK=20 MHz) Applications Digital television receivers Digital video equipment Digital image processing equipment 36 35 34 33 32 31 30 29 28 27 26 25 N.C. AVDD VIN N.C. N.C. N.C. AVSS DVSS DVDD LINDF OVF N.C. 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Features N.C. VRBS VRB VR3 VR2 VR1 VRT VRTS N.C. AVSS AVDD AVDD The MN65771F is a high-speed 10-bit CMOS analogto-digital converter for image processing applications. It uses a half flash structure based on chopper comparators to achieve both high speed and low power consumption. POWD NOE CLK MINV LINV N.C. DVDD DVSS DVSS DVDD TEST1 TEST2 D0 D1 D2 D3 D4 DVSS DVDDL D5 D6 D7 D8 D9 Overview (TOP VIEW) QFH048-P-0707 1 2 3 2 1 47 46 9 8 31 Clock generator Upper encoder (5 bits) 5 Lower encoder (5 bits) 57 POWD 29 Lower comparator (5 bits) RTS VRB VRBS AVSS 20 21 LINV MINV DD 26 AV DD 25 AV 27 VR3 32 V R2 31 VR1 30 VRT 29 V 33 34 35 DD SS 39 V IN 38 AV DVDD 44 DV SS 43 AV 45 ( 24 Upper comparator (5 bits) 10 D7 11 D8 12 D9 13 TEST2 14 TEST1 15 DVDD 16 DVSS 17 DVSS 18 DVDD 22 CLK NOE 23 D6 D5 DDL D3 4 5 D4 6 DVSS 7 DV D2 D1 D0(LSB) OVF UNDF MN65771F A/D, D/C Converters for Image Signal Processing Block Diagram Pin NO. 19, 28, 36, 37, 40, 41, 42, 48 are N.C.pin. 31 5 Error correction and data latch ) A/D, D/C Converters for Image Signal Processing MN65771F Pin Descriptions Pin No. 1 Symbol D0 Function Description Digital code output (LSB) 2 D1 Digital code output 3 D2 Digital code output 4 D3 Digital code output 5 D4 Digital code output 6 DVSS 7 DVDDL Ground for digital circuits 8 D5 Digital code output 9 D6 Digital code output Power supply for digital circuits 10 D7 Digital code output 11 D8 Digital code output 12 D9 Digital code output 13 TEST2 Test mode selection 14 TEST1 Test mode selection 15 DVDD Power supply for digital circuits 16 DVSS Ground for digital circuits 17 DVSS Ground for digital circuits 18 DVDD Power supply for digital circuits 19 N.C. No connection 20 LINV Output inversion 21 MINV Output inversion 22 CLK Sampling clock 23 NOE Digital output enable 24 POWD 25 AVDD Power supply for analog circuits 26 AVDD Power supply for analog circuits 27 AVSS Ground for analog circuits Power down mode selection 28 N.C. No connection 29 VRTS Reference voltage power supply (TOP) 30 VRT Reference voltage input (TOP) 31 VR1 Intermediate reference voltage 32 VR2 Intermediate reference voltage 33 VR3 Intermediate reference voltage 34 VRB Reference voltage input (BOTTOM) 35 VRBS Reference voltage power supply (BOTTOM) 36 N.C. No connection 37 N.C. No connection 38 AVDD Power supply for analog circuits 39 VIN Analog signal input 40 N.C. No connection 3 MN65771F A/D, D/C Converters for Image Signal Processing Pin Descriptions (continued) Pin No. 41 Symbol N.C. Function Description No connection 42 N.C. No connection 43 AVSS Ground for analog circuits 44 DVSS Ground for digital circuits 45 DVDD Power supply for digital circuits 46 UNDF Underflow output 47 OVF Overflow output 48 N.C. No connection Absolute Maximum Ratings Ta=25˚C Parameter Power supply voltage Symbol VDD Rating – 0.3 to +7.0 Unit V VI – 0.3 to VDD +0.3 V Output voltage VO – 0.3 to VDD +0.3 V Operating ambient temperature Topr –20 to +70 ˚C Storage temperature Tstg –55 to +125 ˚C Input voltage Recommended Operating Conditions VDD=AVDD=DVDD=5.0V, DVDDL=3.3V, VSS=AVSS=DVSS=0V, Ta=25˚C Parameter Power supply voltage Symbol VDD min 4.50 typ 5.00 max 5.50 Power supply voltage for digital output circuits DVDDL 3.00 3.30 5.50 V VIH 2.4 VDD V VSS 0.8 V Digital input "H" level voltage "L" level VIL Reference voltage "H" level VRT "L" level VRB "H" level pulse width tWH Clock "L" level pulse width Analog input voltage Electrical Characteristics Parameter Power consumption 4.0 2.0 tWL 25 VSS ns VDD V VDD=AVDD=DVDD=3.0V, AVSS=DVSS=0V, Ta=25˚C Symbol Conditions PC FC=20MSPS min RES typ max Unit 115 200 mW 10 bit Linearity error EL fCLK=18MSPS ±1.3 ±2.5 LSB Differential linearity error ED VRT=4.0V ±1.0 ±1.5 LSB VBB=2.0V Maximum conversion rate 4 V ns (not including reference current) Resolution V 25 VAIN Unit V FC(max.) 18 MSPS Clock frequency fCLK 1 18 MHz Analog input dynamic range DR 2 VRT – VRB V Output "H" level IOH VOH=VDD – 0.8V current "L" level IOL VOL=0.4V 1.5 Output delay time td CL=20pF 10 Analog input capacitance CI 15 pF Sampling delay tsd 7 ns –1.5 mA mA 20 30 ns A/D, D/C Converters for Image Signal Processing MN65771F Timing Chart The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital output 2.5 clock cycles later at the rising edge of the clock signal. tWH tWL Clock Analog input N N+1 tsd(7ns) Data output N–3 N–2 N+2 N+3 N–1 N N+4 N+1 td(20ns) Note: The circles indicate analog signal sampling points. 5 MN65771F A/D, D/C Converters for Image Signal Processing Package Dimensions (Unit:mm) QFH048-P-0707 9.0±0.2 7.0±0.2 36 25 24 9.0±0.2 7.0±0.2 (0.75) 37 13 48 1 0.5 (0.75) 12 0.2±0.1 0.1 SEATING PLANE 6 0.1±0.1 0.15 +0.10 -0.05 2.9 max. 2.5±0.2 (1.0) 0.5±0.2 0 to 10°