ATMEL PS-AT17LV010

PS-AT17LV010
®
revision A
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1 MEGABIT
SERIAL EEPROM, MONOLITHIC SILICON
Revision
Written by
Approved by
Date
A
A. GENTIL / S. JAMES
C. FERRE
02/12/05
PS-AT17LV010
Rev A
DOCUMENTATION CHANGE NOTICE
Date of update
Revision letter
modifications
Sheet 2 / 15
PS-AT17LV010
Rev A
1
SUMMARY
GENERAL........................................................................................................................ 4
1.1
1.2
1.3
1.4
1.5
1.6
Scope .............................................................................................................................................................4
Identification..................................................................................................................................................4
Absolute maximum ratings..........................................................................................................................4
Recommended operating conditions..........................................................................................................4
Radiation features.........................................................................................................................................4
Handling precautions ...................................................................................................................................4
2
3
APPLICABLE DOCUMENTS .......................................................................................... 5
REQUIREMENTS ............................................................................................................ 5
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.3
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
3.6.2
Design, construction, and physical dimensions. ......................................................................................5
Package type. .................................................................................................................................................5
Terminal connections......................................................................................................................................5
Block diagram. ................................................................................................................................................5
Timing waveforms...........................................................................................................................................5
Marking ..........................................................................................................................................................5
Lead Identification...........................................................................................................................................5
Component Number........................................................................................................................................5
Traceability Information...................................................................................................................................6
Electrical characteristics..............................................................................................................................6
Burn-in test....................................................................................................................................................6
Electrical circuit ...............................................................................................................................................6
Parameters drift value.....................................................................................................................................6
Environmental and Endurance Tests..........................................................................................................6
Electrical Circuit for Operating LifeTest ..........................................................................................................6
Electrical Measurements at Completion of Environmental and endurance tests............................................6
Conditions for Operating LifeTest ...................................................................................................................6
Total dose irradiation testing.......................................................................................................................6
Bias Conditions ...............................................................................................................................................6
Electrical Measurements.................................................................................................................................6
4
QUALITY ASSURANCE PROVISIONS........................................................................... 6
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.5
Wafer lot acceptance test.............................................................................................................................6
Sampling and inspection. ............................................................................................................................7
Screening.......................................................................................................................................................7
Quality conformance inspection .................................................................................................................7
Group A inspection. ........................................................................................................................................7
Group C inspection. ........................................................................................................................................7
Group D inspection. ........................................................................................................................................7
Delta measurements.....................................................................................................................................7
5
PACKAGING ................................................................................................................... 7
5.1
Packaging requirements ..............................................................................................................................7
FIGURES
FIGURE 1. Case outline .............................................................................................................................................................. 10
FIGURE 2. Terminal connections. ............................................................................................................................................... 11
FIGURE 3. Block diagram............................................................................................................................................................ 12
FIGURE 4. Timing waveforms. .................................................................................................................................................... 13
FIGURE 5. Electrical circuit for power burn-in and operating life test............................................................................................ 14
FIGURE 6. Electrical circuit for total dose radiation test. .............................................................................................................. 15
TABLES
TABLE I. Electrical performance characteristics. ........................................................................................................................... 8
TABLE 2. Parameter drift values.................................................................................................................................................... 9
Sheet 3 / 15
PS-AT17LV010
Rev A
1
GENERAL
1.1
Scope
This specification details the ratings, physical and electrical characteristics, tests and inspection
data of the 1 megabit serial EEPROM named AT17LV010. It also defines the specific requirement for
space and military applications with high reliability.
1.2
Identification
Part number
AT17LV010-10DP-MQ
AT17LV010-10DP-SV
1.3
Description
1 megabit
serial eeprom
1 megabit
serial eeprom
Access
Time
60ns
60ns
Case
Flat pack 400 mils
28 leads
Flat pack 400 mils
28 leads
Application
Military
application
Space
application
Absolute maximum ratings
Supply voltage range (VDD) ................................................ -0.5V to 7V
Output voltage range (VOUT)............................................... -0.1V dc to VDD + 0.5V dc
Power dissipation (Pd) ....................................................... 0,1W
Storage temperature .......................................................... -65°C to 150°C
Maximum junction temperature (TJ) ................................... 175°C
Thermal resistance junction to case (Θjc) :........................ 9°C/W
Lead temperature (soldering @ 1/16 in, 10 s) ................... 260°C
Endurance.......................................................................... 50,000 write cycles
Data retention .................................................................... 10 years
1.4
Recommended operating conditions.
Supply voltage range (VDD) ................................................ 3 V dc to 3.6 V dc
Ambient operating temperature (TA) ................................. -55°C to 125°C
Storage temperature .......................................................... 30°C, 20 to 65% RH, dust free, original packing
1.5
Radiation features
Tested up to a Total Dose of (according to MIL STD 883 Method 1019) :
(dose rate 0.1 rad/s).......................................................... 20 kRads (Si) Read Only Mode, when biased
........... 60 kRads (Si) Read Only Mode, when un-biased
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
1.6
Handling precautions
These components are susceptible to damage by electrostatic discharge. Therefore, suitable
precautions shall be employed for protection during all phases of manufacturing, testing, shipment and any
handling.
ESD (Rzap = 1.5 kΩ, Czap = 100 pF) ............................... 2000 V (class 3)
Sheet 4 / 15
PS-AT17LV010
Rev A
2
APPLICABLE DOCUMENTS
MIL-PRF-38535 ........................................Integrated Circuits, Manufacturing, General Specification for.
MIL-STD-883 ............................................Test Method Standard Microcircuits.
ASTM Standard F1192-95 ........................Standard guide for the measurement of single event phenomena
from heavy ion irradiation of semiconductor devices
JEDEC Standard EIA/JESD78..................IC latch-up test
ATMEL Aerospace Products Quality Flows
In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence.
3
REQUIREMENTS
3.1
Design, construction, and physical dimensions.
The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and
herein.
3.1.1
Package type.
The package shall be a flat pack 400 mils, 28 leads (figure1). The case shall be hermetically
sealed and have a ceramic body. The leads shall be brazed.
3.1.2
Terminal connections.
The terminal connections shall be as specified on figure 2 .
3.1.3
Block diagram.
The block diagram shall be as specified on figure 3 .
3.1.4
Timing waveforms.
The timing waveforms shall be as specified on figure 4.
3.2
Marking
Each component shall be marked in respect of :
(a) Lead Identification
(b) Component Number
(c) Traceability Information
(d) Manufacturer’s Component Number
3.2.1
Lead Identification
An index shall be located at the top of the package in the position defined in Figure 1.
3.2.2
Component Number
Each component shall bear the component number which shall be constituted and marked as
follows :
AT17LV010-10DP-XX
Product identification
Speed (10 = 100 ns)
Package (DP = flat pack 28)
Level (MQ=Military Level B – SV=Space Level B)
Sheet 5 / 15
PS-AT17LV010
Rev A
3.2.3
Traceability Information
Each component shall be marked in respect of traceability information : lot number and date code.
3.3
Electrical characteristics
The parameters to be measured with respect of electrical characteristics are scheduled in Table 1.
The measurements shall be performed at Tamb=22 ± 3°C, Thigh=125 (+0/-5)°C and Tlow = -55 (+5/-0)°C
respectively.
3.4
3.4.1
Burn-in test
Electrical circuit
Circuit for use in performing the power burn-in is shown in figure 5, in accordance with the intent
specified in test method 1015 of MIL-STD-883.
3.4.2
Parameters drift value
For space application, the parameter drift values applicable to burn-in are specified in Table 2 of
this specification. Unless otherwise stated, measurements shall be performed at + 22 + 3 ° C. The
parameter drift values (Δ), applicable to the parameters scheduled, shall not be exceeded.
In addition to these drift value requirements, the appropriate limit value specified for a given
parameter in Table 1 shall not be exceeded.
.
3.5
Environmental and Endurance Tests
3.5.1
Electrical Circuit for Operating LifeTest
The circuit for operating life testing shall be as specified for power burn in (figure 5).
3.5.2
Electrical Measurements at Completion of Environmental and endurance tests
The parameters to be measured are scheduled in Table 1. Unless otherwise stated, the
measurements shall be performed at tamb = 22+3°C.
3.5.3
Conditions for Operating LifeTest
The conditions for operating life testing shall be as specified for power burn in.
3.6
3.6.1
Total dose irradiation testing
Bias Conditions
Continuous bias shall be applied during irradiation testing as shown in Figure 6 of this specification.
3.6.2
Electrical Measurements
The parameters to be measured prior to, during and on completion of irradiation texture are
scheduled in Table 1 of this specification.
4
QUALITY ASSURANCE PROVISIONS
4.1
Wafer lot acceptance test
Compliant with ATMEL Quality Management System.
Sheet 6 / 15
PS-AT17LV010
Rev A
For space application, Wafer Lot is accepted by a SEM performed according to PAQC0016
(PAQC0016 referred to MIL-Std-883 method 2018 and 21400 ESCC specification).
4.2
Sampling and inspection.
Sampling and inspection procedures shall be in accordance with MIL-PRF-38535.
4.3
Screening.
Screening equivalent to MIL-PRF-38535. Screening shall be conducted on all devices prior to
qualification and technology conformance inspection
• The burn-in test duration, test condition and test temperature, or approved alternatives shall be as
specified in accordance with MIL-PRF-38535.
• Additional screening for space application devices shall be as specified in MIL-PRF-38535, appendix B.
4.4
Quality conformance inspection
Qualification inspection for high reliability and space applications devices shall be in accordance
with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein
for groups A, B, C, D, and E inspections.
4.4.1
Group A inspection.
• Tests shall be as specified in table 1 herein.
• Subgroups 7 and 8 of table I of method 5005 of MIL STD 883 shall include verifying the functionality of
the device.
• O/V (latch up) tests shall be measured only for the initial qualification and after any process or design
changes which may affect the performance of the device.
• Capacitance measurement shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the
designated terminal and GND at a frequency of 1 MHz. Sample size is five devices with no failure, and all
input and output terminals tested.
4.4.2
Group C inspection.
The group C inspection end-point electrical parameters shall be as specified in table 1 herein.
4.4.3
Group D inspection.
The group D inspection end-point electrical parameters shall be as specified in table 1 herein.
4.5
Delta measurements
Delta measurements, as specified in table 2, shall be made and recorded before and after the
required burn-in screens to determine delta compliance. The electrical parameters to be measured, with
associated delta limits are listed in table 2. The device manufacturer may, at his option, either perform
delta measurements or within 24 hours after life test perform final electrical parameter tests, subgroups 1,
7 and 9.
5
PACKAGING
5.1
Packaging requirements
The requirements for packaging shall be in accordance with MIL-PRF-38535.
Sheet 7 / 15
PS-AT17LV010
Rev A
TABLE I. Electrical performance characteristics.
Test
method MilStd-883
High level input
voltage
Low level input
voltage
High level output
voltage
Low level output
voltage
Low level Input
current
High level Input
current
Supply current
Active mode
Supply current
Standby mode
Input
capacitance
VIH
3013
Conditions
-55°C ≤ TC ≤ +125°C
+3 V ≤ VDD ≤ +3.6 V
unless otherwise specified
VDD = 3.6 V
VIL
3013
VDD = 3.0 V
VOH
3007
VDD =3 V, IOH = -2 mA VSS =0V
VOL
3007
VDD =3 V, IOL = 3 mA VSS =0V
IIL
3009
VIN =0 VDD = 3.6V VSS =0V
IIH
3009
VIN =VDD = 3.6V VSS =0V
ICCA
3005
ICCS
Test
Sym
bol
Limits
Min
2
Unit
Note
Max
V
4
V
4
V
3
V
3
μA
3
10
μA
3
VDD = 3.6V VSS =0V
5
mA
3
3005
VDD = 3.6V VSS =0V
150
µA
3
CIN
3012
12
pF
5
Output
capacitance
COUT
3012
VIN = 0 V VSS =0V
TC = 25°C
fIN = 1.0 MHz
VOUT = 0 V VSS =0V
TC = 25°C
fIN = 1.0 MHz
12
pF
5
Maximum clock
frequency
FMAX
10
MHz
CE setup time
TSCE
2.4
0.4
-10
3003
VDD = 3 V &VDD = 3.6 V, FMAX
to CLK (to
guarantee
proper counting)
CE hold time to
CLK (to
guarantee
proper counting)
CLK low time
CLH high time
OE high time (to
guarantee
counter is reset)
OE to data delay
(1)
CLK to data
delay (1)
Data hold from
CE , OE or CLK
0.8
35
ns
3
THCE
3003
VDD = 3 V &VDD = 3.6 V, FMAX
0
ns
3
TLC
THC
THOE
3003
3003
3003
VDD = 3 V &VDD = 3.6 V, FMAX
VDD = 3 V &VDD = 3.6 V, FMAX
VDD = 3 V &VDD = 3.6 V, FMAX
25
25
ns
ns
4
4
4
25
ns
TOE
3003
VDD = 3 V &VDD = 3.6 V, FMAX
55
ns
TCAC
3003
VDD = 3 V &VDD = 3.6 V, FMAX
60
ns
TOH
3003
VDD = 3 V &VDD = 3.6 V, FMAX
CE or OE to
data float delay
(2)
TDF
3003
VDD = 3 V &VDD = 3.6 V, FMAX
CE to data
TCE
delay (1)
0
ns
50
3
3
3, 6
ns
4
3003
VDD = 3 V &VDD = 3.6 V, FMAX
60
ns
3
Sheet 8 / 15
PS-AT17LV010
Rev A
CLK to data float
delay when
cascading (2)
CLK to CEO
delay when
cascading (1)
CE to CEO
delay when
cascading (1)
RESET /OE to
TCDF
3003
VDD = 3 V &VDD = 3.6 V, FMAX
3003
VDD = 3 V &VDD = 3.6 V, FMAX
TOCK
3003
3003
ns
55
ns
40
ns
40
ns
4
3
VDD = 3 V &VDD = 3.6 V, FMAX
TOCE
TOOE
50
VDD = 3 V &VDD = 3.6 V, FMAX
3
3
CEO delay
when cascading
(1)
Notes :
(1)
(2)
(3)
(4)
(5)
(6)
Output load gate equivalent +CL <30 pF
Float delays are measured with 5 pF AC loads. Transition is measured +/- 200 mV from steady-state active levels
Recorded
Go-no-go tested
This parameter is tested initially and after any design or process change which could affect this parameter,
and therefore shall be guaranteed to the limits specified in Table I
All the cases are tested, but only one is recorded (worst case) if required (note 3)
TABLE 2. Parameter drift values
Test
High level output
voltage
Low level output
voltage
Low level Input
current
High level Input
current
Supply current
Standby mode
Sym
bol
VOH
Test method
Mil-Std-883
As per table 2
VOL
Conditions
As per table 2
Drift
limits
0.1
Unit
V
As per table 2
As per table 2
0.1
V
IIL
As per table 2
As per table 2
0.5
μA
IIH
As per table 2
As per table 2
0.5
μA
ICCS
As per table 2
As per table 2
15
µA
Note : the above parameter shall be recorded before and after burn-in and life test to determine the delta.
Sheet 9 / 15
PS-AT17LV010
Rev A
FIGURE 1. Case outline
mm
inch
Min
Max
Min
Max
A
2.29
3.30
0.090
0.130
b
0.38
0.48
0.015
0.019
c
0.08
0.15
0.003
0.006
D
---
18.80
---
0.740
E
9.65
10.67
0.380
0.420
E2
4.57
---
0.180
---
E3
0.76
---
0.030
---
1.27 BSC
e
0.050 BSC
L
6.35
9.40
0.250
0.370
Q
0.66
---
0.026
---
S
---
1.30
---
0.051
S1
0.00
---
0.000
---
N
28
Sheet 10 / 15
PS-AT17LV010
Rev A
FIGURE 2. Terminal connections.
Case outline
X
Pin Number
Name
1
RESET /OE
2
NC
3
WP2
4
CE
5
GND
6
NC
7
NC
8
NC
9
NC
10
NC
11
CEO
12
NC
13
NC
14
READY
15
NC
16
NC
17
SER _ EN
18
NC
19
VCC
20
NC
21
NC
22
NC
23
NC
24
DATA
25
CLK
26
WP1
27
NC
28
NC*
Note : * indicates this pin must not be used
Name
CE
Description
Output enable (active high) and reset (active
low) when SER _ EN is high. The logic polarity
of this input is programmable
Used to protect portions of memory during
programming
Chip enable input
CEO
Chip enable output
READY
SER _ EN
Open collector reset state indicator
Serial enable
DATA
CLK
VCC
GND
Tri-state data for configuration
Clock input
Power
Ground
RESET /OE
WP1,WP2
Sheet 11 / 15
PS-AT17LV010
Rev A
FIGURE 3. Block diagram
Sheet 12 / 15
PS-AT17LV010
Rev A
FIGURE 4. Timing waveforms.
4(a). AC characteristics
4(b). AC characteristics when cascading
Sheet 13 / 15
PS-AT17LV010
Rev A
FIGURE 5. Electrical circuit for power burn-in and operating life test.
S1
2,2K
NC
1
28
NC
2
27
NC
GND
2,2K
3
26
2,2K
GND
S2
2,2K
4
25
2,2K
S3
GND
5
24
4,7K
VDD
NC
6
23
4,7K
GND
NC
7
NC
NC
22
NC
8
21
NC
NC
9
20
NC
NC
10
19
VDD
11
18
GND
4,7K
AT17LV010
NC
2,2K
NC
12
17
NC
13
16
NC
GND
14
15
NC
S4
Notes :
S1 to S4 are signals which enable to read continuously the Eeprom 1 Meg memory plan according to the Figure 4a.
Sheet 14 / 15
PS-AT17LV010
Rev A
FIGURE 6. Electrical circuit for total dose radiation test.
3.3V ± 0.1
1
28
2
27
3
26
4
25
5
24
6
23
7
8
9
10
11
22
AT17LV01
21
20
19
18
12
17
13
16
14
15
Input protection resistors = 5,6 kohm +/- 10%
Sheet 15 / 15