ATMEL ATR0601-PFQW

Features
•
•
•
•
•
•
•
•
Very Low Power Design (40 mW)
Single IF Architecture
Excellent Noise Performance
1.5-bit ADC On Chip
Small QFN Package (4 mm × 4 mm, 24 pins)
Highly integrated, Few External Components
Advanced BiCMOS Technology (UHF6s)
Non ESD Sensitive Device
GPS Front-end
IC
1. Description
The ATR0601 is a single IF GPS front-end IC, designed to meet the requirements of
mobile and automotive applications. Excellent RF performance combined with low
noise figure enables high quality GPS solutions and it's very low power consumption
fits perfectly to portable devices. Featuring a balanced XTO and a fully integrated balanced frequency synthesizer, only few external components are required. The
ATR0601 offers a complete autonomous mode, utilizing the on chip AGC in closed
loop operation, to set the gain of the IF VGA. Alternatively, in combination with the
baseband processor ATR0621 the optimum gain of the IF VGA can be computed and
set by software, using the digital SDI interface.
PURF
EGC
AGCO
NBPI
BPI
NBP
BP
VDIG
VCC
PUXTO
Preliminary
Block Diagram
VCC
Figure 1-1.
ATR0601
SDI
PMSS
Logic
1
A
D
RF
NRF
A
D
VCO
PLL
SL
SH
SC
XTO
NXTO
XTO
X
MO
TEST
GND
NX
Rev. 4866A–GPS–08/05
2. Pin Configuration
Pinning QFN24
SC
SH
SL
SDI
EGC
VCC
Figure 2-1.
24 23 22 21 20 19
VDIG
AGCO
NXTO
NX
X
XTO
1
2
3
4
5
6
Paddle
GND
18
17
16
15
14
13
PURF
PUXTO
NBPI
BPI
NBP
BP
VCC
MO
TEST
NRF
RF
NC
7 8 9 10 11 12
Table 2-1.
Pin
Symbol
Type(1)
Paddle
GND
S
Common ground
Digital supply
Function
1
VDIG
S
2
AGCO
A_I/O
3
NXTO
A_I
XTO interface (optional: TCXO input)
4
NX
A_O
XTO interface
5
X
A_O
XTO interface
6
XTO
A_I
XTO interface (optional: TCXO input)
7
VCC
S
8
MO
A_O
Testbuffer output (fIF)
9
TEST
A_I
Enable testbuffer
10
NRF
A_I
RF input complementary
11
RF
A_I
RF input
12
NC
–
13
BP
A_O
IF-Filter interface (mixer output, open collector)
14
NBP
A_O
IF-Filter interface (mixer output complementary, open collector)
15
BPI
A_I
IF-Filter interface (IF-input)
16
NBPI
A_I
IF-Filter interface (IF-input complementary)
17
PUXTO
D_I
Power-up XTO
18
PURF
D_I
Power-up RF
19
VCC
S
Analog supply
20
EGC
D_I
Enable external gain control (high = external; low = internal)
21
SDI
D_I
Input for external gain control signal (Σ∆ modulation)
AGC: gain control voltage output/corner frequency determination
Analog supply
Not connected
22
SL
D_O
Data output: “low”
23
SH
D_O
Data output: “high”
24
SC
D_O
Sample clock
Note:
2
Pin Description
1. Type: A_I Analog input, A_O Analog output, D_I Digital input, D_O Digital output, S Supply
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
3. Functional Description
3.1
General Description
The ATR0601 GPS receiver IC has been especially designed for GPS applications in both
mobile phone and automotive applications. From this system point of view, it incorporates highest isolation between GPS and cellular bands, as well as very low power consumption.
The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a centre frequency of: fRF = 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK)
with a chip rate of 1.023 Mbps. As the input signal power at the antenna is approximately
–140 dBm, the desired signal is below the thermal noise floor.
3.2
PMSS Logic
The Power Management, Startup and Shutdown Logic ensures reliable operation within the recommended operating conditions. The external power control signals PUrf and PUxto are passed
thru Schmitt-trigger inputs to eliminate voltage ripple and prevent undesired behaviour during
startup and shutdown. Digital and analog supply voltages are analyzed by a monitoring circuit,
enabling the startup of the IC only within a secure operating area.
3.3
XTO
The XTO is designed for minimum phase noise and frequency perturbations. The balanced
topology gives maximum isolation from external and ground coupled noise. The built-in jump
start circuitry ensures reliable start-up behaviour of any specified crystal. For use with an external TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.
The recommended reference frequency is: fXTO = 23.104 MHz.
3.4
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behaviour and
excellent spurious suppression. The relation between the reference frequency (fXTO) and the
VCO centre frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
3.5
RF-Mixer/Image-filter
Combined with the antenna an external LNA provides a first band path filtering of the signal. For
the LNA, Atmel’s ATR0610 is recommended, due to it’s low Noise Figure, high linearity an low
power consumption. The output of the LNA drives an SAW filter, which provides image rejection
for the mixer and the required isolation of all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
The IF frequency (fIF) is given by: fIF = fRF – fVCO = 1575.42 MHz – 1478.656 MHz = 96.764 MHz.
3.6
IF-filter
The mixer directly drives an external LC-Bandpath filter via open collector outputs. In order to
provide highest selectivity and conversion gain, it is recommended to design the external filter,
according to the application proposal, as a 2-pole filter with a quality factor Q > 25.
3
4866A–GPS–08/05
3.7
VGA/AGC
The output of the IF-Filter drives an on-chip Variable Gain Amplifier (VGA) which is combined
with additional low-pass filtering. The on-chip Automatic Gain Control (AGC) stage sets the gain
of the VGA in order to optimally charge the input of the following analog-to-digital converter. The
AGC control loop can be selected for on-chip closed loop operation or for external gain control
mode. For external gain control mode, the loop needs to be closed by the baseband IC
ATR0621.
3.8
A/D Converter
The analog-to-digital converter stage has a total resolution of 1.5 bit. It comprises balanced comparators and a sub sampling unit, clocked by the reference frequency (fXTO). The frequency
spectrum of the digital output signal (fOUT), present at the data outputs SL and SH, is then given
by: fOUT = ⏐ fIF – fXTO × n⏐ . The selected sub sampling factor (n = 4) leads to the designated
digital output signal, with a centre frequency given by:
fOUT = fIF – fXTO × 4 = 96.764 MHz – 23.104 MHz – 4 = 4.348 MHz.
3.9
Clock and Data Driver
CMOS output drivers are providing sign and magnitude bits as well as the system clock to the
baseband IC ATR0621. The rail-to-rail output signal level is determined by the digital supply voltage (VDIG).
4
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Analog supply voltage
VCC
–0.3 to +3.7
V
Digital supply voltage
VDIG
–0.3 to +3.7
V
Vin
–0.3 to +3.7
V
Input voltage
Operating temperature
Top
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Symbol
Value
Unit
Rth
125
K/W
5. Thermal Resistance
Parameters
Junction ambient
6. Operating Range
Parameters
Symbol
Value
Unit
Analog supply voltage
VCC
2.70 to 3.30
V
Digital supply voltage
VDIG
1.65 to 2.00
V
V∆
≥ 0.80
V
Temp
–40 to +85
°C
Input frequency
fRF
1575.42
MHz
Reference frequency
fXTO
23.104
MHz
Supply voltage difference (V∆ = VCC – VDIG)
Temperature range
7. Electrical Characteristics
No.
1
1.1
Parameters
Test Conditions
Pin
Symbol
VPUxto = VPUrf = VPU,on
7, 19
IS
VPUxto = VPUrf = VPU,on
1
Min.
Typ.
Max.
Unit
Type*
14.2
mA
A
IDIG
700
µA
A
Common
Analog supply current(1)
(1),(2)
1.2
Digital supply current
1.3
Analog supply current in
XTO mode(1)
VPUxto = VPU,on,
VPUrf = VPU,off
7, 19
IS_XTO
2.9
mA
A
1.4
Digital supply current in
XTO mode(1),(3)
VPUxto = VPU,on,
VPUrf = VPU,off
1
IDIG_XTO
500
µA
A
1.5
Supply current in power
down mode(1)
VPUxto = VPUrf = VPU,off
1, 7, 19
IPD
µA
A
1.6
Maximum total gain
VAGCO = 2.2V
dB
B
1.7
Noise figure (SSB)
dB
C
Gmax_tot
NFtot
2
90
6.8
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Conditions: VCC = 2.7V; VDIG = 1.65V; Temperature = 27°C
2. Capacitive load (CL = 3.3 pF) at pins 22, 23, 24
3. Capacitive load (CL = 3.3 pF) at pin 24
5
4866A–GPS–08/05
7. Electrical Characteristics (Continued)
No.
2
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Mixer
2.1
Output frequency
fXTO = 23.104 MHz
13, 14
fIF
96.764
MHz
A
2.2
Input impedance
(balanced)
fRF = 1575.42 MHz
10, 11
Z11
10-j80
Ω
C
2.3
Conversion Gain
Recommended IF-filter
8
GMIX
20
dB
B
8
NFMIX
5.8
dB
C
2.4
3
Noise figure (SSB)
VGA/AGC
3.1
Minimum gain
VAGCO = 1.0V
GVGA,min
0
dB
B
3.2
Maximum gain
VAGCO = 2.2V
GVGA,max
70
dB
B
3.3
Control-voltage sensitivity
3.4
AGC cut-off frequency
Cext = open
3.5
AGC cut-off frequency
Cext = 100 pF
3.6
Gain-control output
voltage
4
VAGCO = 2.2V
NVGA,min
6.6
dB/V
D
VAGCO = 1.0V
NVGA,max
150
dB/V
D
2
f3dB_AGC
250
kHz
D
2
f3dB_AGC
33
kHz
D
2
VAGCO
V
B
0.9
2.3
Reference Oscillator
4.1
XTO phase noise at
100 Hz
With specified crystal
24
Pn100
–80
dBc/Hz
C
4.2
XTO phase noise at 1 kHz With specified crystal
24
Pn1k
–100
dBc/Hz
C
5
Clock and Data Driver
5.1
Clock driver frequency
fXTO = 23.104 MHz
24
fCLK
23.104
MHz
A
5.2
Clock output level
Cload,max = 10 pF
24
VCLK,high
0.9 × VDIG
V
B
5.3
Clock output level
Cload.max = 10 pF
24
VCLK,low
0.1 × VDIG
V
B
5.4
Data output level
Cload,max = 10 pF
22, 23
VData,high
0.9 × VDIG
V
B
5.5
Data output level
Cload,max = 10 pF
22, 23
VData,low
0.1 × VDIG
V
B
V
A
V
A
6
PMSS
6.1
Voltage level power-on
17, 18
VPU,on
6.2
Voltage level power-off
17, 18
VPU,off
1.3
0.5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Conditions: VCC = 2.7V; VDIG = 1.65V; Temperature = 27°C
2. Capacitive load (CL = 3.3 pF) at pins 22, 23, 24
3. Capacitive load (CL = 3.3 pF) at pin 24
6
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
8. Timing
Figure 8-1.
Recommended Power-up/down Sequence
VCC
VDIG
PUxto
PUrf
tmin = 0s
Figure 8-2.
tmin = 0s
tmin = 0s
tmin = 5ms
tmin = 0s
tmin=0s
tmin = 0s
Recommended Sleep-mode Sequence
VCC
VDIG
PUxto
PUrf
tmin = 0s
Figure 8-3.
tmin = 4 µs
tmin = 0s
Recommended XTO Start-up/Shut-down Sequence
VCC
VDIG
PUxto
tmin = 1 ms
Figure 8-4.
tmin = 4 µs
Sample Clock Start-up Delay
VCC
VDIG
PUxto
SC
tmax = 500 µs
T = 1/23.104 MHz
7
4866A–GPS–08/05
Figure 8-5.
Synchronous Shut-down Behaviour of SC with Respect to PUxto
VCC
VDIG
PUxto
SC
T = 1/23.104 MHz
tmin = 0s
tmax = 25ns
Figure 8-6.
tmax = 0s
Data Outputs SL and SH are Valid with Rising Edge of Sample Clock SC
SL
SH
SC
T = 1/23.104 MHz
8
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
9. Application Circuit
AGCO
2
NBPI 16
EGC 20
100pF
220nH
5pF
BPI 15
BP 13
VDIG 1
VCC 19
VCC 7
VCC
PU RF
PU RF
NBP 14
5pF
100nF
PU XTO
220nH
100nF
220nH
220nH
100nF
VCC
VDIG
VCC
Application Example Using a GPS Crystal with ESRtyp = 12Ω (Please see Table 9-1 on page 11)
VCC
Figure 9-1.
SDI 21
17 PUxto
18 PUrf
PMSS
Logic
1
10nF
1.3pF
47pF
4.7nH
SL 22
A
11 RF
D
Data out "low"
5.6nH
1.5pF
ATR0610
SAW
B4060
1.3pF
LNA section (opt.)
SH 23
A
10 NRF
D
VCO
PLL
6 XTO
SC 24
Data out "high"
Sample clock
3 NXTO
47pF
Reference frequency: Application #1
Note:
12 NC
4 NX
8 MO
X1
XTO
5 X
9 TEST
82pF
GND
47pF
27
Please consider the recommended IF-filter layout, shown in Figure 9-5 on page 11.
Figure 9-2.
Application Example Using a GPS Crystal with ESRtyp ≠ 12Ω
(Please see Table 9-2 on page 11)
6
XTO
3
NXTO
47pF
5
R1
X
82pF
4
NX
X1
47pF
Reference frequency: Application #2
Note:
The external series resistor R1 has to be selected depending on the typical value of the crystal
ESR. Please refer to Application Note “ATR0601: Crystal and TXCO selection”.
9
4866A–GPS–08/05
Figure 9-3.
Equivalent Application Examples Using a GPS TCXO (Please see Table 9-3 on
page 12)
33 pF
6
XTO
10 pF
3
TCXO
NXTO
22 pF
5
X
Do not
4
connect
NX
Reference frequency: Application #4a
6
10 pF
XTO
33 pF
3
TCXO
NXTO
22 pF
5
X
Do not
4
connect
NX
Reference frequency: Application #4b
Figure 9-4.
Application Example Using an External Reference and Balanced Inputs
(Please see Table 9-4 on page 12)
1:1
6
XTO
Vin
3
NXTO
5
Do not
connect
X
4
NX
Reference frequency: Application #5
10
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
Recommended IF-filter: Layout versus Schematic
14
Ca
15
16
Lc
BPI
NBPI
Cb
NBP
13
BP
Figure 9-5.
13
14
15
16
Ld
Ca
Cb
B
Lc
Le
A
Note:
Ld
Le
Lf
Lf
VCC
Mutual inductance between the four inductors Lc - Lf plays an important role in the IF-filter characteristics. In any design, the layout arrangement shown in Figure 9-5 on page 11 should be
resembled as close as possible. Measures: A = 2.8 mm; B = 1.4 mm; Lc - Lf: Wirewound SMD
inductors, 0603 size. (Please see Table 10-1).
Table 9-1.
Specification of GPS Crystals Appropriate for the Application Example Shown in
Figure 9-1 on page 9
Parameter
Comment
Min.
Typ.
Max.
Units
Frequency Characteristics
Fundamental Frequency
Nominal frequency referenced to
25°C
Calibration tolerance
Frequency at 23°C ±2°C
7.0
±ppm
Frequency deviation
Over operating temperature range
15.0
±ppm
Temperature range
Operating temperature range
–40.0
+85.0
°C
18.5
19.5
pF
23
Ω
23.104
MHz
Electrical
Load capacitance (CL)
Equivalent Series Resistance (ESR)
Fundamental
Table 9-2.
Parameter
Specification
7
12
Specification of GPS Crystals Appropriate for the Application Example Shown in
Figure 9-2 on page 9
Comment
Min.
Typ.
Max.
Units
40
Ω
Equivalent Series Resistance (ESR)
Fundamental
Note:
Specification
7
All other parameters as specified in Table 9-1.
11
4866A–GPS–08/05
Table 9-3.
Specification of GPS TCXOs Appropriate for the Application Example Shown in
Figure 9-3 on page 10
Parameter
Comment
Min.
Typ.
Max.
Units
Frequency Characteristics
Nominal Frequency
Nominal frequency referenced to
25°C
Frequency deviation
Over operating temperature range
Temperature range
Operating temperature range
23.104
–40.0
MHz
2.0
±ppm
+85.0
°C
Electrical
Output waveform
DC coupled clipped sinewave
Output voltage
(peak-to-peak)
At minimum supply voltage
Output load capacitance
Tolerable load capacitance
Table 9-4.
0.8
V
10
pF
Specification of an external reference signal for the application example shown in
Figure 9-4 on page 10
Parameter
Comment
Min.
Typ.
Max.
Units
Signal Characteristics
Nominal Frequency
12
23.104
Waveform
Sinewave or clipped sinewave
Amplitude
Voltage peak-to-peak
0.6
0.8
MHz
1.0
V
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
10. Demonstration Board
Figure 10-1. Schematic of Demonstration Board
VCC
L3
L5
L4
C22
C21
13
14
15
NBP
BP
2
NBPI
1
C3
C10
16
BPI
J3
P1
L6
8
2
MO
AGCO
VDD1.8
20
EGC
21
C7
J2
NIN
NOUT
R1
9
TEST
11
1
P2
IN
OUT
2
C15
XTO
NXTO
6
3
C5
1
2
3
C1
19
7
1
2
J4
NX
4
NC
12
PURF
PUXTO
18
17
C6
J1
X1
C4
VCC
J6
R7
FB1
VCC
1
2
SC
5
VDD1.8
J5
22
24
10
X
VCC
1
2
SL
NRF
FI1
23
SH
RF
L2
6
P4
SDI
1
2
3
C17
5
1
2
3
VDD1.8
1 2 3
J8
1 2 3
J9
VDIG
1
FB2
C2
C19
C9
C8
13
4866A–GPS–08/05
Figure 10-2. Illustration of Demonstration Board
Table 10-1.
Qty
Device
Parts
4
JP2E
J3, J4, J5, J6
Molex
90120-0762
5
JP3E
J1, J2, J7, J8, J9
Molex
90120-0763
Value
Tolerance Manufacturer
Mfr. Order Code
Vishay
CRCW0402000Z
1
0
RESISTOR-0402
R1
1
2n2
CAPACITOR-0402
C3
5%
Vishay
VJ0402Y222JXJA
2
1p3
CAPACITOR-0402
C15, C17
0,1 pF
Tayo Yuden
EVK105CH1R3BW
1
5n6 2%
Multilayer
INDUCTOR-0402
L2
2%
Würth
Elektronik
744784056G
2
5p0 ±0p1
CAPACITOR-0402
C21, C22
±0p1
Yageo America 0402CG509C9B200
2
10µ
ELKO-B
C1, C2
20%
Vishay
293D106X0016B2
1
27
RESISTOR-0402
R7
5%
Vishay
CRCW040227RJ
2
47p
CAPACITOR-0402
C5, C6
5%
Vishay
VJ0402A470JXXA.
1
82p
CAPACITOR-0402
C4
Vishay
VJ0402A820JXXA
4
100n
CAPACITOR-0402
C7, C8, C9, C19
5%
Vishay
VJ0402V104JXJ
1
100p
CAPACITOR-0402
C10
5%
Vishay
VJ0402A101JXXA.
3
14
BOM of Demonstration Board
142-0711-841 COAX-SMA
P1, P2, P4
4
220n 2%
INDUCTOR_WIREWOUND-0603
L3, L4, L5, L6
2
74279266
FERRITE_BEAD-0603
1
ATR0601-1
1
B4060
1
RSX-5
23.104 MHz
Johnson Comp. 142-0711-841
Würth
Elektronik
744761222G
FB1, FB2
Würth
Elektronik
74279266
ATR0601-1
IC1
Atmel
ATR0601
FILTER-BALANCED
FI1
Epcos
B4060
Rakon
XZC736 IEC19RSX-5
23.104 MHz
XTAL-4PIN-6035
X1
2%
ATR0601 [Preliminary]
4866A–GPS–08/05
ATR0601 [Preliminary]
11. Recommended Footprint
Figure 11-1. Recommended Footprint (QFN24 - 4 mm × 4 mm)
15
4866A–GPS–08/05
12. Ordering Information
Extended Type Number
Package
QFN24, 4 × 4
ATR0601-PFQW
Remarks
Taped and reeled
13. Package Information
Package: QFN 24 - 4 x 4
Exposed pad 2.6 x 2.6
(acc. JEDEC OUTLINE No. MO - 220)
Dimensions in mm
Not indicated tolerances ±0.05
0.9±0.1
4
+0
2.6
0.05-0.05
24
19
1
24
18
0.4
1
6
0.25
13
6
12
technical drawings
according to DIN
specifications
7
0.5 nom.
Drawing-No.: 6.543-5101.02-4
2.5
Issue: 1; 03.06.05
16
ATR0601 [Preliminary]
4866A–GPS–08/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
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