Preliminary Technical Data FEATURES Filterless Class-D amplifier with built-in output stage 2 W into 4 Ω and 1.2 W into 8 Ω at 5.0 V supply with less than 10% THD 85% efficiency at 5.0 V, 2W into 4 Ω speaker Better than 95dB SNR (signal-to-noise ratio) Available in 16-lead 3 mm × 3 mm LFCSP Single-supply operation from 2.2 V to 5.0 V 20 nA ultralow shutdown current Short-circuit and thermal protection Pop-and-click suppression Built-in resistors reduce board component count Default fixed 18dB gain and user-adjustable APPLICATIONS 2 W Filterless Class-D Stereo Audio Amplifier SSM2304 The SSM2304 features a high efficiency, low noise modulation scheme. It operates with 85% efficiency at 2 W into 4 Ω from a 5.0 V supply and has a signal-to-noise ratio (SNR) that is better than 95 dB. PDM modulation is used to provide lower EMIradiated emissions compared with other Class-D architectures. The SSM2304 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin. The architecture of the device allows it to achieve a very low level of pop and click. This minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. Notebooks and PCs Mobile phones MP3 players Portable gaming Portable electronics Educational toys The fully differential input of the SSM2304 provides excellent rejection of common-mode noise on the input. Input coupling capacitors can be omitted if the dc input common-mode voltage is approximately VDD/2. GENERAL DESCRIPTION The SSM2304 also has excellent rejection of power supply noise, including noise caused by GSM transmission bursts and RF rectification. PSRR is typically 70 dB at 217 Hz. The SSM2304 is a fully integrated, high efficiency, Class-D stereo audio amplifier. It is designed to maximize performance for portable applications. The application circuit requires a minimum of external components and operates from a single 2.2 V to 5.0 V supply. It is capable of delivering 2 W of continuous output power with less than 10% THD + N driving a 4 Ω load from a 5.0 V supply. The gain can be set to 6 dB or 18 dB utilizing the gain control select pin connected respectively to ground or VDD. Gain can also be adjusted externally by using an external resistor. The SSM2304 is specified over the commercial temperature range (−40°C to +85°C). It has built-in thermal shutdown and output short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm lead-frame chip scale package (LFCSP). Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. SSM2304 Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM 0.1µF 10µF SSM2304 0.01µF1 RIGHT IN+ VDD OUTR+ INR+ INR– RIGHT IN– VDD VBATT 2.5V TO 5.0V GAIN CONTROL MODULATOR FET DRIVER OUTR– 0.01µF1 SD GAIN GAIN 0.01µF1 LEFT IN+ INTERNAL OSCILLATOR OUTL+ INL+ INL– LEFT IN– BIAS GAIN CONTROL MODULATOR 0.01µF1 GND 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 1. Rev. PrD | Page 2 of 19 FET DRIVER OUTL– GND 06162-001 SHUTDOWN Preliminary Technical Data SSM2304 TABLE OF CONTENTS Features...............................................................................................1 Pop-and-Click Suppression .......................................................12 Applications .......................................................................................1 EMI Noise ....................................................................................12 General Description..........................................................................1 Layout ...........................................................................................13 Functional Block Diagram ...............................................................2 Input Capacitor Selection ..........................................................13 Revision History................................................................................3 Proper Power Supply Decoupling.............................................13 Specifications .....................................................................................4 Evaluation Board Information ......................................................14 Absolute Maximum Ratings ............................................................5 Introduction.................................................................................14 Thermal Resistance.......................................................................5 Operation .....................................................................................14 ESD Caution ..................................................................................5 SSM2304 Application Board Schematic ..................................15 Pin Configuration and Function Descriptions .............................6 SSM2304 Stereo Class-D Amplifier Evaluation Module Component List...........................................................................16 Typical Performance Characteristics ..............................................7 Typical Application Circuits ..........................................................11 Application Notes............................................................................12 Overview ......................................................................................12 SSM2304 Application Board Layout ........................................17 Outline Dimensions........................................................................18 Ordering Guide ...........................................................................18 Gain Selection..............................................................................12 REVISION HISTORY 7/06—Revision 0: Initial Version Rev. PrD | Page 3 of 19 SSM2304 Preliminary Technical Data SPECIFICATIONS VDD = 5.0 V, TA = 25oC, RL = 8 Ω, Gain=6dB, unless otherwise noted Table 1. Parameter DEVICE CHARACTERISTICS Output Power Symbol Conditions PO RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V POUT = 2.5 W, 4 Ω, VDD = 5.0 V POUT = 1.4 W, 8 Ω, VDD = 5.0 V PO = 2 W into 4 Ω each channel, f = 1 kHz, VDD = 5.0 V PO = 1 W into 8 Ω each channel, f = 1 kHz, VDD = 3.6 V Efficiency η Total Harmonic Distortion + Noise THD + N Input Common-Mode Voltage Range Common-Mode Rejection Ratio Channel Separation Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio VCM CMRRGSM XTALK fSW VOOS VDD PSRR PSRRGSM Supply Current ISY Shutdown Current ISD GAIN CONTROL Closed-Loop Gain Min Typ 1.4 TBD 0.615 TBD 0.275 3.3 1.53 TBD 0.77 TBD 0.35 87 85 0.2 0.25 1.0 VCM = 2.5 V ± 100 mV at 217 Hz PO = 100 mW , f = 1 kHz VDD − 1 60 78 1.8 2.0 G = 6 dB Guaranteed from PSRR test VDD = 2.5 V to 5.0 V , 50 Hz, input floating/ground VRIPPLE = 100 mV rms at 217 Hz, inputs ac GND, CIN = 0.01 μF, input referred VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V SD = GND Max 2.5 70 5.0 Unit W W W W W W W W W W W W % % % % V dB dB MHz mV 85 70 V dB dB 7.0 6.5 5.2 20 mA mA mA nA Av0 Av1 ZIN GAIN1 = 0 V GAIN2 = VDD SD = VDD, Av0 and Av1 modes SD = GND 6 12 37.5 210 dB dB KΩ KΩ SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance VIH VIL tWU tSD ZOUT ISY ≥ 1 mA ISY ≤ 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND 1.2 0.5 30 5 >100 V V ms μs KΩ NOISE PERFORMANCE Output Voltage Noise en VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded, AV = 6 dB, A weighting POUT = 2.5 W, RL = 4 Ω 35 μV 98 dB Differential Input Impedance Signal-to-Noise Ratio SNR Rev. PrD | Page 4 of 19 Preliminary Technical Data SSM2304 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 2. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range (Soldering, 60 sec) Rating 6V VDD VDD 4 kV −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 16-lead, 3 mm × 3 mm LFCSP θJA 44 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 5 of 19 θJC 31.5 Unit °C/W SSM2304 Preliminary Technical Data 13 GND 12 OUTR+ 11 OUTR– 10 GAIN NC = NO CONNECT 06162-002 9 INR+ INR– 8 NC 7 TOP VIEW (Not to Scale) INL– 5 INL+ 4 SSM2304 NC 6 SD 3 14 VDD PIN 1 INDICATOR OUTL+ 1 OUTL– 2 15 VDD 16 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. SSM2304 LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic OUTL+ OUTL− SD INL+ INL− NC NC INR− INR+ GAIN OUTR− OUTR+ GND VDD VDD GND Description Inverting Output for Left Channel. Noninverting Output for Left Channel. Shutdown Input. Active low digital input. Noninverting Input for Left Channel. Inverting Input for Left Channel. No Connect. No Connect. Inverting Input for Right Channel. Noninverting Input for Right Channel. Gain Selection. Digital input. Noninverting Output for Right Channel. Inverting Output for Right Channel. Ground for Output Amplifiers. Power Supply for Output Amplifiers. Power Supply for Output Amplifiers. Ground for Output Amplifiers. Rev. PrD | Page 6 of 19 Preliminary Technical Data SSM2304 TYPICAL PERFORMANCE CHARACTERISTICS 100 RL = 8Ω, 33µH GAIN = 6dB VDD = 2.5V THD + N (%) 10 1 VDD = 3.6V 0.1 0.000001 0.0001 0.0000001 0.00001 0.001 0.01 0.1 1 10 OUTPUT POWER (W) Figure 6. THD + N vs. Output Power into 8 Ω, AV = 6 dB Figure 3. THD + N vs. Output Power into 4 Ω, AV = 12 dB 100 06162-004 VDD = 5V 0.01 100 RL = 8Ω, 33µH GAIN = 12dB VDD = 5V RL = 8Ω, 33µH 10 VDD = 2.5V 10 THD + N (%) 1 VDD = 3.6V 0.1 0.01 0.1 1W 0.25W 0.5W 0.001 0.0001 0.001 0.01 0.1 1 OUTPUT POWER (W) 10 0.0001 10 100 1k 10k 100k 06162-005 0.01 0.000001 0.00001 100k 06162-006 VDD = 5V 06162-003 FREQUENCY (Hz) Figure 4. THD + N vs. Output Power into 8 Ω, AV = 12 dB Figure 7. THD + N vs. Frequency, VDD = 5.0 V 100 VDD = 3.6V RL = 8Ω, 33µH 10 1 THD + N (%) THD + N (%) 1 500mW 0.1 0.01 125mW 250mW 0.001 0.0001 10 100 1k 10k FREQUENCY (Hz) Figure 8. THD + N vs. Frequency, VDD = 3.6 V Figure 5. THD + N vs. Output Power into 4 Ω, AV = 6 dB Rev. PrD | Page 7 of 19 SSM2304 100 Preliminary Technical Data 1.6 VDD = 2.5V RL = 8Ω, 33µH f = 1kHz GAIN = 2 RL = 8Ω, 33µH 1.4 10 THD + N (%) OUTPUT POWER (W) 1.2 1 250mW 0.1 75mW 125mW 0.01 1.0 10% 0.8 1% 0.6 0.4 0.001 1k 100k 10k FREQUENCY (Hz) 0 2.5 5.0 06162-010 100 06162-007 0.0001 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 06162-011 0.2 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) Figure 9. THD + N vs. Frequency, VDD = 2.5 V Figure 12. Maximum Output Power vs. Supply Voltage 9 8 SUPPLY CURRENT (mA) 7 6 5 4 3 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 06162-008 1 Figure 10. Supply Current vs. Supply Voltage, No Load Figure 13. Efficiency vs. Output Power into 4 Ω 12 100 90 VDD = 2.5V VDD = 3.6V 80 8 RL = 8Ω, 33µH VDD = 5V 70 EFFICIENCY (%) VDD = 5V 6 VDD = 2.5V 4 VDD = 3.6V 60 50 40 30 2 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 SHUTDOWN VOLTAGE (V) 0.8 06162-009 SHUTDOWN CURRENT (µA) 10 0 0 OUTPUT POWER (W) Figure 11. Supply Current vs. Shutdown Voltage Figure 14. Efficiency vs. Output Power into 8 Ω Rev. PrD | Page 8 of 19 Preliminary Technical Data 1.0 SSM2304 VDD = 3.6V RL = 8Ω, 33µH 0.9 POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT POWER (W) Figure 15. Power Dissipation vs. Output Power at VDD = 3.6 V 1.8 400 VDD = 5V RL = 8Ω, 33µH 1.6 RL = 8Ω, 33µH 350 VDD = 5V SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 VDD = 3.6V 250 200 VDD = 2.5V 150 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 OUTPUT POWER (W) 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 06162-014 0 300 50 0.2 06162-013 100k 1.4 OUTPUT POWER (W) Figure 16. Power Dissipation vs. Output Power at VDD = 5.0 V Figure 19. Output Power vs. Supply Current, One Channel 0 –10 –20 –30 PSRR (dB) POWER DISSIPATION (W) Figure 18. Output Power vs. Load Resistance, THD = 1% 06162-015 0 06162-012 0.1 –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k FREQUENCY (Hz) Figure 20. Power Supply Rejection Ratio vs. Frequency Figure 17. Output Power vs. Load Resistance, THD = 10% Rev. PrD | Page 9 of 19 SSM2304 –10 7 RL = 8Ω, 33µH GAIN = 6dB 5 SD INPUT 4 –30 VOLTAGE CMRR (dB) –20 –40 –50 3 2 1 –60 0 –70 –1 100 1k 10k 100k FREQUENCY (Hz) 06162-016 –80 10 OUTPUT 6 Figure 21. Common-Mode Rejection Ratio vs. Frequency –2 –20 0 20 40 60 80 100 120 140 TIME (ms) Figure 24. Turn-Off Response 0 –20 VDD = 3.6V VRIPPLE = 1V rms RL = 8Ω, 33µH CROSSTALK (dB) –40 –60 –80 –100 –140 10 100 1k 10k 100k FREQUENCY (Hz) 06162-017 –120 Figure 22. Crosstalk vs. Frequency Figure 25. Output Frequency Spectrum 7 6 5 SD INPUT 3 2 1 OUTPUT 0 –1 –2 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 TIME (ms) 06162-018 VOLTAGE 4 Figure 23. Turn-On Response Rev. PrD | Page 10 of 19 160 180 06162-019 0 Preliminary Technical Data Preliminary Technical Data SSM2304 TYPICAL APPLICATION CIRCUITS 10µF 0.1µF SSM2304 0.01µF1 RIGHT IN+ VDD INR+ INR– RIGHT IN– VDD VBATT 2.5V TO 5.0V OUTR+ GAIN CONTROL FET DRIVER MODULATOR OUTR– 0.01µF1 SD SHUTDOWN VDD GAIN 0.01µF1 LEFT IN+ INTERNAL OSCILLATOR INL+ INL– LEFT IN– BIAS GAIN OUTL+ GAIN CONTROL FET DRIVER MODULATOR OUTL– 0.01µF1 GND 06162-030 GND 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 26. Stereo Differential Input Configuration 10µF 0.1µF SSM2304 0.01µF RIGHT IN VDD VBATT 2.5V TO 5.0V VDD INR+ INR– OUTR+ GAIN CONTROL MODULATOR FET DRIVER OUTR– 0.01µF SD SHUTDOWN GAIN 0.01µF LEFT IN BIAS GAIN INTERNAL OSCILLATOR INL+ INL– OUTL+ GAIN CONTROL MODULATOR FET DRIVER OUTL– 0.01µF GND 06162-031 GND Figure 27. Stereo Single-Ended Input Configuration Rev. PrD | Page 11 of 19 SSM2304 Preliminary Technical Data APPLICATION NOTES 70 60 = HORIZONTAL = VERTICAL = REGULATION VALUE 50 40 30 20 0 0.1 1 10 100 06162-032 10 10k 06162-033 The SSM2304 stereo Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and thus reducing systems cost. The SSM2304 does not require an output filter, but instead relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square-wave output. While most Class-D amplifiers use some variation of pulse-width modulation (PWM), the SSM2304 uses a Σ-Δ modulation to determine the switching pattern of the output devices. This provides a number of important benefits. Σ-Δ modulators do not produces a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. Σ-Δ modulation provides the benefits of reducing the amplitude of spectral components at high frequencies; that is, reducing EMI emission that might otherwise be radiated by speakers and long cable traces. The SSM2304 also offers protection circuits for overcurrent and temperature protection. from 30 kHz to 2 GHz. These figures clearly describe the SSM2304 EMI behavior as being well below the FCC regulation values, starting from 100 kHz and passing beyond 1 GHz of frequency. Although the overall EMI noise floor is slightly higher, frequency spurs from the SSM2304 are greatly reduced. LEVEL (dB(µV/m)) OVERVIEW FREQUENCY (MHz) GAIN SELECTION Figure 28. EMI Emissions from SSM2304 The SSM2304 has a pair of internal resistors which set a 18dB of default gain of the amplifier. 60 = HORIZONTAL = VERTICAL = REGULATION VALUE 50 LEVEL (dB(µV/m)) It is possible to adjust the SSM2304 gain by using external resistors at the input. To set a gain lower than 18 dB refer to Error! Reference source not found. for differential input configuration and Error! Reference source not found. for single-ended configuration. The external gain configuration is calculated as 70 External Gain Settings = 300k/(37.5k+Rext) 40 30 20 The gain pin is not connected internally, therefore its external connection is not required. 10 0 10 POP-AND-CLICK SUPPRESSION 100 1k FREQUENCY (MHz) Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system, therefore as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, the following can be sources of audible transients: system power-up/ power-down, mute/unmute, input source change, and sample rate change. The SSM2304 has a pop-and-click suppression architecture that reduces this output transients, resulting in noiseless activation and deactivation. Figure 29. EMI Emissions from SSM2304 The measurements for Figure 28 and Figure 29 were taken with a 1 kHz input signal, producing 0.5 W output power into an 8 Ω load from a 3.6 V supply. Cable length was approximately 5 cm. The EMI was detected using a magnetic probe touching the 2” output trace to the load. EMI NOISE The SSM2304 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the device. Figure 28 shows SSM2304 EMI emission starting from 100 kHz to 30 MHz. Figure 29 shows SSM2304 EMI emission Rev. PrD | Page 12 of 19 Preliminary Technical Data SSM2304 LAYOUT INPUT CAPACITOR SELECTION As output power continues to increase, care needs to be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Make track widths at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines helps to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended to use a large-area ground plane for minimum impedances. Good PCB layouts also isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency ones. Properly designed multilayer printed circuit boards can reduce EMI emission and increase immunity to RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for ground plane, whereas the ground plane side of a doubleside board is often disrupted with signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes nor analog and digital power planes. The SSM2304 will not require input coupling capacitors if the input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed (Figure 26), or if using a singleended source (Figure 27). If high-pass filtering is needed at the input, the input capacitor along with the input resistor of the SSM2304 will form a high-pass filter whose corner frequency is determined by the following equation: fC = 1/(2π × RIN × CIN) Input capacitor can have very important effects on the circuit performance. Not using input capacitors degrades the output offset of the amplifier as well as the PSRR performance. PROPER POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality low ESL and low ESR capacitor—usually around 4.7 μF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 μF capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2304 helps maintain efficiency performance. Rev. PrD | Page 13 of 19 SSM2304 Preliminary Technical Data EVALUATION BOARD INFORMATION INTRODUCTION Inputs and Outputs The SSM2304 audio power amplifier is a complete low power, Class-D, stereo audio amplifier capable of delivering 2.8 W/channel into 4 Ω load. In addition to the minimal parts required for the application circuit, measurement filters are provided on the evaluation board so that conventional audio measurements can be made without additional components. 1. Ensure that the audio source is set to the minimum level. 2. Connect the audio source to Inputs INL± and INR±. 3. Connect the speakers to Outputs OUTL± and OUTR±. This section provides an overview of Analog Devices SSM2304 evaluation board. It includes a brief description of the board as well as a list of the board specifications. Table 5. SSM2304 Evaluation Board Specifications Parameter Supply Voltage Range, VDD Power Supply Current Rating Continuous Output Power, PO (RL = 4 Ω, f = 1 kHz, 22 kHz BW) Minimum Load Impedance Specification 2.5 V to 5.0 V 1.5 A 2W 4Ω OPERATION External Gain Settings It is possible to adjust the SSM2304 gain lower than 18 dB using external resistors at the input, refer to Error! Reference source not found.6 and Error! Reference source not found.7 on the product data sheet for proper circuit configuration. For external gain configuration, use the following formula: External Gain Settings = 300k/(37.5k+Rext) Shutdown Control The shutdown select header controls the shutdown function of the SSM2304. The shutdown pin on the SSM2304 is active low, meaning that a low voltage (GND) on this pin places the SSM2304 into shutdown mode. Use the following steps when operating the SSM2304 evaluation board. 1. Select jumper to 1-2 position. Shutdown pulled to VDD. 2. Select jumper to 2-3 position. Shutdown pulled to GND. Power and Ground Input Configurations 1. 1. For differential input configuration with input capacitors do not place a jumper on JP8, JP9, JP10, and JP11. 2. For differential input configuration without input capacitors place a jumper on JP8, JP9, JP10, and JP11. Set the power supply voltage between 2.5 V and 5.0 V. When connecting the power supply to the SSM2304 evaluation board, make sure to attach the ground connection to the GND header pin first and then connect the positive supply to the VDD header pin. Rev. PrD | Page 14 of 19 Preliminary Technical Data SSM2304 SSM2304 APPLICATION BOARD SCHEMATIC JP2 POWER JP8 HEADER 2 C7 0.1µF 1 2 C8 INL+ L2 FERRITE BEAD SD C9 C1 1nF JP3 1 2 OUT LEFT C2 1nF 1 OUTL– 2 OUTL+ INR– 9 1 2 OUTR– VDD OUTR+ NC GND C10 16 15 14 U1 SSM2302 L1 FERRITE BEAD GAIN 0.01µF 2 1 JP11 HEADER 2 GAIN 1 2 OUT RIGHT C4 1nF VDD R3 100kΩ C3 1nF L2 FERRITE BEAD C11 0.01µF VDD 13 VDD JP12 1 3 5 2 4 6 HEADER 13C SD R4 100kΩ Figure 30. SSM2304 Application Board Schematic Rev. PrD | Page 15 of 19 06162-034 SD INL+ VDD 12 8 GND NC GAIN 7 INL– 11 JP10 HEADER 2 6 INR+ JP9 HEADER 2 5 3 0.01µF 2 1 RIN+ 3 RIN– 2 1 RIGHT IN C5 10µF 0.01µF 4 3 2 1 LEFT IN LIN+ LIN– C6 0.1µF L1 FERRITE BEAD 10 JP1 1 2 VDD SSM2304 Preliminary Technical Data SSM2304 STEREO CLASS-D AMPLIFIER EVALUATION MODULE COMPONENT LIST Table 6. Reference C8, C9, C10, C11 C6, C7 C5 C1, C2, C3, C4 R3, R4 L1, L2, L3, L4 U1 EVAL BOARD Description Capacitors, 0.01 μF Capacitor, 0.1 μF Capacitor, 10 μF Capacitor, 1 nF Resistor, 100 kΩ Ferrite bead IC, SSM2304 PCB evaluation board Footprint 0402 0603 0805 0402 0603 0402 3.0 mm × 3.0 mm Quantity 4 2 1 4 2 4 1 1 Rev. PrD | Page 16 of 19 Manufacturer/Part Number Murata Manufacturing Co., Ltd./GRM15 Murata Manufacturing Co., Ltd./GRM18 Murata Manufacturing Co., Ltd./GRM21 Murata Manufacturing Co., Ltd./GRM15 Vishay/CRCW06031003F Murata Manufacturing Co., Ltd./BLM15EG121 SSM2304CSPZ Preliminary Technical Data SSM2304 06162-035 SSM2304 APPLICATION BOARD LAYOUT Figure 31. SSM2304 Application Board Layout Rev. PrD | Page 17 of 19 SSM2304 Preliminary Technical Data OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.45 PIN 1 INDICATOR TOP VIEW 13 12 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX 16 PIN 1 INDICATOR *1.65 1 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 0.50 0.40 0.30 1.50 SQ 1.35 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 32. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model SSM2304CPZ-REEL1 SSM2304CPZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = Pb-free part. Rev. PrD | Page 18 of 19 Package Option CP-16-3 CP-16-3 Branding A1F A1F Preliminary Technical Data SSM2304 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06162-0-7/06(PrD) Rev. PrD | Page 19 of 19