Features • • • • • • • • • • • • • • • Single-chip WiMax Transceiver @ 3.5GHz Fully Differential Design Low-IF Receiver Architecture; Requires No External Filters Self Calibration Mode for RX / TX Filters Supports Channel Bandwidths of 1.75, 3.5, and 7MHz Modulation up to 64QAM Ultra-fast Fractional-N Synthesizer Sensitivity < -68dBm @ 64-QAM, CR=¾, 7MHz BW Phase Noise Synthesizer: 0.8° (-37dBc) Low Supply Voltage: 2.7V TX Output PRF: -12 dBm RX/TX Operating Current: 200/320mA Typical Low Power Off Current: < 20µA Typical 56-lead QFN Package Low External Component Count of only a few Passives WiMax Transceiver 802.16-2004 AT86RF535A Applications • 3.5 GHz Band Wireless Communication Devices • IEEE® 802.16-2004 Radios • Supports OFDM up to 64QAM Figure 1. Preliminary AT86RF535A Block Diagram TX Power Control RX Gain Control I LNA Q Synthesizer I Driver Q Config Register CLK 5108B–WiMax–2/06 Description Atmel’s AT86RF535A is a fully integrated, low cost RF 3.5GHz Low-IF conversion transceiver for WiMax applications. It combines excellent RF performance with low current consumption at the smallest die size. The AT86RF535A chip is fabricated on the advanced AT46000 SiGe BiCMOS process. The transceiver combines LNA, PA driver, RX/TX mixer, RX/TX filters, VCO, Synthesizer, RX Gain control, and TX Power control, all fully digital controlled. The number of external components is limited to only a few devices. Quick Reference Data Table 1. Quick Reference Data Symbol Parameter FRF Input Center Frequency DFRS Frequency Resolution VDD Supply Voltage Applied to VDD pins IDDRX Supply Current Receive mode 200 mA IDDTX Supply Current Transmit mode, -5 dBm includes Balun 320 mA IDDPOFF Supply Current Power-off mode, only in “External CLK oscillator” mode 20 µA SENS Sensitivity QPSK Sensitivity 64QAM BW=1.75MHz, CR=½, S/N=9.4dB BW=7MHz, CR=¾, S/N=24.4dB PRF TX Output Power FRF= 3.5 GHz, 15dB back off for 64QAM, EVM=-34dB, includes Balun −12 dBm PN Integrated Phase Noise of Synthesizer Integrated over Frequency Range 50kHz …1MHz 0.8 deg rms TAMB Operating Ambient Temperature Note: 2 Conditions Min Typ Max Unit 3.4 3.55 3.7 GHz 39.2 Hz 3.6 V 3.0 3.3 −89 −68 −30 27 +70 dBm °C All voltages are referenced to GND. VDD=3.0V TAMB=27°C, unless otherwise noted. AT86RF535A [Preliminary] 5108B–WiMax–2/06 AT86RF535A [Preliminary] Electrical Characteristics Table 2. Symbol Receiver Characteristics(1) Parameter Conditions Min Typ Max Unit 3.4 3.55 3.7 GHz System FRF Input Center Frequency ZIN Differential Impedance at LNA Input Includes a matching inductor and two series capacitors SENS Sensitivity QPSK 1/2 Sensitivity 64QAM 3/4 BW=1.75MHz, S/N=9.4dB BW=7MHz, S/N=24.4dB PIN,MAX Maximum Input Power BW=7MHz, EVM=24.4dB NFSSB Noise Figure Single Side Band High gain mode, includes Balun w/o Frontend loss GRX,STEP RX Chain: Gain Steps 0.76 dB GRX,RANGE RX Chain: Gain Range 95.5 dB tRX/TX RX to TX Switching Time LLO-ANT LO Leakage to Antenna ACR±1 ACR±2 Ω diff. 50 −90 −69 -20 dBm dBm 4 5 dB 5 µs All gain modes, includes Balun tbd dBm Adjacent Ch. Rejection 16QAM 3/4 64QAM 3/4 −11 -4 dB Nonadjacent Ch. Rejection 16QAM 3/4 64QAM 3/4 −30 −23 dB Baseband filters, DC cancellation, RSSI, IQ outputs ROUT Output load resistance Pin to GND COUT Output load capacitance Pin to GND VOMAX Maximum Output Voltage Differential VOUT Nominal I or Q output Voltage Differential at the load specified Output buffer gain offset = 0dB Backoff –15dB relative to I or Q GB,OFFSTEP I, Q output buffer: Gain Offset Steps GB,RANGE I, Q output buffer: Gain Range 1 MΩ 10 1 V 0.141 Vrms 0.76 dB −9 +2.25 BW3dB 3-dB Bandwidth of Filter Low-IF Center Frequency: 1MHz 2MHz 4MHz Note 2 IMRR Image Rejection Ratio Note 3 −42 FIF Low-IF Frequency Note 2 1.0 2.0 4.0 CMD Common Mode IQ Voltage Note: pF 0.9 1.75 3.5 7 1.0 dB MHz −36 dB MHz 1.1 V DC 1. VDD=3.0V, TAMB=27°C, FRF=3.55 GHz, specific application circuit TBD, unless otherwise noted 2. Internally adjusted by built-in self test 3. Calibration vector access able over SPI Register 3 5108B–WiMax–2/06 Transmitter Characteristics(1) Table 3. Symbol Parameter Conditions Min Typ Max Unit 3.4 3.55 3.7 GHz System FRF Output Center Frequency ZOUT Differential Impedance at Driver Output POUT TX Output Power tTX/RX TX to RX Switching Time GPA,RANGE TX Chain Gain Control Range GLSB,STEP TX Chain Gain Control LSB Step Size For 64QAM modulated signals 50 Ω diff -12 dBm tbd 50 µs 71.9 dB 0.76 dB 1.75 3.5 7 MHz -43 dBc BW3dB 3-dB Bandwidth of Filter Low-IF Center Frequency: 1MHz 2MHz 4MHz Note 2 LCarr Carrier Leakage Note 3 EVM Error Vector Magnitude 64QAM 3/4 ZIN IQ Input Impedance Differential 10 kΩ diff VIN IQ Input Voltage Peak, Differential 1 Vp,diff VIN, DC DC Input Voltage 1.05 V Note: −34 dB 1. VDD=3.0V, TAMB=27°C, FRF=3.55 GHz, specific application circuit TBD, unless otherwise noted 2. Internally adjusted by built-in self test 3. Calibration vector access able over SPI Register. Functional Description The AT86RF535A is a fully integrated, low-cost Low-IF conversion transceiver for WiMax applications and is based on the IEEE 802.16-2004 standard. This product will provide transmit, receive, and frequency synthesis functions OFDM modulation schemes, as defined in the above specifications. It combines excellent RF performance at low current consumption. The transceiver combines LNA, PA driver, RX/TX mixer, RX/TX filters, VCO, Synthesizer, RX gain control, and TX power control, all fully digital controlled. The number of external components is limited to only a few devices. The AT86RF535A consists of a frequency-agile RF transceiver intended for use in 3.5-GHz licensed bands at data rates up to 26Mbps. Configuration and control registers and a bi-directional data communications interface to existing baseband devices from different vendors will be included. The AT86RF535A addresses the requirements of base station (BS) as well as subscriber station (SS) equipment. The device will operate down to 3.0V. The AT86RF535A is fabricated in Atmel’s AT46000 advanced SiGe BiCMOS process technology and is assembled in a 8mm x 8mm 56-lead QFN package. RX Path The differential low noise amplifier (DLNA) makes use of a differential bipolar stage with resistive emitter linearization. For digital gain control operation, the DLNA supports the four gain modes 4 AT86RF535A [Preliminary] 5108B–WiMax–2/06 AT86RF535A [Preliminary] 0, 6, 12, and 18dB. The linearity improves as the gain is reduced. The differential inphase quadraturephase mixer (IQMIX) utilizes a differential bipolar stage with emitter degeneration for the best linearity performance. A complex driving LO source was chosen for optimal LO leakage cancellation. The IQMIX has 4, 10, 16, and 22dB switchable gain. The receive poly phase filter (RXPPF) is designed as a frequency shifted leapfrog structure. The filter provides three different bandwidths at three different center frequencies. The bandwidth of this filter is tuned by built-in self test (BIST). The tuning process adjusts the cap values within the filter after power-up. The tuning can be determined via SPI. Image rejection is calibrated via SPI. Three digital controlled gain amplifiers (DGA1-3) are used to make necessary amplification available. Each stage supports the four gain modes 0, 6, 12, and 18dB. An additional fine gain stage DGB enables gain tuning of approximately ± 6dB in 0.76 dB steps. An output buffer gain offset matches the voltage swing to the respective BB input stage. The gain control is completely digital and affects LNA, MIX, and the three DGAs by using the same granularity for each stage. The BB/MAC provides the gain vector at a separate serial interface. A fast TX/RX switching is possible via TX/RX switch input pins controlled by the BB/MAC. The Low-IF conversion receiver does not have to amplify DC signals. But the gain setting produces different offsets in gain stages related to the output. To prevent signal saturation effects contribution, an offset correction takes place after each gain step. For dynamic range reasons, every stage has its individual offset correction stage. The DC feedback (DCFB) works as output offset compensation network which depends on actual gain setting. The internal gain control operation is optimized for fixed target amplitude. To adapt to different application requirements, the IQ output buffer DGB has a programmable gain offset from –1.5dB to 6dB in increments of 0.76dB. So, the nominal output voltage can be set between 180mVp and 650mVp. The gain is controllable via the register. The IQOB is able to drive a capacitive load on all four-output ports (RXI1, RXI2, RXQ1, RXQ2). The external pin CMD is an output pin, which delivers the common mode output voltage of the DGB. TX Path The transmit low pass filter (TXLP) filter is band limited concerning emission regulation and OFDM signals. So the input signal at the four-input ports (TXI1, TXI2, TXQ1, TXQ2) driving the TXLP could be a digital one but with defined levels. The complex filtered BB signal is upconverted with IQ Low-IF Upconverter IQUC. A complex driving LO source is chosen for optimal LO leakage cancellation. The output currents of the two mixer stages are added together. The resulting signal drives the power amplifier control (PAC) block. PAC is a Gilbert cell based current domain amplifier. Gain is controlled by DC voltage across the mixer core. In that way linear to dB gain control is achieved. The BB/MAC provides the gain setting vector at a separate serial interface. Synthesizer Voltage controlled oscillator (VCO) works at doubled LO frequency. This enables building complex LO phases for IQMIX and IQUC easily by using a divide by two and reduces load-pulling effects regarding DC current swing of the integrated PA. The VCO utilizes a differential doublegrounded bipolar stage as core and tank; the latter is made up of an inductive and a capacitive part in parallel. No external devices are necessary. The capacitive part consists of a digital controlled switch cap tuning array and analog controlled varactor. The main reason to use a 5 5108B–WiMax–2/06 combined analog and digital – hybrid – operating phase locked loop (Hybrid PLL) is to overcome tolerance, noise and integration problems in the VCO. Because of the course digital tuning, the analog tuning gain could be reduced so that the characteristic impedance of the loop filter increases and the charge pump current is reduced. That helps to integrate the whole active loop filter (APLL). Use of two (proportional and integral component) charge pumps and programming their currents permit changing of filter parameters. The phase interpolation divider (PDIV) is an alternate of a conventional modulus divider. It has the speed and power advantages of an asynchron divider and is programmable in a restricted range. Calibration Support Calibration of transceiver imbalances has to be performed by appendant BB/MAC processor. This processor generates corresponding control signals. The AT86RF535A contains additional analog calibration modules detecting for excellent calibration support: 1. LO signal leakage, 2. IQ signal imbalances in the TX Path, and 3. IQ signal imbalances in the RX Path. The control values will be given as analog control voltage. SPI Interface Serial peripheral interface (SPI) controls the transceiver. This 4-wire bus contains the ports SDE, SCL, SDI and SDO. The SPI has an 8-bit organization. Each transmission starts with a command byte with following structure: Table 4. SPI Interface Structure MSB CMD LSB ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 The command bit CMD is set to “1“ for WRITE operation and “0” for READ operation. The transmission continues with the data bytes. The number of data bytes depends on the register. The MSB of each data byte is sent first. Table 5. For an 8 Bit Register MSB DATA7 6 LSB DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 AT86RF535A [Preliminary] 5108B–WiMax–2/06 AT86RF535A [Preliminary] Table 6. For a 16 Bit Register MSB Figure 2. LSB DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 SPI Transmission for Multiple Bytes SDE SCL SDI SDO X X CMD ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR0 IN MSB IN LSB CMD ADR 6 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 OUT MSB OUT LSB ADR 5 7 5108B–WiMax–2/06 Pin Description & Package Drawing Table 7. Pin Description PIN PIN No. DESCRIPTION NIER 1 Interface Enable RX Gain Control Low active, input enable of the serial RX gain control interface NIET 2 Interface Enable TX Level Control Low active, input enable of the serial TX level control interface PRX 3 Power Switch of Receive Path High active, digital CMOS input levels PTX 4 Power Switch Transmit Path High active, digital CMOS input levels RFRX1 5 RF Receive Input 1 Low noise amplifier input. The 50Ω matching is, in part, the bond/package inductance and an external component (tbd). RFRX2 6 RF Receive Input 2 Complementary signal to RFRX1 VSSRFRX 7 Ground Supply of Radio Frequency Receive Circuit Modules VDDRFRX 8 Voltage Supply of Radio Frequency Receive Circuit Modules RFTX1 9 RF Transmit Output 1 P1dB up to +10dBm @ 50Ω differential 3.5GHz. The 50Ω matching is, in part, the bond/package inductance and an external component (tbd). RFTX2 10 RF Transmit Output 2 Complementary signal to RFTX1 VDDPA 11 Voltage Supply of Power Amplifier Driving Module VDDRFTX2 12 Voltage Supply of Radio Frequency Transmit Circuit Modules DTB 13 Digital Test Bus Input/Output Digital DTB input/output signal for testing purposes, connection and direction is configurable over SPI. NRES 14 Power On Reset Low active, open drain output with internal 10kΩ pull up resistor SDO 15 SPI Data Digital Output NSDE 16 SPI Enable Digital Input The rising edge of SCL and a low SDE indicate the start of a data transmission to the SPI slave SDI 17 SPI Data Digital Input Serial SPI data input stream is initiated with SDE and begins with an address byte. Input is MSB first. The MSB of the address byte is the R/W control bit. A number of data bytes follows after the address byte. The actual number of data bytes depends on the address. SCL 18 SPI Clock Digital Input At every rising edge, the SDI data is latched into the internal SPI register. SDO data change also on the rising edge. VDDSPI 19 Voltage Supply of SPI Interface Pads VDDDIG1 20 Voltage Supply of Digital Circuit Modules VSSDIG1 21 Ground Supply SPI Interface Pads and of Digital Circuit Modules 8 AT86RF535A [Preliminary] 5108B–WiMax–2/06 AT86RF535A [Preliminary] Table 7. PIN Pin Description (Continued) PIN No. DESCRIPTION VDDRFTX1 22 Voltage Supply of Radio Frequency Transmit Circuit Modules VDDBBTX 23 Voltage Supply of BB TX circuit modules BBTXQN 24 Base Band Transmit Input Q Negative Base Band transmit input signal Quad Phase BBTXQP 25 Base Band Transmit Input P Positive Complementary signal to BBTXQN BBTXIP 26 Base Band Transmit Input I Positive Base band transmit input signal In Phase BBTXIN 27 Base Band Transmit Input I Negative Complementary signal to BBTXIP EXCLE 28 External Clock Enable High active, digital CMOS input levels VDDCLK 29 Voltage Supply of CMOS Clock I/O Modules VSSCLK 30 Ground Supply of CMOS Clock I/O Modules CLK 31 32/40MHz CMOS Clock digital I/O Direction depend on XTALE VSSDIG3 32 Ground Supply of Synthesizer Divider Modules and Digital Modules VDDDIG3 33 Voltage Supply of Synthesizer Divider Modules and Digital Modules VDDXTAL 34 Voltage Supply of Crystal Circuit Modules XTAL2 35 Crystal connection 32/40MHz Analog IO VSSXTAL 36 Ground Supply of Crystal Circuit Modules XTAL1 37 Crystal connection 32/40MHz Analog IO ATB 38 Analog Test Bus Analog IO Analog output/input signal for testing purposes, connection configurable over SPI VDDCHP 39 Voltage Supply of Phase Frequency Detector and Charge Pump Modules VSSCHP 40 Ground Supply of Phase Frequency Detector and Charge Pump Modules CHPO 41 Charge Pump Current Output For external filter mode, configurable by SPI CVI 42 Control Voltage Input for external Loop Filter Configurable over SPI register VCMD 43 Common Mode Voltage Bias Output RX Elements DC output voltage 1.0V, only active if PRX=High BBRXIN 44 Base Band Receive Output I Negative In Phase output negative. The base band-processed signal is level voltage programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric BBRXIP 45 Base Band Receive Output I Positive Complementary signal to BBRXIN 9 5108B–WiMax–2/06 Table 7. Pin Description (Continued) PIN PIN No. DESCRIPTION BBRXQP 46 Base Band Receive Output Q Positive Quad Phase output positive. The base band-processed signal is voltage level programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric. BBRXQN 47 Base Band Receive Output Q Negative Complementary signal to BBRXQP VSSBBRX 48 Voltage Supply of BB Receive circuit modules VDDBBRX 49 Voltage Supply of BB Receive circuit modules VDDVCO 50 Voltage Supply of Synthesizer modules VCO and APLF VSSVCO 51 Ground Supply of Synthesizer modules VCO and APLF VDDBBIF 52 Voltage Supply of BB Interface Pads VSSDIG2 53 Ground Supply of BB Interface Pads and of Digital Circuit Modules IDA 54 Interface Data Data input of the serial gain, level and frequency control interface ICL 55 Interface Clock Clock input of the serial gain, level and frequency control interface VDDDIG2 56 Voltage Supply of Digital Circuit Modules Note: 10 Additional ground supplies are generated by down bonds to the exposed paddle. AT86RF535A [Preliminary] 5108B–WiMax–2/06 AT86RF535A [Preliminary] VSSVCO VDDVCO VDDBBRX VSSBBRX BBRXQN BBRXQP BBRXIP BBRXIN VCMD PIN51 PIN50 PIN49 PIN48 PIN47 PIN46 PIN45 PIN44 PIN43 PIN52 VSSDIG2 VDDBBIF IDA PIN54 PIN53 ICL PIN56 NIER PIN55 Pinning Information VDDDIG2 Figure 3. PIN1 PIN42 AT86RF535 CVI NIET PIN2 PIN41 CHPO PRX PIN3 PIN40 VSSCHP PTX PIN4 PIN39 VDDCHP RFRX1 PIN5 PIN38 ATB RFRX2 PIN6 PIN37 XTAL1 VSSRFRX PIN7 PIN36 VSSXTAL VDDRFRX PIN8 PIN35 XTAL2 RFTX1 PIN9 PIN34 VDDXTAL RFTX2 PIN10 PIN33 VDDDIG3 PIN11 PIN32 VSSDIG3 VDDRFTX2 PIN12 PIN31 CLK DTB PIN13 PIN30 VSSCLK PIN14 PIN29 VDDCLK VDDPA PIN25 PIN26 PIN27 PIN28 BBTXQN BBTXQP BBTXIP BBTXIN EXCLE VDDRFTX1 PIN24 PIN22 VSSDIG1 VDDBBTX PIN21 VDDDIG1 PIN23 PIN20 VDDSPI SDI PIN19 PIN17 NSDE SCL PIN16 SDO PIN18 PIN15 NRES QFN56 11 5108B–WiMax–2/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are ® and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 5108B–WiMax–2/06