Revised June 2005 74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs General Description Features The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/receiver. The device is nibble controlled. ■ Input and output interface capability to systems at 5V VCC Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVTH16240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16240 and LVTH16240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16240), also available without bushold feature (74LVT16240) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink 32 mA/64 mA ■ Functionally compatible with the 74 series 16240 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Number Package Description 74LVT16240MEA MS48A 74LVT16240MTD MTD48 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation DS012025 www.fairchildsemi.com 74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs March 1999 74LVT16240 • 74LVTH16240 Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 3-STATE Outputs Truth Table Inputs Outputs OE1 I0–I3 O0–O3 L L H L H L H X Z Inputs Outputs OE2 I4–I7 O4–O7 L L H L H H X L Z Inputs Outputs OE3 I8–I11 O8–O11 L L H L H L H X Z I12–I15 O12–O15 L L H L H L H X Z Inputs OE4 Outputs H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Functional Description The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble (4-bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage Value IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 2) VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH Level Output Current IOL LOW Level Output Current TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC Min Max Units 2.7 3.6 V 0 5.5 V 32 mA 64 mA 40 85 qC 0 10 ns/V 3.0V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC (V) Parameter TA 40qC to 85qC Min Typ Max Units Conditions (Note 10) 1.2 VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage 0.5 0.4 3.0 3.0 II(OD) Bushold Input Over-Drive 3.0 (Note 4) Current to Change State II Input Current Data Pins Power Off Leakage Current Power Up/Down 3-STATE Output Current VO t VCC 0.1V IOH 100 PA IOH 8 mA IOH 32 mA IOL 100 PA IOL 24 mA 16 mA 0.5 IOL 32 mA 0.55 IOL 75 V PA 500 PA 500 Control Pins V IOL 75 (Note 4) II VO d 0.1V or 0.2 2.7 18 mA V V V 3.0 3.0 IPU/PD 0.8 2.7 Bushold Input Minimum Drive IOFF 2.0 64 mA VI 0.8V VI 2.0V (Note 5) (Note 6) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 5 3.6 PA 1 0 r100 PA 0–1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V 3 www.fairchildsemi.com 74LVT16240 • 74LVTH16240 Absolute Maximum Ratings(Note 1) 74LVT16240 • 74LVTH16240 DC Electrical Characteristics Symbol (Continued) TA 40qC to 85qC VCC (V) Parameter Min Typ Units Max Conditions (Note 10) IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA VI GND or VCC, Outputs HIGH Power Supply Current ICCL 3.6 5 mA VI GND or VCC, Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA VI GND or VCC, Outputs Disabled ICCZH Power Supply Current 3.6 0.19 mA VI GND or VCC, VCC d VO d 5.5V, 'ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC 0.6V Outputs Disabled Other Inputs at VCC or GND (Note 7) Note 3: All typical values are at VCC 3.3V, TA 25qC. Note 4: Applies to bushold versions only (LVTH16240). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 8) VCC Parameter (V) 25qC TA Min Typ Conditions Units Max CL 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 9) 500: Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output at LOW. AC Electrical Characteristics TA Symbol 40qC to 85qC, CL Parameter Min Typ 500: 50 pF, RL 3.3V r 0.3V VCC VCC Max Min 2.7V Units Max (Note 10) tPLH Propagation Delay Data to Output tPHL tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 1.0 3.5 1.0 4.2 1.0 3.5 1.0 4.0 1.0 4.0 1.0 4.9 1.2 4.8 1.2 6.1 1.7 4.7 1.7 5.2 4.2 1.7 1.7 tOSHL Output to Output Skew tOSLH (Note 11) Note 10: All typical values are at VCC 3.3V, TA 1.0 ns ns ns 4.4 1.0 ns 25qC. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 12) Symbol Parameter Conditions CIN Input Capacitance VCC 0V, VI COUT Output Capacitance VCC 3.0V, VO Note 12: Capacitance is measured at frequency f www.fairchildsemi.com 0V or VCC 0V or VCC 1 MHz, per MIL-STD-883, Method 3012. 4 Typical Units 4 pF 8 pF 74LVT16240 • 74LVTH16240 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 5 www.fairchildsemi.com 74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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