Revised May 2005 74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs General Description Features The LCX16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The LCX16244 is designed for low voltage (2.5 or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 5V tolerant inputs and outputs ■ 2.3V to 3.6V VCC specifications provided ■ 4.5 ns tPD max, 10 PA ICCQ max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ r24 mA output drive (VCC 3.0V) ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model ! 2000V Machine model ! 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX16244G (Note 2)(Note 3) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LCX16244MEA (Note 3) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCX16244MTD (Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol GTO¥ is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS012000 www.fairchildsemi.com 74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs February 1994 74LCX16244 Connection Diagrams Pin Descriptions Pin Names Pin Assignment for SSOP and TSSOP Description OEn Output Enable Input (Active LOW) I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 OE2 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE4 OE3 NC I15 Truth Tables Inputs Pin Assignment for FBGA Outputs OE1 I0–I3 L L L L H H H X Inputs OE2 I4–I7 L L L L H H H X Z Outputs I8–I11 L L L L H H H X Z I12–I15 O12–O15 Inputs O8–O11 Outputs L L L L H H H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance 2 O4–O7 OE3 OE4 www.fairchildsemi.com Z Outputs Inputs (Top Thru View) O0–O3 puts are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. The LCX16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE out- Logic Diagram 3 www.fairchildsemi.com 74LCX16244 Functional Description 74LCX16244 Absolute Maximum Ratings(Note 4) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Value IO DC Output Source/Sink Current ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150 Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI GND V mA VO GND mA VO ! VCC mA mA mA qC Recommended Operating Conditions (Note 6) Symbol VCC Parameter VI Input Voltage VO Output Voltage IOH/IOL Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 Supply Voltage Output Current TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC 3.0V 3.6V VCC 2.7V 3.0V VCC 2.3V 2.7V 3.0V r24 r12 r8 Units V V V mA 40 85 qC 0 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage VCC TA 40qC to 85qC (V) Min 2.3 2.7 1.7 2.7 3.6 2.0 Max V 2.3 2.7 0.7 2.7 3.6 0.8 IOH 100 PA IOH 8 mA 2.3 3.6 2.3 1.8 IOH 12 mA 2.7 2.2 IOH 18 mA 3.0 2.4 2.2 V IOH 24 mA 3.0 100 PA 2.3 3.6 0.2 IOL 8 mA 2.3 0.6 IOL 12 mA 2.7 0.4 IOL 16 mA 3.0 0.4 IOL 24 mA 3.0 0.55 II Input Leakage Current 0 d VI d 5.5V 2.3 3.6 r5.0 IOZ 3-STATE Output Leakage 0 d VO d 5.5V 2.3 3.6 r5.0 0 10 IOFF Power-Off Leakage Current www.fairchildsemi.com VIH or VIL VI or VO 5.5V 4 V VCC 0.2 IOL VI Units V PA PA PA Symbol (Continued) Parameter VCC Conditions (V) ICC Quiescent Supply Current VI V CC or GND 3.6V d VI, VO d 5.5V (Note 7) 'ICC Increase in ICC per Input VIH VCC 0.6V 40qC to 85qC TA Min Units Max 2.3 3.6 20 2.3 3.6 r20 2.3 3.6 500 PA PA Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA Symbol Parameter VCC CL 40qC to 85qC, RL 500 : 3.3V r 0.3V VCC 50 pF CL 2.7V 50 pF VCC CL 2.5 r 0.2V 30 pF Min Max Min Max Min tPHL Propagation Delay 1.0 4.5 1.0 5.2 1.0 5.4 tPLH Data to Output 1.0 4.5 1.0 5.2 1.0 5.4 tPZL Output Enable Time 1.0 5.5 1.0 6.3 1.0 7.2 1.0 5.5 1.0 6.3 1.0 7.2 1.0 5.4 1.0 5.7 1.0 6.5 1.0 5.4 1.0 5.7 1.0 6.5 tPZH tPLZ Output Disable Time tPHZ tOSHL Output to Output Skew (Note 8) Max 1.0 tOSLH Units ns ns ns ns 1.0 Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL VCC Conditions TA 25qC (V) Typical CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 CL 30pF, VIH 2.5V, VIL 0V 2.5 0.6 CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 CL 30pF, VIH 2.5V, VIL 0V 2.5 0.6 Unit V V Capacitance Symbol Parameter Conditions CIN Input Capacitance VCC Open, VI COUT Output Capacitance VCC 3.3V, VI 0V or VCC CPD Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 5 0V or VCC 10 MHz Typical Units 7 pF 8 pF 20 pF www.fairchildsemi.com 74LCX16244 DC Electrical Characteristics 74LCX16244 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol www.fairchildsemi.com VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL 0.3V VOL 0.3V VOL 0.15V Vy VOH 0.3V VOH 0.3V VOH 0.15V 6 74LCX16244 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCX16244 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 8 74LCX16244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com 74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10