74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments (Top View) The 74LVC1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a A 1 B 2 5 Vcc 4 Y mixed voltage environment. The device is fully specified for GND 3 NEW PRODUCT partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow SOT25 / SOT353 when the device is powered down. The gate performs the positive Boolean function: Y = A •B or (Top View) Y = A+B A 1 6 Vcc B 2 5 NC GND 3 4 Y Features • Wide Supply Voltage Range from 1.65 to 5.5V • ± 24mA Output Drive at 3.3V • CMOS low power consumption • IOFF Supports Partial-Power-Down Mode Operation • Inputs accept up to 5.5V • ESD Protection Tested per JESD 22 DFN1410 (Note 2) Applications • • • • Exceeds 200-V Machine Model (A115-A) Exceeds 2000-V Human Body Model (A114-A) • Latch-Up Exceeds 100mA per JESD 78, Class II • Range of Package Options • Direct Interface with TTL Levels • SOT25, SOT353, and DFN1410: Assembled with “Green” • Lead Free Finish/ RoHS Compliant (Note 1) Molding Compound (no Br, Sb) Notes: Voltage Level Shifting General Purpose Logic Power Down Signal Isolation Wide array of products such as. o PCs, networking, notebooks, netbooks, PDAs o Computer peripherals, hard drives, CD/DVD ROM o TV, DVD, DVR, set top box o Cell Phones, Personal Navigation / GPS o MP3 players ,Cameras, Video Recorders 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. 2. Pin 2 and pin 5 of the DFN1410 package are internally connected. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 1 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Pin Descriptions Pin Name A Data Input B Data Input GND Ground Y NEW PRODUCT Description Data Output Vcc Supply Voltage NC No Connection Logic Diagram A B 1 4 Y 2 Function Table Inputs Output A B Y H H L L X H X L H 74LVC1G00 Document number: DS32196 Rev. 2 - 2 2 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Absolute Maximum Ratings (Note 3) Symbol Description Rating Unit 2 KV 200 V Supply Voltage Range -0.5 to 6.5 V VI Input Voltage Range -0.5 to 6.5 V Vo Voltage applied to output in high impedance or IOFF state -0.5 to 6.5 V Vo Voltage applied to output in high or low state -0.3 to VCC +0.5 V IIK Input Clamp Current VI<0 -50 mA IOK Output Clamp Current -50 mA IO Continuous output current ±50 mA Continuous current through Vdd or GND ±100 mA Operating Junction Temperature -40 to 150 °C Storage Temperature -65 to 150 °C ESD HBM Human Body Model ESD Protection ESD MM Machine Model ESD Protection NEW PRODUCT VCC TJ TSTG Notes: 3. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should be within recommend values. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 3 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Recommended Operating Conditions (Note 4) Symbol VCC Operating Voltage Parameter Operating Data retention only VCC = 1.65V to 1.95V High-level Input Voltage NEW PRODUCT VIH VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 4.5V to 5.5V Min 1.65 1.5 Low-level input voltage Unit V V 0.65 X VCC 1.7 V 2 0.7 X VCC VCC = 1.65V to 1.95V VIL Max 5.5 0.35 X VCC VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 VCC = 4.5V to 5.5V V 0.3 X VCC VI Input Voltage 0 5.5 V VO Output Voltage 0 VCC V IOH Low-level output current IOL Δt/ΔV TA Notes: High-level output current VCC = 1.65V -4 VCC = 2.3V -8 VCC = 3V -16 -24 VCC = 4.5V -32 VCC = 1.65V 4 VCC = 2.3V 8 VCC = 3V 16 24 VCC = 4.5V 32 VCC = 1.8V ± 0.15V, 2.5V ± 0.2V Input transition rise or fall VCC = 3.3V ± 0.3V rate VCC = 5V ± 0.5V Operating free-air temperature mA mA 20 10 ns/V 5 -40 85 ºC 4. Unused inputs should be held at Vcc or Ground. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 4 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Electrical Characteristics (All typical values are at Vcc = 3.3V, TA = 25°C) Over recommended free-air temperature range (unless otherwise noted) Symbol Parameter Test Conditions Vcc 1.65 V to 5.5V IOH = -100μA High Level Output Voltage NEW PRODUCT VOH IOH = -4mA 1.2 IOH = -8mA 2.3V 1.9 IOH = -16mA 3V High-level Input Voltage Typ. Max V 2.4 2.3 IOH = -32mA 4.5 V IOL = 100μA 1.65 V to 5.5V 0.1 IOL = 4mA 1.65 V 0.45 IOL = 8mA 2.3 V 0.3 IOL = 16mA 3.8 V 0.4 3V IOL = 24mA Unit VCC – 0.1 1.65 V IOH = -24mA VOL Min 0.55 IOL = 32mA 4.5 V 0.55 Input Current VI = 5.5 V or GND 0 to 5.5 V ±5 μA IOFF Power Down Leakage Current VI or VO = 5.5V 0 ± 10 μA ICC Supply Current VI = 5.5V of GND IO=0 1.65 V to 5.5V 10 μA Additional Supply Current One input at VCC – 0.6 V Other inputs at VCC or GND 3 V to 5.5V ΔICC 500 μA Ci Input Capacitance Vi = VCC – or GND SOT25 SOT353 DFN1410 SOT25 SOT353 DFN1410 3.3 II θJA Thermal Resistance Junction-to-Ambient θJC Thermal Resistance Junction-to-Case Notes: (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) 3.5 204 371 430 52 143 190 pF o C/W C/W o C/W o C/W o C/W o C/W o 5. Test condition for SOT25, SOT353, and DFN1410: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 5 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Switching Characteristics Over recommended free-air temperature range, CL = 15pF (see Figure 1) Vcc = 1.8 V Vcc = 2.5 V From TO ± 0.15V ± 0.2V Parameter (Input) (OUTPUT) Min Max Min Max A or B NEW PRODUCT tpd 2.2 Y 7.2 0.9 4.4 Vcc = 3.3 V ± 0.3V Min Max Vcc = 5 V ± 0.5V Min Max 0.8 0.8 3.8 Over recommended free-air temperature range, CL = 30 or 50pF as noted (see Figure 2) Vcc = 1.8 V Vcc = 2.5 V Vcc = 3.3 V From TO ± 0.15V ± 0.2V ± 0.3V Parameter (Input) (OUTPUT) Min Max Min Max Min Max A or B tpd Y 3.1 9.0 1.3 5.5 1.0 4.7 3.4 Vcc = 5 V ± 0.5V Min Max 1.0 4.0 Unit ns Unit ns Operating Characteristics TA = 25 ºC Parameter Cpd Power dissipation capacitance 74LVC1G00 Document number: DS32196 Rev. 2 - 2 Test Conditions Vcc = 1.8 V Vcc = 2.5 V Vcc = 3.3 V Vcc = 5 V TYP TYP TYP TYP f = 10 MHz 22 22 23 25 6 of 14 www.diodes.com Unit pF December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE NEW PRODUCT Parameter Measurement Information Inputs Vcc 1.8V±0.15V 2.5V±0.2V 3.3V±0.3V 5V±0.5V VI VCC VCC 3V VCC tr/tf ≤2ns ≤2ns ≤2.5ns ≤2.5ns VM CL RL VCC/2 VCC/2 1.5V 15pF 15pF 15pF 15pF 1MΩ 1MΩ 1MΩ 1MΩ VCC/2 Voltage Waveform Pulse Duration Voltage Waveform Propagation Delay Times Inverting and Non Inverting Outputs Figure 1. Load Circuit and Voltage Waveforms Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate ≤ 10 MHz. C. Inputs are measured separately one transition per measurement. D. tPLH and tPHL are the same as tPD. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 7 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE NEW PRODUCT Parameter Measurement Information (Continued) Inputs Vcc VI 1.8V±0.15V VCC 2.5V±0.2V VCC 3V 3.3V±0.3V 5V±0.5V VCC tr/tf ≤2ns ≤2ns ≤2.5ns ≤2.5ns VM CL RL VCC/2 30pF 1KΩ VCC/2 1.5V 30pF 500Ω 50pF 50pF 500Ω 500Ω VCC/2 Voltage Waveform Pulse Duration Voltage Waveform Propagation Delay Times Inverting and Non Inverting Outputs Figure 2. Load Circuit and Voltage Waveforms Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate ≤ 10 MHz. C. Inputs are measured separately one transition per measurement. D. tPLH and tPHL are the same as tPD. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 8 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Ordering Information 74LVC1G 00 XXX - 7 NEW PRODUCT Logic Device 74 : Logic Prefix LVC : 1.65 to 5.5V Family 1G : One gate Device 74LVC1G00W5-7 74LVC1G00SE-7 74LVC1G00FZ4-7 Notes: Package Code W5 SE FZ4 Function 00 : 2-Input NAND-Gate Packaging (Note 6) SOT25 SOT353 DFN1410 Package W5 : SOT25 SE : SOT353 FZ4 : DFN1410 Packing 7 : Tape & Reel 7” Tape and Reel Quantity Part Number Suffix 3000/Tape & Reel -7 3000/Tape & Reel -7 5000/Tape & Reel -7 6. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. 74LVC1G00 Document number: DS32196 Rev. 2 - 2 9 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Marking Information (1) SOT25 and SOT353 (Top View) 4 7 5 XX : Identification code Y : Year 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week X : A~Z : Internal code NEW PRODUCT XX Y W X 1 2 3 Part Number 74LVC1G00W5 74LVC1G00SE Package SOT25 SOT353 Identification Code US US (2) DFN1410 (Top View) XX YWX Part Number 74LVC1G00FZ4 74LVC1G00 Document number: DS32196 Rev. 2 - 2 XX : Identification Code Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week X : A~Z : Internal code Package DFN1410 10 of 14 www.diodes.com Identification Code US December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Package Outline Dimensions (All Dimensions in mm) NEW PRODUCT (1) Package Type: SOT25 (2) Package Type: SOT353 6x-0.42 CL 0.10/0.30 C L 0.40/0.45 0.65Bsc. 0.25/0.40 C L 1.8/2.2 74LVC1G00 Document number: DS32196 Rev. 2 - 2 0.1/0.22 Detail"A" 0.9/1.0 0/0.1 1.10Max. Gauge Plane Land Pattern Recommendation (unit:mm) Top View 0.25 PIN 1 0°/8 ° C L 6x-0.60 2x-0.65 1.15/1.35 2.0/2.2 C L 1.9 1.3 "A" 11 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Package Outline Dimensions (Continued) 1.35/1.45 0.550 6x-0.25 2X- NEW PRODUCT C Side View 6x-0.35 Seating Plane 0.25 A 0.08 C 0.13Typ. 0.40Max. 0.10 C 6x- 0/0.05 (3) Package Type: DFN1410 A 0.50Typ. 2X- (Pin #1 ID) X 45¢ . 1x C0 0.075¡ 0Ó.030 6x-0.25/0.35 0.95/1.05 B 4x-0.50Typ. Land Pattern Recommendation (mm) Top View 0.25 B 0.10(4x) 6x-0.15/0.25 0.10 C A B Bottom View 74LVC1G00 Document number: DS32196 Rev. 2 - 2 12 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Taping Orientation (Note 7) NEW PRODUCT For DFN1410 Notes: 7. The taping orientation of the other package type can be found on our website at http://www.diodes.com/datasheets/ap02007.pdf 74LVC1G00 Document number: DS32196 Rev. 2 - 2 13 of 14 www.diodes.com December 2010 © Diodes Incorporated 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). NEW PRODUCT Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. 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