PHILIPS SC2000

INTEGRATED CIRCUITS
DATA SHEET
SC2000
Universal Timeslot Interchange
Preliminary specification
File under Integrated Circuits
2000 Sep 07
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Package Mechanical Drawing . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SCbus/ST-BUS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Data Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bus Data Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
2
2
2
3
Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logical Pin Organization . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Physical Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Microprocessor Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Command/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Internal Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Version/Revision Register (O4H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Destination Routing Memory (80H-9FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 10
Source Routing Memory (A0H-BFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Destination Parallel Access Registers (C0H-DFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................. . . . . . . . . . . . . . . . . . . 12
Source Parallel Access Registers (E0H-FFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CRecommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. 13
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Microprocessor Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Local and Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Clock and Sync Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2000 Sep 07
2
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
• Internal support for SCbus clock
fallback
FEATURES
• Multi-time slot switching capability
for N x 64K channels (N = 1 to 32).
• Built-in SCbus message bus
interface
• Architecture optimized for the call
processing environment: SCSA ,
PEB , or MVIP compatible.
TM
• Supports both Intel® and Motorola®
processor interfaces
TM
TM
• Two software selectable expansion
bus formats:
• SCbus
TM
/ST-BUS
SC2000
• 68-pin PLCC package
• 5v CMOS technology
TM
• PEB
• Two software selectable local bus
formats:
• ST-BUS
• PEB
• Enhanced input hysteresis threshold.
• 32 x 2048 channel switch
• Serial or parallel access to the SCbus.
MC Rx data
MC Tx data
0.995 [25.27]
0.985 [25.02]
CLKFAIL
MC
CLKFAIL&
MC bus
0.800 [20.32] REF
Configuration
registers
Microprocessor Bus
Microprocessor
Interface
Parallel
Access
Registers
0.995 [25.27]
0.985 [25.02]
0.800 [20.32]
REF
Routing
Memory
SI
SO
Local
Bus
Interface
Switch
Matrix
PIN 1
INDEX
Expansion
Bus
Interface
Expansion Serial Bus
Clock in
Clock Out
Timing
Expansion Clock Out
0.048 [1.22]
0.042 [1.07]
0.056 [1.42]
0.042 [1.07]
Block Diagram
0.200 [5.08]
0.165 [4.19]
Package Mechanical Drawing
2000 Sep 07
3
0.130 [3.30]
0.090 [2.29]
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
OVERVIEW
The SC2000 is a custom VLSI circuit
optimized for use in the call processing
environment. The SC2000 provides a
cost-effective means of implementing
the interface between a high speed
internal TDM bus and an external
(expansion) TDM bus. Internal buffering allows the exchange of data between
TDM buses of different speeds and
architectures.
The SC2000 supports two external bus
formats; SCbus/ST-BUS and PEB,
and two internal bus formats; SCbus/
ST-BUS and PEB. It is compatible with
SCSA, PEB, or MVIP requirements.
SCbus operation is also compatible
with the Siemens PCM Highway.
The switching function and operational
configurations of the SC2000 are fully
software programmable. The processor
bus interface is pin configured, allowing
ease of use with a wide variety of industry-standard CPUs.
DESCRIPTION
The primary function of the SC2000 is
to exchange digital data between the
time slot on the local bus and the time
slot on the expansion bus . A microprocessor interface allows the host CPU to
define the time slots and serial streams
between which the data is exchanged.
SCbus/ST-BUS Mode
In SCbus mode the serial streams of the
external bus can be programmed to
operate at 2.048 Mbps, 4.096 Mbps or
8.192 Mbps. The local bus will always
operate at 2.048 Mbps.
The local-to-external bus switch connection is defined by the contents of the
destination routing memory. There are
32 destination routing memory locations, one corresponding to each time
slot of the local bus. The data stored in
the destination routing memory selects
the time slot and serial stream of the expansion bus to which the local bus input
(SI) will be connected.
2000 Sep 07
SC2000
The external-to-local bus switch connection is defined by the contents of the
source routing memory. There are 32
source routing memory locations, one
corresponding to each time slot of the
local bus. The data stored in the source
routing memory selects the time slot and
serial stream to which the local bus output (SO) will be connected.
Writing data into the routing memories
is synchronized with the SCbus timing
so that routing data is only changed on
frame boundaries.
All serial data is buffered in holding registers. The entire contents of the holding
register are transferred to the output
registers on frame boundaries. This
architecture introduces a constant
one-frame delay through the switch.
This constant delay allows bundled
time slots to be switched.
PEB Mode
In PEB mode the serial streams of the
external bus and the local bus may be
selected to run at either 1.544 Mbps
or 2.048 Mbps.
When PEB mode is selected, one of four
PEB configurations may be used:
1. PEB resource mode, without
switching.
2. PEB network mode, without
switching.
3. PEB resource mode, with switching.
4. PEB network mode, with switching.
When switching is not selected the serial
data is simply buffered between the local
bus and the PEB. This maintains the
data position relative to the multi-frame
sync and allows robbed-bit or CAS
signals to propagate transparently.
When switching is selected the serial
data is transferred between the local and
PEB buses via the switching matrix. The
one-frame delay that occurs requires
that robbed-bit or CAS signals be
handled specially.
4
The advantages of modes with
switching are:
• Timing delays between the local and
PEB bus are decoupled by the switch
matrix
• The local bus can access all PEB data
lines (SERR, SERT, and L_SERT)
• SO can be set to high impedance
on frame boundaries, allowing a
bi-directional local bus to be
implemented
Non-switching modes are the only configurations that support an interface
to an asynchronous PEB.
CPU Data Switching
In addition to switching local bus serial
data to and from the external bus, the
SC2000 also allows the CPU to write
data directly to the external bus. The
chip provides a frame-sync generated
interrupt which enables a group of
time slots to be accessed from the
same frame.
Internal Bus Data Switching
The Source Routing Memory Local
Connect Enable selects the switching
of data from any SI time slot to any SO
time slot. This operation introduces a
constant two-frame delay, as the data
passes through the switch twice.
Loopback Mode
The SCbus Loopback Mode electrically
isolates the SC2000 from the external
bus but still allows access to the local
bus. This mode is intended for isolating
the board from the external bus while
diagnostic tests are being run. A
CLK_IN source is required for this
mode. The recommended CLK_IN
frequencies are 2.048 MHz, 4.096
MHz, 8.192 MHz, 16.384 MHz, or
32.768 MHz.
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Additional Features
The SO output may be set to high impedance on frame boundaries by setting
the Source Routing Memory Switch
Output Enable Bit. This allows outputs
from multiple devices to be connected
to a common line. The SO signal may
also be configured as an open collector
output.
The data sample position of both local
and external buses is selectable between
50% and 75% of the bit width.
SD_1
SD_0
CLKFAIL
63
62
61
Logical and Physical Pinout Diagrams
SD_3
SD_2
66
65
SD_5
SD_6
SD_4
SD_7
67
SD_8
3
SD_9
7
4
SD_10
8
5
SD_11
9
SC2000
55
29
D_4
(FSYNCT) SCLK
57
30
D_3
(MSYNCT) RSRVD
58
10
60
31
D_2
(SERT) FSYNC*
59
SD_12
11
59
FSYNC*
32
D_1
(SIGT) CLKFAIL
61
SD_13
12
58
RSRVD
33
D_0
(L_CLKT) SD_0
62
SD_14
13
57
SCLK
(L_FSYNCT) SD_1
63
14
56
37
A_1
(L_MSYNCT) SD_2
65
SD_15
15
38
A_0
(L_TSX*) SD_3
66
MC
16
67
I*
17
RESET
18
50
CLK_IN
52
SYNC_IN
39
SI
54
TXD
SO_MS
46
SI_MS
44
SO
43
RXD
53
Physical Pinout
PLCC68
Logical Pin Organization
2000 Sep 07
5
43
47
S0
48
SI_FS
42
40
SO_FS
44
41
41
SI_CLK
45
26
40
SO_CLK
SO_MS
25
D_6
S0_CLK
16
46
S1_CLK
15
(R_SIGT) MC
24
39
(R_SERT) SD_15
SI_FS
D_7
38
13
47
S1
12
(R_TSX*) SD_14
23
A_0
(R_MSYNCT) SD_13
SO_FS
CS*
37
11
48
36
(R_FSYNCT) SD_12
CLK_IN
49
35
9
SYNC_IN
50
INT
(R_CLKT) SD_11
RXD
52
51
A_1
8
TXD
53
22
34
7
SCLKX2*
54
21
33
(SERR) SD_9
(SIGR) SD_10
55
20
RD*
32
I*(M)
WR*
31
5
D_0
4
(MSYNCR) SD_8
D_1
(FSYNCR) SD_7
RESET
D_2
17
WR*(R/W*)
19
30
18
3
D_3
20
(CLKR) SD_6
29
RD*(STRB*)
1
D_4
22
(L_SIGT) SD_5
28
CS*
27
23
SC2000
68-PIN PLCC
(TOP VIEW)
D_5
(L_SERT) SD_4
64
(CLKT) SCLKX2*
68
35
D_5
1
INT
D_6
27
2
D_7
26
6
24
SI_MS
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
PIN DESCRIPTION
Pin Name
Input/Output
D_0 - D_7
I/O
A_0, A_1
I
Pin Number
Pin Description
33, 32, 31, 30,
29, 27, 26, 24
Data bus.
These bi-directional, tri-state lines are the SC2000s interface to the CPU data bus.
38, 37
Address bus. These inputs select the internal register used by a read or write operation. Normally connected to CPU address lines
A0 and A1 in 8-bit CPU systems, or A1 and A2 in 16-bit CPU systems.
CS*
I
23
Chip Select. This active low input selects the chip for a read or write operation.
I*
I
17
Bus Interface Mode Select. This input selects Intel- and Motorola-type data bus interface configurations.
0 = Intel. 1 = Motorola.
RD*
or
I
22
STRB*
I
I* = 0. Read
This active low input enables the data bus drivers to drive the CPU data bus with the contents of the internal register selected by
A_0 and A_1.
I* = 1. Strobe
During a read operation a low on this input enables the data bus drivers to drive the CPU data bus with the contents of the internal
register selected by A_0 and A_1. During a write operation data is transferred from the CPU data bus to the register selected b y
A_0 and A_1 on a low to high transition of this signal.
WR*
or
I
20
R/W*
I
I* = 0. Write
During a write operation data is transferred from the CPU data bus to the register selected by A_0 and A_1 on a low to high
transition of this signal.
I* = 1. Read/Write
This input selects between a write operation (R/W* = 0) and a read operation (R/W* =1).
RESET
I
18
Reset.
This active high input forces all outputs to tri-state, and resets the SC2000 chip.
CLK_IN
I
50
Local clock input.
SYNC_IN
I
52
Local sync input.
SI
I
39
Serial input.
Local serial bus data input line.
SO
O
43
Serial output.
Local serial bus data output line.
TXD
I
54
Transmit data
SCbus Message Bus transmit data input line.
INT
O
35
Interrupt Request.
Active high interrupt request output line.
SCLKx2* or
CLKT
I/O
I
55
Register bit C_4 = 0. SCbus System clock x 2.
Register bit C_4 = 1. PEB Transmit clock.
SCLK or
FSYNCT
I/O
I
57
Register bit C_4 = 0. SCbus System clock.
Register bit C_4 = 1. PEB Frame sync.
RSRVD or
MSYNCT
I
I
58
Register bit C_4 = 0. SCbus Reserved.
Register bit C_4 = 1. PEB Transmit multi-frame sync.
FSYNC* or
SERT
I/O
I
59
Register bit C_4 = 0. SCbus Frame sync.
Register bit C_4 = 1. PEB Transmit serial data.
CLKFAIL
I/O
61
Register bit C_4 = 0.
SCbus Clock fail signal.
SD_0 or
L_CLKT
I/O
I/O
62
Register bit C_4 = 0. SCbus Serial data stream 0.
Register bit C_4 = 1. PEB Local resource transmit clock.
SD_1 or
L_FSYNCT
I/O
I/O
63
Register bit C_4 = 0. SCbus Serial data stream 1.
Register bit C_4 = 1. PEB Local resource transmit frame sync.
SD_2 or
L_MSYNCT
I/O
I/O
65
Register bit C_4 = 0. SCbus Serial data stream 2.
Register bit C_4 = 1. PEB Local resource multi-frame sync.
SD_3 or
L_TSX*
I/O
I/O
66
Register bit C_4 = 0. SCbus Serial data stream 3.
Register bit C_4 = 1. PEB Local resource transmit time slot enable.
2000 Sep 07
6
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
PIN DESCRIPTION (continued)
Pin Name
Pin Number
Pin Description
SD_4 or
L_SERT
Input/Output
I/O
I/O
67
Register bit C_4 = 0. SCbus Serial data stream 4.
Register bit C_4 = 1. PEB Local resource transmit serial data.
SD_5
I/O
1
Register bit C_4 = 0.
SCbus Serial data stream 5.
SD_6 or
CLKR
I/O
I/O
3
Register bit C_4 = 0. SCbus Serial data stream 6.
Register bit C_4 = 1. PEB Receive clock.
SD_7 or
FSYNCR
I/O
I/O
4
Register bit C_4 = 0. SCbus Serial data stream 7.
Register bit C_4 = 1. PEB Receive frame sync.
SD_8 or
MSYNCR
I/O
I/O
5
Register bit C_4 = 0. SCbus Serial data stream 8.
Register bit C_4 = 1. PEB Receive multi-frame sync.
SD_9 or
SERR
I/O
I/O
7
Register bit C_4 = 0. SCbus Serial data stream 9.
Register bit C_4 = 1. PEB Receive data stream.
SD_10
I/O
8
Register bit C_4 = 0.
SCbus Serial data stream 10.
SD_11
I/O
9
Register bit C_4 = 0.
SCbus Serial data stream 11.
SD_12
I/O
11
Register bit C_4 = 0.
SCbus Serial data stream 12.
SD_13
I/O
12
Register bit C_4 = 0.
SCbus Serial data stream 13.
SD_14
I/O
13
Register bit C_4 = 0.
SCbus Serial data stream 14.
SD_15
I/O
15
Register bit C_4 = 0.
SCbus Serial data stream 15.
MC
I/O
16
Register bit C_4 = 0.
SCbus Message Bus signal.
SO_CLK
O
41
Serial Output Clock.
Clock for local serial output data.
SI_CLK
O
40
Serial Input Clock.
Clock for local serial input data.
SO_FS
O
48
Serial Output Frame Sync.
Frame sync for local serial output data.
SI_FS
O
47
Serial Input Frame Sync.
Frame sync for local serial input data.
SO_MS
O
46
Serial Output Multi-frame Sync.
Multi-frame sync for local serial output data.
SI_MS
O
44
Serial Input Multi-frame Sync.
Multi-frame sync for local serial input data.
RXD
53
Receive Data. Message channel serial data output.
VDDO1 VDDO5
Power
O
2, 10, 25, 45, 60
I/O pad V DD (+5 V).
VDDI1 VDDI3
Power
19, 34, 51
Core V DD (+5 V).
VSSO1 VSSO7
Power
6, 14, 28, 42, 56,
64, 68
I/O pad VSS (GND).
VSSI1 VSSI3
Power
21, 36, 49
Core VSS (GND).
2000 Sep 07
7
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
REGISTER DESCRIPTION
Microprocessor Interface Registers
The four 8-bit Microprocessor Interface
Registers comprise the command and
control port for the SC2000.
Command/Status Register
Busy (CS_0): This bit is automatically
set to 1 when a command that requires
synchronization with the SC2000’s internal state machine has been initiated.
The bit is cleared to 0 when the command has been completed. The following commands require synchronization:
SC2000
Terminate (CS_3): Setting this bit to 1
terminates any command that requires
synchronization with the SC2000’s internal state machine. This command is
needed to complete a command when
the SC2000’s internal state machine has
stopped running due to the failure of the
system clocks. The command currently
being executed is completed asynchronously and the BUSY bit is cleared to 0.
To restore normal operation the TERMINATE bit must be explicitly cleared
to 0. This bit can be read back for verification purposes.
• Destination Routing Memory Write
Low Byte Data Register
BIT
R/W
Function
0
R/W
D_0
1
R/W
D_1
2
R/W
D_2
3
R/W
D_3
4
R/W
D_4
5
R/W
D_5
6
R/W
D_6
7
R/W
D_7
Note:
Command/Status Register
• Source Routing Memory Write
• Parallel Access Destination Write
• Parallel Access Source Read
Read (CS_1): Setting this bit to 1 initiates a read of the register pointed to
by the contents of the Internal Address
Register. Once the BUSY bit is read as
cleared to 0 the contents of the selected
register will be available in the Low Byte
and High Byte Data Registers. Once the
READ operation is complete the READ
bit is cleared automatically.
Write (CS_2): Setting this bit to 1 initiates a write to the register pointed to
by the contents of the Internal Address
Register. Once the busy bit has been
cleared to 0 the contents of the Low Byte
and High Byte Data Registers have been
transferred into the selected register.
Once the WRITE operation is completed the WRITE bit is cleared automatically.
2000 Sep 07
Bit 0 is the LSB of the byte.
High Byte Data Register
BIT
R/W
Command/Status
0
R
CS_0: Busy (S)
BIT
1
W
CS_1: Read (C)
0
R/W
2
W
CS_2: Write (C)
1
R/W
D_9
3
R/W
CS_3: Terminates (C)
2
R/W
D_10
4
CS_4: Reserved
3
R/W
D_11
5
CS_5: Reserved
4
R/W
D_12
6
CS_6: Reserved
5
R/W
D_13
CS_7: Reset (C)
6
R/W
D_14
7
R/W
D_15
7
Note:
R/W
(1) Bit 0 is the LSB of the byte.
(2) Initiating multiple commands in a
single access is not recommended.
CPU Interface Register Map
A_1
A_0
Register Name
0
0
Command/Status
0
1
Internal Address
1
0
Low Byte Data
1
1
High Byte Data
8
Note:
R/W
Function
D_8
Bit 0 is the LSB of the byte.
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Configuration Registers
Internal Register Memory Map
Configuration Register 1(00H)
Values for
Function
A_7 .. A_0 (H)
R/W
00
.
.
03
Configuration 1
.
.
Configuration 4
R/W
04
Version/Revision
R/W
05
.
.
7F
Reserved
.
.
Reserved
R/W
80
.
.
9F
Destn Routing
.
.
Destn Routing
R/W
A0
.
.
BF
Source Routing
.
.
Source Routing
R/W
C0
.
.
DF
Destn Parallel
.
.
Destn Parallel
R/W
E0
.
.
FF
Source Parallel
.
.
Source Parallel
R/W
Configuration Register 1
Reset (CS_7): Setting this bit to 1 forces
the SC2000 into its reset state, and
initializes all internal registers. This
command reproduces the function
of the RESET pin. Setting this bit to 0
returns the SC2000 to normal operation.
This bit can be read back for verification
purposes.
Internal Registers
The internal registers are accessed by
reads and writes to the Data Registers
using the address held in the Internal
Address Register.
2000 Sep 07
BIT
Function
0
C_0: Global Output Enable
1
C_1: Expansion Bus Timing
Driver Enable
2
3
C_2: Framing Mode 0
C_3:Framing Mode 1
4
C_4: Expansion Bus
Interface Select
5
C_5: SCbus Loopback Mode
6
7
C_6: PEB module Type 0
C_7:PEB Module Type 1
Note:
Framing Mode (C_3, C_2): This two-bit
field selects the number of bits per frame
(B/F), time slots per frame (TS/F) and
frames per multi-frame (F/MF) on both
the local and expansion bus.
When SCbus Mode is selected
(C_4 = 0), there is no multi-frame sync
signal available on the expansion bus.
The (00) combination of (C_3, C_2)
is invalid. In this case the internal
multi-frame sync will be free running,
and synchronous to FSYNC.
When PEB Mode is selected (C_4 = 1)
the only valid combinations of (C_3,
C_2) are (00) and (01).
These bits are cleared on RESET.
Bit 0 is the LSB of the Low Byte
Data Register.
Global Output Enable (C_0): Clearing
this bit to 0 forces all outputs to the high
impedance state, with the exception of
the microprocessor interface data bus.
Setting this bit to 1 enables all outputs.
This bit is cleared on RESET.
Expansion Bus Timing Driver
Enable (C_1): When SCbus Mode is
selected (C_4 = 0), clearing this bit to
0 disables the expansion bus timing
drivers.
Expansion Bus
C_3, C_2
B/F
TS/F
F/MF
00
193
24
12
01
256
32
16
10
512
64
16
11
1024
128
16
Local Bus
C_3, C_2
B/F
TS/F
F/MF
When PEB Resource Mode is selected
(C_6, C_4 = 01), this bit has no effect.
00
193
24
12
01
256
32
16
When PEB Network Mode is selected
(C_6, C_4 = 11), clearing this bit to 0
disables the expansion bus drivers
CLKR, L_CLKT, FSYNCR, L_FSYNCT,
MSYNCR, and L_MSYNCT. Setting this
bit to 1 enables these timing drivers.
10
256
32
16
11
256
32
16
This bit is cleared on RESET.
Expansion Bus Interface Select (C_4):
This bit selects the expansion bus interface operating mode. Clearing this bit to
0 selects SCbus Mode. Setting this bit to
1 selects PEB Mode.
This bit is cleared on RESET.
9
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SCbus Loopback Mode Select (C_5):
When SCbus Mode is selected (C_4 =
0), this bit controls the SCbus loopback.
Clearing this bit to 0 disables Loopback
Mode. Setting this bit to 1 enables Loopback Mode.
When PEB Mode is selected (C_4 = 1)
this bit has no effect.
When loopback is enabled the expansion bus timing and data bus drivers are
forced to high impedance, and the data
outputs are looped back internally to the
corresponding inputs. This mode is used
to test the SC2000 without disrupting
the operation of the SCbus.
A clock must be supplied at CLK_IN
for operation in Loopback Mode.
This bit is cleared on RESET.
PEB Module Type (C_7, C_6): When
PEB Mode is selected (C_4 = 1) this
two-bit field selects the PEB module
type.
When SCbus Mode is selected (C_4 = 0)
these bits have no effect.
These bits are cleared on RESET.
PEB Module Type
C_7, C_6
Operating Mode
00
Resource module without switching
01
Network module without switching
10
Resource module with switching
11
Network module with switching
Configuration Register 2 (01H)
Configuration Register 2
SC2000
CLK_IN Divider (C_10, C_9, C_8):
This field selects the CLK_IN division
ratio used in the generation of the system source clock.
When “CLK_IN divide by 1” and SCbus
Mode are selected and the expansion
bus timing drivers are enabled (C_10,
C_9, C_8, C_4, C_1 = 00001), then
SCLKx2* is held high and the FSYNC*
period is equal to 1 SCLK period.
C_10, C_9, C_8
000
1
001
2
010
4
011
8
100
16
101
Reserved
Timing Mode
00
Master
01
Master, MSYNCTfi
L_MSYNCT
10
Slave, MSYNCTfi
MSYNCR
11
Slave, SYNC_INfi
MSYNCR
110
Reserved
111
Reserved
Configuration Register 3
SYNC_IN Format (C_11): This bit
selects the SYNC_IN format to be either
PEB conventional or ST-BUS. If this bit
is cleared to 0 then SYNC_IN is taken to
be in the PEB conventional format. If
this bit is set to 1, SYNC_IN is taken to
be in the ST-BUS format.
In ST-BUS format the CLK_IN signal is
inverted to produce the system clock
source.
This bit is cleared on RESET.
SYNC_IN Select (C_13, C_12): This
two bit field selects the function of
the SYNC_IN input.
3
C_11: SYNC_IN Format
C_13, C_12
4
5
C_12: SYNC_IN Select 0
C_13: SYNC_IN Select 1
00
Ignored
01
Frame sync
10
Ignored
11
Multi-frame sync
These bits are cleared on RESET.
SYNC_IN Select
SYNC_IN Function
Bit 0 is the LSB of the Low Byte
Data Register.
2000 Sep 07
C_15, C_14
Configuration Register 3 (02H)
Function
Note:
PEB Network Module Timing Mode
CLK_IN Divided By
C_8: CLK_IN Divider 0
C_9: CLK_IN Divider 1
C_10: CLK_IN Divider 2
7
These bits are cleared on RESET.
CLK_IN Divider
0
1
2
C_14: PEB Network
Modul Timing Select 0
C_15: PEB Network
Modul Timing Select 1
Otherwise these bits have no effect.
These bits are cleared on RESET.
Bit
6
PEB Network Module Timing Select
(C_15, C_14): When PEB Network
Module Mode is selected (C_6, C_4,
C_1 = 111), this two bit field selects the
module timing mode.
10
Note:
Bit
Function
0
C_16: Expansion Bus Data
Sample Position
1
C_17: Local Bus Data
Sample Position
2
C_18: SCbus Output Driver
3
C_19: SO Output Driver
4
C_20: Local Bus Framing Format
5
C_21: Message Channel
TXD Select
6
7
C_22: SERT Mux 0
C_23: SERT Mux 1
Bit 0 is the LSB of the Low Byte
Data Register.
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Expansion Bus Data Sample
Position (C_16): When SCbus Mode is
selected (C_4 = 0) this bit determines
the location of the sampled point in the
bit cell. When this bit is cleared to 0,
sampling occurs at 50% of the bit width.
When this bit is set to 1, sampling occurs
at 75% of the bit width.
When PEB Mode is selected (C_4 = 1)
this bit has no effect, and data is always
sampled at the 50% point.
SCLKx2* must be present in order to
sample at the 75% point.
This bit is cleared on RESET.
Local Bus Data Sample Position
(C_17): When SCbus Mode is selected
(C_4 = 0) this bit determines the location of the sample point in the bit cell.
When this bit is cleared to 0 sampling
occurs at 50% of the bit width. When
this bit is set to 1, sampling occurs at
75% of the bit width.
When PEB Mode is selected (C_4 = 1)
this bit has no effect, and data is always
sampled at the 50% point.
SCLKx2* must be present in order to
sample at the 75% point.
This bit is cleared on RESET.
SCbus Output Driver (C_18): When
SCbus Mode is selected (C_4 = 0), this
bit determines the SCbus output driver
type. When this bit is cleared to 0, the
output drivers are configured as tri-state
type. When this bit is set to 1 the output
drivers are configured as open collector
type.
When PEB Mode is selected (C_4 = 1)
this bit has no effect. PEB outputs are
always driven open collector.
All SCbus outputs are affected by this bit
with the exception of CLKFAIL and MC,
which are always driven open collector.
This bit is cleared on RESET.
SC2000
SO Output Driver (C_19): This bit
determines the SO output driver type.
When this bit is cleared to 0 the output
drivers are configured as tri-state. When
this bit is set to 1 the output drivers are
configured as open collector.
When PEB Mode without switching
is selected (C_7, C_4 = 01) then SO is
always enabled.
This bit is cleared on RESET.
Local Bus Framing Format (C_20):
When SCbus Mode is selected
(C_4 = 0) this bit determines the local
bus framing format. When this bit is
cleared to 0 the local bus operates with
PEB conventional framing format.
When this bit is set to 1 the local bus operates with ST-BUS framing format.
When PEB Mode is selected (C_4 = 1)
this bit has no effect.
When PEB Mode is selected (C_4 = 1),
this bit has no effect. MC is not used in
PEB mode.
When a transparent buffer is selected
(C_21 = 0), the HDLC controller should
output TXD on the rising edge of
SO_CLK. When a latched buffer is
selected (C_21 = 1) the HDLC controller should output TXD on the falling
edge of SO_CLK.
This bit is cleared on RESET.
SERT Mux (C_23, C_22): When PEB
Network Mode is selected, this two bit
field selects the source of data for the local bus SO serial stream.
When SCbus Mode (C_7, C_6,
C_4 = xx0) or PEB Resource Mode
(C_7, C_6, C_4 = 001) are selected,
these bits have no effect.
PEB Data Source Stream
With ST-BUS framing format selected,
SI_CLK is replaced by C4*, SI_FS by
F0*, and SI_MS by M0*. SO_CLK,
SO_FS and SO_MS are unaffected by
the status of this bit, and continue to
output PEB conventional framing.
C_23, C_22
Data Source
00
L_SERT
01
(L_SERT* !L_TSX*)
+(SERT* L_TSX*)
Configuration Register 4 (03H)
ST-BUS Framing Format Replacements
Configuration Register 4
PEB Conventional
ST-BUS
SI_CLK
C4*
SI_FS
F0*
SI_MS
M0*
SCLKx2* must be present, or SCLK
must be at least twice the local clock
(CLK_IN) frequency for ST-BUS framing format to be used.
This bit is cleared on RESET.
Message Channel TXD Select (C_21):
When SCbus Mode is selected
(C_4 = 0) this bit determines the
configuration of the TXD input. When
this bit is cleared to 0, the TXD input
is configured as a transparent buffer.
When this bit is set to 1 the TXD input
is configured as a latched buffer.
Bit
Function
0
C_24: CLKFAIL latch
1
C_25: CFSYNC latch
2
C_26: CLKFAIL latch Clear*
3
C_27: FSYNC latch Clear*
4
C_28: CLKFAIL polarity
5
C_29: INT Mask*
6
C_30: INT polarity
7
Note:
C_31: INT ouput driver
Bit 0 is the LSB of the Low Byte
Data Register.
CLKFAIL Latch (C_24): When SCbus
Mode is selected (C_4 = 0) this bit indicates the status of the CLKFAIL latch.
0 → CLKFAIL clear
1 → CLKFAIL set
When PEB Mode is selected (C_4 = 1),
this bit is always clear.
2000 Sep 07
11
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
FSYNC Latch (C_25): When SCbus
Mode (C_4 = 0) or PEB Mode with
switching (C_7, C_4 = 11) are selected,
these bits indicate the status of the
FSYNC latch.
The status of this bit does not affect the
CLKFAIL Latch or FSYNC Latch bits
(C_24 and C_25), and these bits can still
be used to determine the status of the
two latches.
0 → FSYNC clear
1 → FSYNC set
This bit is cleared on RESET.
When a PEB Mode without switching
is selected (C_7, C_4 = 01) this bit is
always clear.
CLKFAIL Latch Clear* (C_26): This bit
resets the CLKFAIL latch. Clearing this
bit to 0 clears the CLKFAIL latch and
disables CLKFAIL interrupts. Setting
this bit to 1 enables CLKFAIL interrupts.
This bit is cleared on RESET.
FSYNC Latch Clear* (C_27): This bit
resets the FSYNC latch. Clearing this bit
to 0 clears the FSYNC latch and disables
FSYNC interrupts. Setting this bit to 1
enables FSYNC interrupts.
This bit is cleared on RESET.
CLKFAIL Polarity (C_28): This bit
controls the level of the CLKFAIL signal
which will set the CLKFAIL latch. When
this bit is cleared to 0, the CLKFAIL
latch is set when the CLKFAIL signal is
“lo” (0). When this bit is set to 1 the
CLKFAIL latch is set when the CLKFAIL
signal is “hi” (1).
The “CLKFAIL = 0” interrupt mode is
used by the new clock master to determine that clock fall back has been executed effectively. The “CLKFAIL = 1”
interrupt mode is used by the standby
clock board to detect clock failure.
This bit should only be changed when
the CLKFAIL interrupt is disabled
(C_26 = 0).
This bit is cleared on RESET.
INT Mask* (C_29): This bit controls the
interrupts generated by CLKFAIL and
FSYNC (INT = CLKFAIL + FSYNC).
When this bit is cleared to 0 all interrupts are masked. When this bit is set
to 1, interrupts are enabled.
2000 Sep 07
INT Output Polarity (C_30): This bit
controls the active level of the INT interrupt output. When this bit is cleared
to 0, then the INT output is active low.
When this bit is set to 1 then the INT
output is active high.
This bit is cleared on RESET.
INT Output Driver (C_31): This bit
controls the configuration of the INT
output driver. When this bit is cleared to
0, the INT output driver is configured as
open collector. When this bit is set to 1
the INT output driver is configured as
totem-pole.
Version/Revision Register (04H):The
Version/Revision Register is an 8-bit
read-only register used to identify the
version and revision status of a particular batch of SC2000s. It is recommended
that a test of this field be included in all
firmware interface code to ensure compatibility.
Version/Revision Register 1
BIT
Function
0
Rev 0
1
Rev 1
2
Rev 2
3
Rev 3
4
Ver 0
5
Ver 1
6
Ver 2
7
Note:
Ver 3
Bit 0 is the LSB of the Low Byte
Data Register.
The initial release of the SC2000 will be
Version/Revision = 00H.
12
Destination Routing Memory
(80H - 9FH): The Destination Routing
Memory maps time slots from the local
SI bus onto the expansion bus. Each
location in the Destination Routing
Memory corresponds to a time slot
on the local SI bus. The contents of
each location specify a time slot on
the expansion bus.
Destination Routing Memory Map
IAR
Destination Map
80H
Channel 0
81H
Channel 1
82H
Channel 2
.
.
9FH
Note:
.
.
Channel 31
IAR = Internal Address register contents.
Channel N is equivalent to time slot N
on the local SI bus.
The contents of all Destination Routing
Memory Locations are cleared on RESET.
When writing data into the Destination
Routing Memory the Low Byte Data
Register contains a 7-bit binary field
holding a time slot number, and the
High Data Byte Register contains a 4-bit
binary field holding a Port (stream)
number. Together these two fields
uniquely identify a time slot on the
expansion bus which will be the destination for data from the local SI bus.
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Time Slot Select (DR_6 .. DR_0): This
7-bit field specifies a time slot number
between 0 and 127. DR_6 is the MSB of
this field.
Destination Port Select (PEB Mode)
DR_11..DR_8
Destination Routing Memory LSB
Bit
0
1
2
3
4
5
6
7
Note:
Function
DR_0: Time slot Select 0
DR_1: Time slot Select 1
DR_2: Time slot Select 2
DR_3: Time slot Select 3
DR_4: Time slot Select 4
DR_5: Time slot Select 5
DR_6: Time slot Select 6
DR_7: Reserved
Bit 0 is the LSB of the Low Byte
Data Register.
Port Select (DR_11 .. DR_8): When
SCbus mode is selected (C_4 = 0) this
4-bit field specifies an SCbus data
stream number between 0 and 15.
DR_11 is the MSB of this field.
When a PEB Mode with switching is
selected (C_6, C_4 = 11) this 4- bit field
specifies a PEB data stream. See table for
details.
Destination Routing Memory MSB
Bit
Function
0
1
2
3
DR_8: Port Select 0
DR_9: Port Select 1
DR_10: Port Select 2
DR_11: Port Select 3
4
DR_12: Reserved
5
DR_13: Reserved
6
DR_14: Parallel Access Enable
7
DR_15: Switch Output Enable
Note:
Bit 0 is the LSB of the High Byte
Data Register.
PEB Destination
0H
L_SERT/L_TSX*
1H
SERR
2H
R_SERT/R_TSX*
3H
SERT
4H
.
.
FH
Reserved
.
.
Reserved
Parallel Access Enable (DR_14): When
this bit is cleared to 0, the SC2000 uses
the local SI bus as the source of data
for the expansion bus. When this bit is
set to 1 the SC2000 uses the contents of
the corresponding Destination Parallel
Access Register as the source of expansion bus data.
Switch Output Enable (DR_15): When
this bit is cleared to 0, the SC2000 expansion bus drivers are forced to the
high impedance state during the specified time slot period. When this bit is set
to 1 the SC2000 expansion bus drivers
drive the bus during the specified time
slot period.
Source Routing Memory (A0H - BFH):
The Source Routing Memory maps time
slots from the expansion bus onto time
slots on the local SO bus. Each location
in the Source Routing Memory
corresponds to a time slot on the
local SO bus.
The contents of all Source Routing
Memory Location are cleared on
RESET.
When writing data into the Source
Routing Memory the Low Byte Data
Register contains a 7-bit binary field
holding a time slot number, and the
High Data Byte Register contains a 4-bit
binary field holding a Port (stream)
number. Together these two fields
uniquely identify a time slot on the
expansion bus which will be used as a
source of data for a time slot on the local
SO bus.
Time slot Select (SR_6 .. SR_0): This
7-bit field specifies a time slot number
between 0 and 127. SR_6 is the MSB of
this field.
Source Routing Memory LSB
Bit
Function
0
1
2
3
4
5
6
SR_0: Time Slot Select 0
SR_1: Time Slot Select 1
SR_2: Time Slot Select 2
SR_3: Time Slot Select 3
SR_4: Time Slot Select 4
SR_5: Time Slot Select 5
SR_6: Time Slot Select 6
7
Note:
SR_7: Reserved
Bit 0 is the LSB of the Low Byte
Data Register.
Port Select (SR_11 .. SR_8): When
SCbus Mode is selected (C_4 = 0),
this 4-bit field specifies an SCbus data
stream number between 0 and 15.
SR_11 is the MSB of this field.
Source Routing Memory
IAR
Source Mapping
A0H
Channel 0
A1H
Channel 1
A2H
.
.
BFH
Note:
2000 Sep 07
SC2000
Channel 2
.
.
Channel 31
IAR = Internal Address register contents.
Channel N is equivalent to time slot N
on the local S0 bus.
13
When a PEB Mode with switching is
selected (C_6, C_4 = 11) this 4-bit field
specifies a PEB data stream as follows:
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SR_11 is the MSB of this field.
Source Routing Memory MSB
Bit
Function
0
1
2
3
SR_8: Port Select 0
SR_9: Port Select 1
SR_10: Port Select 2
SR_11: Port Select 3
4
SR_12: Reserved
5
SR_13: Reserved
6
SR_14: Local Connect Enable
7
SR_15: Switch Output Enable
Note:
Bit 0 is the LSB of the High Byte
Data Register.
PEB Mode Source Data Stream
SR_11..SR_8
Switch Output Enable (SR_15): When
this bit is cleared to 0 the local SO bus
drivers are forced to the high impedance
state during the specified time slot period. When this bit is set to 1 the local
SO bus drivers drive the bus during the
specified time slot period.
Destination Parallel Access Registers
(C0H .. DFH): If Parallel Access and
Switch Output are enabled, the device
CPU can write data to the expansion bus
via these SC2000 registers. The write
mapping is controlled by the Destination Routing Memory. The contents of
the selected Parallel Access Register will
replace the contents of the local SI bus
time slot that would otherwise have
been transferred to the expansion bus.
Source PEB Stream
0H
SERT Mux
1H
SERR
2H
R_SERT
3H
SERT
4H
.
.
FH
Reserved
.
.
Reserved
Local Connect Enable (SR_14): This bit
controls the internal connection time
slots on the local bus. When this bit is
cleared to 0 Local Connect is disabled.
When this bit is set to 1 Local Connect is
enabled and a time slot on the local SI
bus will be connected internally to a
time slot on the local SO bus.
SC2000
Destination Parallel Access Regs
Source Parallel Access Regs
IAR
SO Destination
E0H
Channel 0
E1H
Channel 1
E2H
Channel 2
.
.
FFH
Note:
IAR
SI Destination
C0H
Channel 0
C1H
Channel 1
C2H
.
.
DFH
Note:
Channel 2
.
.
Channel 31
IAR = Internal Address Register contents. Channel N is equivalent to time
slot N on the local SI bus.
When Local Connect is enabled the
Source Routing Memory Time slot
Select bits (SR_0 .. SR_6) select the
destination time slot on the local SO
bus. The contents of the Port Select
field (SR_8 .. SR_11) are ignored.
2000 Sep 07
Source Parallel Access Registers
( E0H .. FFH): The Source Parallel
Access Registers are continually loaded
with the data being written to the corresponding local SO bus time slot, irrespective of the status of the Parallel
Access Enable or Switch Output Enable
bits. If Local Connect is enabled this
data will originate from the local SI bus.
14
.
.
Channel 31
IAR = Internal Address Register contents. Channel N is equivalent to time
slot N on the local SO bus.
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Parameter
Test Conditions
Minimum
Maximum
Unit
TS
Storage temperature
-65
150
°C
VI
Input voltage
-0.5
7
V
PD
Package power dissipation
1
W
Note:
1. Voltages are with respect to ground (V SS ) unless otherwise stated.
Recommended DC Operating Conditions
Symbol
Parameter
Test Conditions
Minimum
Maximum
Unit
TA
Ambient temperature
0
70
°C
VDD
Supply voltage
4.75
5.25
V
Note:
1. Voltages are with respect to ground (V SS ) unless otherwise stated.
DC Electrical Characteristics
Symbol
Parameter
I DD
Supply (voltage) current
V IH
Input high voltage
V IL
VH YS
I LI
Input leakage current
Test Conditions
Minimum
Maximum
Unit
100
mA
2.0
VDD+0.5
V
Input low voltage
-0.5
1.0
V
Input hysteresis voltage
±0.4
V
V I = VDD or VSS
±10
µA
7
pF
CI
Input capacitance
V OH1
Output high voltage (1)
V OL1
Output low voltage (1)
I OL = 24 mA
V OH2
Output high voltage (2)
I OH = -4 mA
V OL2
Output low voltage (2)
I OL = 4 mA
I LO
Output leakage current
VO = VDD or VSS
C IO
Output or I/O capacitance
Notes:
1. VOH1, V OL1 apply to Expansion Bus Interface (SCbus/PEB) signals.
2. VOH2, VOL2 apply to all other signals.
3. Voltages are with respect to ground (VSS ) unless otherwise stated.
4. Input hysteresis voltage: indicates that when the input is interpreted as high (2.0 volts), it will be interpreted "high" until the input is dropped below 1.6
volts. Likewise, a low input will be interpreted as "low" until the input goes above 1.4 volts.
2000 Sep 07
I OH = -24 mA
2.4
V
0.4
2.4
V
V
0.4
15
V
±10
µA
7
pF
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 1.Microprocessor Interface Timing — Intel Bus Mode
t1
CS*
RD*
WR*
A_[1:0]
t2
t3
t4
t5
t7
t9
t11
t6
t12
t13
t8
t16
t15
t14
t10
t18
t17
D_[7:0]
Table 1. Microprocessor Interface Timing — Intel Bus Mode
Symbol
Parameter
Min
Typ
Max
Unit
t1
CS* setup to WR*↑
30
ns
ns
t2
CS* hold from WR* ↑
20
t3
RD* setup to CS*
10
ns
t4
RD* hold from CS*
10
ns
t5
WR* pulse width
30
ns
t6
WR* hold from CS*
10
ns
t7
A_[1:0] setup to WR* ↑
30
ns
t8
A_[1:0] hold from WR* ↑
20
ns
t9
D_[7:0] setup to WR* ↑
30
ns
t10
D_[7:0] hold from WR* ↑
20
ns
t11
RD* hold from CS*
10
ns
t12
WR* setup to CS*
10
ns
t13
WR* hold from CS*
10
ns
t14
D_[7:0] valid delay from CS*
t15
D_[7:0] valid delay from RD*
40
ns
t16
D_[7:0] valid delay from A_[1:0]
40
ns
t17
D_[7:0] float delay from CS*
25
ns
t18
D_[7:0] float delay from RD*
25
ns
Note:
1. Timing measured with 100 pF load on D_[7:0].
2000 Sep 07
40
16
ns
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 2. Microprocessor Interface Timing — Motorola Bus Mode
t1
CS*
t3
STRB*
R/W*
A_[1:0]
t2
t5
t4
t11
t6
t7
t9
t12
t13
t8
t16
t15
t14
t10
t18
t17
D_[7:0]
Table 2. Microprocessor Interface Timing — Motorola Bus Mode
Symbol
Parameter
Min
Typ
Max
Unit
t1
CS* setup to STRB*↑
30
t2
CS* hold from STRB*↑
20
ns
t3
STRB* pulse width
30
ns
t4
STRB* hold from CS*
10
ns
t5
R/W* setup to STRB*
10
ns
t6
R/W* hold from STRB*
10
ns
t7
A_[1:0] setup to STRB*↑
30
ns
t8
A_[1:0] hold from STRB* ↑
20
ns
t9
D_[7:0] setup to STRB*↑
30
ns
t10
D_[7:0] hold from STRB* ↑
20
ns
t11
STRB* hold from CS*
10
ns
t12
R/W*setup to STRB*
10
ns
t13
R/W*hold from STRB*
10
ns
t14
D_[7:0] valid delay from CS*
40
t15
D_[7:0] valid delay from STRB*
40
ns
t16
D_[7:0] valid delay from A_[1:0]
40
ns
t17
D_[7:0] float delay from CS *
25
ns
t18
D_[7:0] float delay from STRB*
25
ns
Note:
1. Timing measured with 100 pF load on D_[7:0].
2000 Sep 07
ns
17
ns
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
t1
SCLKX2*
t7
FSYNC*
t9
SI_CLK
t13
t15
MC
RXD
2000 Sep 07
t12
t16
t17
t18
t21
t20
t24
t19
t23
t22
t25
t28
t27
SD_[15:0] Input
TXD
t6
t14
SI
SD_[15:0] Output
t5
t8
t11
SI_FS,SI_MS
t3
t10
SO_CLK
SO
t2
t4
SCLK
SO_FS,SO_MS
SC2000
t26
t30
t29
t32
t31
t33
t34
t35
18
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 3. Local Bus Interface Timing — SCbus Mode (2.048 Mbps)
Symbol
Parameter
Min
Typ
Max
t1
SCLKx2* low time
122
ns
t2
SCLKx2* high time
122
ns
t3
SCLKx2* period
244
ns
t4
SCLK low time
244
ns
t5
SCLK high time
244
ns
t6
SCLK period
t7
FSYNC* setup to SCLK↑
0
ns
t8
FSYNC* hold from SCLK↑
15
ns
t9
SI_CLK ↓ delay from SCLKx2* ↓
40
t10
SI_CLK ↑ delay from SCLKx2* ↑
40
ns
t11
SO_CLK ↑ delay from SCLK ↑
40
ns
488
Unit
ns
ns
t12
SO_CLK ↓ delay from SCLK ↓
40
ns
t13
SI_FS, SI_MS ↓ delay from SCLKx2* ↑
45
ns
t14
SI_FS, SI_MS ↑ delay from SCLKx2* ↑
45
ns
t15
SO_FS, SO_MS ↑ delay from SCLK ↑
45
ns
t16
SO_FS, SO_MS ↓ delay from SCLK ↑
45
ns
t17
SO float to valid delay from SCLK↑
40
ns
t18
SO valid to valid delay from SCLK↑
40
ns
t19
SO valid to float delay from SCLK↑
25
ns
t20
SI setup to SCLK↓ (50% sample position)
0
ns
t21
SI hold from SCLK ↓ (50% sample position)
25
ns
t22
SI setup to SCLKx2*↑ (75% sample position)
0
ns
t23
SI hold from SCLKx2* ↑ (75% sample position)
25
t24
SD_[15:0] float to valid delay from SCLK↑
ns
35
ns
t25
SD_[15:0] valid to valid delay from SCLK↑
35
ns
t26
SD_[15:0] valid to float delay from SCLK↑
25
ns
t27
SD_[15:0] setup to SCLK ↓ (50% sample)
0
t28
SD_[15:0] hold from SCLK ↓ (50% sample)
25
ns
t29
SD_[15:0] setup to SCLKx2* ↑ (75% sample)
0
ns
t30
SD_[15:0] hold from SCLKx2* ↑ (75% sample)
25
ns
t31
TXD setup to SCLK↑ (registered MC)
0
ns
t32
TXD hold from SCLK↑ (registered MC)
25
t33
MC delay from SCLK↑ (registered MC)
85
ns
t34
MC delay from TXD (passed through MC
80
ns
t35
RXD delay from MC
35
ns
Notes:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.
2. MC timing measured with 200 pF, 470 Ω pullup (4.7 K Ω/10). Open collector low to high transitions include 61 ns delay from hi-Z to 2.4 V.
3. SI_CLK, SI_FS and SI_MS shown in ST-BUS framing format. When in PEB conventional framing format SI_CLK, SI_FS and SI_MS have
identical timing to SO_CLK, SO_FS and SO_MS.
4. SO shown configured as tri-state driver.
5. SO_MS, SI_MS are free-running multi-frame synchronization signals that occur once every 16 frames.
2000 Sep 07
ns
ns
19
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 4. Local Bus Interface Timing — SCbus Mode (4.096 Mbps)
t1
SCLKX2*
t4
SCLK
t8
FSYNC*
t9
SI_CLK
t13
SO
t15
t12
t14
t16
t17
t18
t21
SI
SD_[15:0] Output
t24
t28
t32
TXD
RXD
2000 Sep 07
t27
t19
t23
t20
t25
SD_[15:0] Input
MC
t6
t7
t11
SI_FS,SI_MS
t5
t3
t10
SO_CLK
SO_FS,SO_MS
t2
t22
t26
t30
t29
t31
t33
t34
t35
20
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 4. Local Bus Interface Timing — SCbus Mode (4.096 Mbps)
Symbol
Parameter
Min
Typ
Max
Unit
t1
SCLKx2* low time
61
ns
t2
SCLKx2* high time
61
ns
t3
SCLKx2* period
122
ns
t4
SCLK low time
122
ns
t5
SCLK high time
122
ns
t6
SCLK period
244
ns
t7
FSYNC* setup to SCLK ↑
0
ns
t8
FSYNC* hold from SCLK↑
15
ns
t9
SI_CLK ↓ delay from SCLK ↑
40
t10
SI_CLK ↑ delay from SCLK ↓
40
ns
t11
SO_CLK ↑ delay from SCLK ↑
40
ns
ns
ns
t12
SO_CLK ↓ delay from SCLK ↑
40
t13
SI_FS, SI_MS ↓ delay from SCLK ↓
45
ns
t14
SI_FS, SI_MS ↑ delay from SCLK ↓
45
ns
t15
SO_FS, SO_MS ↑ delay from SCLK ↑
45
ns
t16
SO_FS, SO_MS ↓ delay from SCLK ↑
45
ns
t17
SO float to valid delay from SCLK↑
40
ns
t18
SO valid to valid delay from SCLK↑
40
ns
t19
SO valid to float delay from SCLK↑
25
ns
t20
SI setup to SCLK↑ (50% sample position)
0
ns
t21
SI hold from SCLK ↑ (50% sample position)
25
ns
t22
SI setup to SCLK↓ (75% sample position)
0
ns
t23
SI hold from SCLK ↓ (75% sample position)
25
t24
SD_[15:0] float to valid delay from SCLK↑
ns
35
ns
t25
SD_[15:0] valid to valid delay from SCLK↑
35
ns
t26
SD_[15:0] valid to float delay from SCLK↑
25
ns
t27
SD_[15:0] setup to SCLK ↓ (50% sample)
0
t28
SD_[15:0] hold from SCLK ↓ (50% sample)
25
ns
t29
SD_[15:0] setup to SCLKx2* ↑ (75% sample)
0
ns
t30
SD_[15:0] hold from SCLKx2* ↑ (75% sample)
25
ns
t31
TXD setup to SCLK↑ (registered MC)
0
ns
t32
TXD hold from SCLK↑ (registered MC)
25
t33
MC delay from SCLK↑ (registered MC)
85
ns
t34
MC delay from TXD (passed through MC)
80
ns
t35
RXD delay from MC
35
ns
Notes:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.
2. MC timing measured with 200 pF, 470 Ω pullup (4.7 K Ω /10). Open collector low to high transitions include 61 ns delay from hi-Z to 2.4 V.
3. SI_CLK, SI_FS and SI_MS shown in ST-BUS framing format. When in PEB conventional framing format SI_CLK, SI_FS and SI_MS have
identical timing to SO_CLK, SO_FS and SO_MS.
4. SO shown configured as tri-state driver.
5. SO_MS, SI_MS are free-running multi-frame synchronization signals that occur once every 16 frames.
2000 Sep 07
ns
ns
21
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 5. Local Bus Interface Timing — SCbus Mode (8.192 Mbps)
t2
t1
SCLKX2*
t4
SCLK
t9
SI_CLK
t11
t13
SI_FS,SI_MS
t15
t16
t17
MC
RXD
2000 Sep 07
t18
t25
t24
t28
t27
t19
t23
t22
t21
t20
SD_[15:0] Input
TXD
t12
t14
SI
SD_[15:0] Output
t6
t10
SO_CLK
SO
t5
t8
t7
FSYNC*
SO_FS,SO_MS
t3
t26
t30
t29
t32
t31
t33
t34
t35
22
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 5.Local Bus Interface Timing — SCbus Mode (8.192 Mbps)
Symbol
Parameter
Min
Typ
Max
t1
SCLKx2* low time
30.5
ns
t2
SCLKx2* high time
30.5
ns
t3
SCLKx2* period
61
ns
t4
SCLK low time
61
ns
t5
SCLK high time
61
ns
t6
SCLK period
t7
FSYNC* setup to SCLK ↑
0
ns
t8
FSYNC* hold from SCLK ↑
15
ns
t9
SI_CLK ↓ delay from SCLK ↑
40
ns
t10
SI_CLK ↑ delay from SCLK ↑
40
ns
t11
SO_CLK↑ delay from SCLK ↑
40
ns
122
Unit
ns
t12
SO_CLK ↓delay from SCLK ↑
40
ns
t13
SI_FS, SI_MS ↓ delay from SCLK ↑
45
ns
t14
SI_FS, SI_MS ↑ delay from SCLK ↑
45
ns
t15
SO_FS, SO_MS↑ delay from SCLK ↑
45
ns
t16
SO_FS, SO_MS↓ delay from SCLK ↑
45
ns
t17
SO float to valid delay from SCLK ↑
40
ns
t18
SO valid to valid delay from SCLK ↑
40
ns
t19
SO valid to float delay from SCLK ↑
25
ns
t20
SI setup to SCLK↑ (50% sample position)
0
ns
t21
SI hold from SCLK ↑ (50% sample position)
25
ns
t22
SI setup to SCLK↑ (75% sample position)
0
ns
t23
SI hold from SCLK ↑ (75% sample position)
25
t24
SD_[15:0] float to valid delay from SCLK ↑
ns
35
ns
t25
SD_[15:0] valid to valid delay from SCLK ↑
35
ns
t26
SD_[15:0] valid to float delay from SCLK ↑
25
ns
t27
SD_[15:0] setup to SCLK↓ (50% sample)
0
t28
SD_[15:0] hold from SCLK ↓(50% sample)
25
ns
t29
SD_[15:0] setup to SCLKx2*↑ (75% sample)
0
ns
t30
SD_[15:0] hold from SCLKx2* ↑ (75% sample)
25
ns
t31
TXD setup to SCLK↑ (registered MC)
0
ns
t32
TXD hold from SCLK ↑ (registered MC)
25
t33
MC delay from SCLK ↑ (registered MC)
85
ns
t34
MC delay from TXD (passed through MC)
80
ns
t35
RXD delay from MC
35
ns
Notes:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.
2. MC timing measured with 200 pF, 470 Ω pullup (4.7 K Ω/10). Open collector low to high transitions include 61 ns delay from hi-Z to 2.4 V.
3. SI_CLK, SI_FS and SI_MS shown in ST-BUS framing format. When in PEB conventional framing format SI_CLK, SI_FS and SI_MS have
identical timing to SO_CLK, SO_FS and SO_MS.
4. SO shown configured as tri-state driver.
5. SO_MS, SI_MS are free-running multi-frame synchronization signals that occur once every 16 frames.
2000 Sep 07
ns
ns
23
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 6. Local Bus Interface Timing — PEB Resource Module Without Switching
t1
CLKR
t4
SO_CLK
t2
t3
t2
t3
t5
FSYNCR
SO_FS
MSYNCR
SO_MS
SERR
t6
t7
t8
t9
t10
SO
t1
L_CLKT
t11
SI_CLK
t13
L_FSYNCT
SI_FS
t12
t14
t15
t16
t17
t18
L_MSYNCT
SI_MS
SI
L_SERT
L_TSX*
2000 Sep 07
t19
t20
t22
t21
t23
24
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 6.Local Bus Interface Timing — PEB Resource Module Without Switching
Symbol
Parameter
Min
Typ
Max
Unit
t1a
CLKR, L_CLKT high time (1.544 Mbps)
323
ns
t1b
CLKR, L_CLKT high time (2.048 Mbps)
244
ns
t2a
CLKR, L_CLKT low time (1.544 Mbps)
323
ns
t2b
CLKR, L_CLKT low time (2.048 Mbps)
244
ns
t3a
CLKR, L_CLKT period (1.544 Mbps)
647
ns
t3b
CLKR, L_CLKT period (2.048 Mbps)
488
t4
SO_CLK ↑delay from CLKR ↑
35
ns
t5
SO_CLK ↓delay from CLKR ↓
35
ns
t6
SO_FS ↑delay from FSYNCR↑
35
ns
ns
t7
SO_FS ↓delay from FSYNCR↓
35
ns
t8
SO_MS ↑delay from MSYNCR ↑
35
ns
t9
SO_MS ↓delay from MSYNCR ↓
35
ns
t10
SO delay from SERR
35
ns
t11
SI_CLK ↑delay from L_CLKT ↑
35
ns
t12
SI_CLK ↓delay from L_CLKT ↓
35
ns
t13
L_FSYNCT setup to L_CLKT↓
5
ns
t14
L_FSYNCT hold from L_CLKT↓
15
ns
t15
SI_FS ↑delay from L_FSYNCT ↑
35
ns
t16
SI_FS ↓delay from L_FSYNCT ↓
35
ns
t17
SI_MS ↑delay from L_MSYNCT ↑
35
ns
t18
SI_MS ↓delay from L_MSYNCT ↓
35
ns
t19
L_SERT enable delay from L_CLKT ↑
70
ns
t20
L_SERT delay from SI
60
ns
t21
L_SERT disable delay from L_CLKT ↑
70
ns
t22
L_TSX* ↓ delay from L_CLKT ↑
35
ns
t23
L_TSX* ↑ delay from L_CLKT ↑
70
ns
Notes:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions
include 43 ns delay from hi-Z to 2.4 V.
2. L_TSX* occurs on time slot boundaries.
2000 Sep 07
25
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 7. Local Bus Interface Timing — PEB Network Module Without Switching
t1
L_CLKT
t4
SO_CLK
L_FSYNCT
SO_FS
L_MSYNCT
SO_MS
SERT, L_SERT
t6
t7
t8
t9
t10
t11
t2
t3
t2
t3
t5
L_TSX*
SO
t1
CLKR
t12
SI_CLK
t14
FSYNCR
SI_FS
t13
t15
t16
t17
t18
t19
MSYNCR
SI_MS
SI
SERR
2000 Sep 07
t20
t21
26
t22
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 7. Local Bus Interface Timing — PEB Network Module Without Swithing
Symbol
Parameter
Min
Typ
Max
Unit
t1a
L_CLKT, CLKR high time (1.544 Mbps)
323
ns
t1b
L_CLKT, CLKR high time (2.048 Mbps)
244
ns
t2a
L_CLKT, CLKR low time (1.544 Mbps)
323
ns
t2b
L_CLKT, CLKR low time (2.048 Mbps)
244
ns
t3a
L_CLKT, CLKR period (1.544 Mbps)
647
ns
t3b
L_CLKT, CLKR period (2.048 Mbps)
488
t4
SO_CLK↑ delay from L_CLKT ↑
35
ns
t5
SO_CLK↓ delay from L_CLKT ↓
35
ns
t6
SO_FS↑ delay from L_FSYNCT↑
35
ns
t7
SO_FS↓ delay from L_FSYNCT↓
35
ns
t8
SO_MS ↑ delay from L_MSYNCT ↑
35
ns
t9
SO_MS ↓ delay from L_MSYNCT ↓
35
ns
t10
SO delay from SERT, L_SERT
35
ns
t11
SO delay from L_TSX*
35
ns
t12
SI_CLK ↑ delay from LCLKR ↑
35
ns
35
ns
ns
t13
SI_CLK ↓ delay from L_CLKR ↓
t14
FSYNCR setup to CLKR ↓
5
ns
t15
FSYNCR hold from CLKR ↓
15
ns
t16
SI_FS ↑ delay from FSYNCR ↑
35
ns
t17
SI_FS ↓ delay from FSYNCR ↓
35
ns
t18
SI_MS ↑ delay from MSYNCR ↑
35
ns
t19
SI_MS ↓ delay from MSYNCR ↓
35
ns
t20
SERR enable delay from CLKR ↑
70
ns
t21
SERR delay from SI
60
ns
t22
SERR disable delay from CLKR ↑
70
ns
Note:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions
include 43 ns delay from hi-Z to 2.4 V.
2000 Sep 07
27
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 8. Local Bus Interface Timing — PEB Resource Module With Switching
t1
CLKR
t4
SO_CLK, SI_CLK
t6
FSYNCR
t2
t3
t5
t7
t8
t9
t10
t11
t12
t13
SO_FS, SI_FS
MSYNCR
SO_MS
L_MSYNCT
SI_MS
SO
SI
2000 Sep 07
t16
t19
t20
t21
t23
t22
t24
TSX* Output
TSX* Input
t15
t18
t17
SER Output
SER Input
t14
t25
t27
t26
28
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 8. Local Bus Interface Timing — PEB Resource Module With Switching
Symbol
Parameter
Min
Typ
Max
Unit
t1a
CLKR high time (1.544 Mbps)
323
ns
t1b
CLKR high time (2.048 Mbps)
244
ns
t2a
CLKR low time (1.544 Mbps)
323
ns
t2b
CLKR low time (2.048 Mbps)
244
ns
t3a
CLKR period (1.544 Mbps)
647
ns
t3b
CLKR period (2.048 Mbps)
488
t4
SO_CLK, SI_CLK↑ delay from CLKR ↑
35
ns
t5
SO_CLK, SI_CLK↓ delay from CLKR ↓
35
ns
t6
FSYNCR setup to CLKR ↓
5
t7
FSYNCR hold from CLKR ↓
15
t8
SO_FS, SI_FS↑ delay from FSYNCR ↑
35
ns
t9
SO_FS, SI_FS↓ delay from FSYNCR ↓
35
ns
t10
SO_MS ↑ delay from MSYNCR ↑
35
ns
t11
SO_MS ↓ delay from MSYNCR ↓
35
ns
t12
SI_MS ↑ delay from L_MSYNCT ↑
35
ns
ns
ns
ns
t13
SI_MS ↓ delay from L_MSYNCT ↓
35
ns
t14
SO float to valid delay from CLKR↑
40
ns
t15
SO valid to valid delay from CLKR ↑
40
ns
t16
SO valid to float delay from CLKR↑
25
ns
t17
SI setup to CLKR ↓
0
ns
t18
SI hold from CLKR↓
25
ns
t19
SER enable delay from CLKR↑
70
ns
t20
SER valid delay from CLKR ↑
70
ns
t21
SER disable delay from CLKR ↑
70
ns
t22
SER setup to CLKR ↓
0
ns
t23
SER hold from CLKR ↓
25
ns
t24
TSX* ↓ delay from CLKR ↑
t25
TSX* ↑ delay from CLKR ↑
t26
TSX* setup to CLKR ↓
0
ns
t27
TSX* hold from CLKR ↓
25
ns
Notes:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions
include 43 ns delay from hi-Z to 2.4 V.
2. SER = L_SERT, SERR, R_SERT, SERT.
3. TSX* = L_TSX*, R_TSX*.
2000 Sep 07
29
35
ns
70
ns
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 9. Local Bus Interface Timing — PEB Network Module With Switching
t1
CLKR
t4
SO_CLK, SI_CLK
t6
FSYNCR
t2
t3
t5
t7
t8
t9
t10
t11
t12
t13
SO_FS, SI_FS
L_MSYNCT
SO_MS
MSYNCR
SI_MS
SO
SI
2000 Sep 07
t16
t19
t20
t21
t23
t22
t24
TSX* Output
TSX* Input
t15
t18
t17
SER Output
SER Input
t14
t25
t27
t26
30
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 9. Local Bus Interface Timing — PEB Network Module With Switching
Symbol
Parameter
Min
Typ
Max
Unit
t1a
CLKR high time (1.544 Mbps)
323
ns
t1b
CLKR high time (2.048 Mbps)
244
ns
t2a
CLKR low time (1.544 Mbps)
323
ns
t2b
CLKR low time (2.048 Mbps)
244
ns
t3a
CLKR period (1.544 Mbps)
647
ns
t3b
CLKR period (2.048 Mbps)
488
t4
SO_CLK, SI_CLK↑ delay from CLKR ↑
35
ns
t5
SO_CLK, SI_CLK↓ delay from CLKR ↓
35
ns
t6
FSYNCR setup to CLKR ↓
5
t7
FSYNCR hold from CLKR ↓
15
t8
SO_FS, SI_FS↑ delay from FSYNCR ↑
35
ns
t9
SO_FS, SI_FS↓ delay from FSYNCR ↓
35
ns
ns
ns
ns
t10
SO_MS ↑ delay from L_MSYNCT ↑
35
ns
t11
SO_MS ↓ delay from L_MSYNCT ↓
35
ns
t12
SI_MS ↑ delay from MSYNCR ↑
35
ns
t13
SI_MS ↓ delay from MSYNCR ↓
35
ns
t14
SO float to valid delay from CLKR ↑
40
ns
t15
SO valid to valid delay from CLKR ↑
40
ns
t16
SO valid to float delay from CLKR ↑
25
ns
t17
SI setup to CLKR ↓
0
ns
t18
SI hold from CLKR ↓
25
ns
t19
SER enable delay from CLKR↑
70
ns
t20
SER valid delay from CLKR ↑
70
ns
t21
SER disable delay from CLKR ↑
70
ns
t22
SER setup to CLKR ↓
0
ns
t23
SER hold from CLKR ↓
25
ns
t24
TSX* ↓ delay from CLKR ↑
t25
TSX* ↑ delay from CLKR ↑
t26
TSX* setup to CLKR ↓
0
ns
t27
TSX* hold from CLKR ↓
25
ns
Notes:
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions
include 43 ns delay from hi-Z to 2.4 V.
2. SER = L_SERT, SERR, R_SERT, SERT.
3. TSX* = L_TSX*, R_TSX*.
2000 Sep 07
31
35
ns
70
ns
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 10. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider ≥4)
t1
t2
t3
CLK_IN (Conventional)
t4
SYNC_IN (Conventional)
t1
t6 t7
t5
t2
t3
CLK_IN (ST-BUS)
t8
SYNC_IN (ST-BUS)
t10b
t10a
SCLKX2*
t11b
t11a
t12b
t12a
SCLK
FSYNC*
t9
t13b
t13a
t14
t15
Table 10. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider ≥ 4)
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLK_IN period
122
ns
t2
CLK_IN high time
61
ns
t3
CLK_IN low time
61
ns
t4
SYNC_IN low setup to CLK_IN↓ (PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN ↓ (PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN↓ (PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN ↓ (PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN↓ (ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN ↓ (ST-BUS)
10
ns
t10a
SCLKx2*↓ delay from CLK_IN ↑ (PEB conventional)
25
ns
t10b
SCLKx2* ↓ delay from CLK_IN ↓ (ST-BUS)
25
ns
t11a
SCLKx2*↑ delay from CLK_IN ↑ (PEB conventional)
25
ns
t11b
SCLKx2* ↑ delay from CLK_IN ↓ (ST-BUS)
25
ns
t12a
SCLK↑ delay from CLK_IN ↑ (PEB conventional)
25
ns
t12b
SCLK ↑ delay from CLK_IN ↓ (ST-BUS)
25
ns
t13a
SCLK↓ delay from CLK_IN ↑ (PEB conventional)
25
ns
t13b
SCLK ↓ delay from CLK_IN ↓ (ST-BUS)
25
ns
t14
FSYNC* ↓ delay from SCLKx2* ↑
30
ns
t15
FSYNC* ↑ delay from SCLKx2* ↑
30
ns
Note:
1. Timing measured with 200 pF load on all SCbus outputs.
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 11. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 2)
t1
t2
t3
CLK_IN (Conventional)
t5
t7
t4
SYNC_IN (Conventional)
t1
t6
t2
t3
CLK_IN (ST-BUS)
t9
t8
SYNC_IN (ST-BUS)
t10b
t10a
SCLKX2*
t11b
t11a
t12b
t12a
SCLK
t13b
t13a
t14
t15
FSYNC*
Table 11. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 2)
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLK_IN period
244
ns
t2
CLK_IN high time
122
ns
t3
CLK_IN low time
122
ns
t4
SYNC_IN low setup to CLK_IN↓ (PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN↓ (PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN↓ (PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN↓ (PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN↓ (ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN↓ (ST-BUS)
10
t10a
SCLKx2* ↓ delay from CLK_IN ↑ (PEB conventional)
25
ns
t10b
SCLKx2* ↓ delay from CLK_IN ↓ (ST-BUS)
25
ns
ns
t11a
SCLKx2* ↑ delay from CLK_IN ↓(PEB conventional)
25
ns
t11b
SCLKx2* ↑ delay from CLK_IN ↑(ST-BUS)
25
ns
t12a
SCLK ↑ delay from CLK_IN ↑(PEB conventional)
25
ns
t12b
SCLK ↑ delay from CLK_IN ↓(ST-BUS)
25
ns
t13a
SCLK ↓ delay from CLK_IN ↑(PEB conventional)
25
ns
t13b
SCLK ↓ delay from CLK_IN ↓ (ST-BUS)
25
ns
t14
FSYNC* ↓ delay from SCLKx2* ↑
30
ns
t15
FSYNC* ↑ delay from SCLKx2* ↑
30
ns
Note:
1. Timing measured with 200 pF load on all SCbus outputs.
2000 Sep 07
33
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 12. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 1)
t1
CLK_IN (Conventional)
t2
t5
t4
SYNC_IN (Conventional)
t1
t3
t7
t6
t2
t3
CLK_IN (ST-BUS)
t9
t8
SYNC_IN (ST-BUS)
SCLKX2*
t10b
t10a
SCLK
t11b
t11a
t12
t13
FSYNC*
Table 12. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 1)
Symbol
Parameter
Min
Typ
Max
t1
CLK_IN period
488
ns
t2
CLK_IN high time
244
ns
t3
CLK_IN low time
t4
SYNC_IN low setup to CLK_IN ↓ (PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN ↓ (PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN ↓(PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN ↓ (PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN ↓ (ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN ↓ (ST-BUS)
10
t10a
SCLK↑ delay from CLK_IN ↑ (PEB conventional)
25
ns
t10b
SCLK ↑ delay from CLK_IN ↓ (ST-BUS)
25
ns
244
Unit
ns
ns
t11a
SCLK↓ delay from CLK_IN ↓ (PEB conventional)
25
ns
t11b
SCLK ↓ delay from CLK_IN ↑ (ST-BUS)
25
ns
t12
FSYNC*↓ delay from SCLK ↓
30
ns
t13
FSYNC* ↑ delay from SCLK ↓
30
ns
Note:
1. Timing measured with 200 pF load on all SCbus outputs.
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34
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 13. CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider ≥ 2)
t1
CLK_IN (Conventional)
t2
t5
t7
t4
SYNC_IN (Conventional)
t3
t6
t1
CLK_IN (ST-BUS)
t2
t3
t9
t8
SYNC_IN (ST-BUS)
t10b
t10a
t11b
t11a
CLKR, L_CLKT
t12
t13
FSYNCR, L_FSYNCT
MSYNCT
t14
t15
MSYNCR
t18
L_MSYNCT
2000 Sep 07
t19
t16
t17
35
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 13. CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider ≥ 2)
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLK_IN period
244
ns
t2
CLK_IN high time
122
ns
t3
CLK_IN low time
122
ns
t4
SYNC_IN low setup to CLK_IN↓(PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN ↓(PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN↓(PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN ↓(PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN↓ (ST-BUS)
10
ns
10
t9
SYNC_IN hold from CLK_IN ↓ (ST-BUS)
t10a
CLKR, L_CLKT↑ delay from CLK_IN ↑(PEB conventional)
60
ns
t10b
CLKR, L_CLKT ↑ delay from CLK_IN ↓ (ST-BUS)
60
ns
ns
t11a
CLKR, L_CLKT↓ delay from CLK_IN ↑(PEB conventional)
30
ns
t11b
CLKR, L_CLKT ↓ delay from CLK_IN ↓ (ST-BUS)
30
ns
t12
FSYNCR, L_FSYNCT↑ delay from CLKR ↑
70
ns
t13
FSYNCR, L_FSYNCT↓ delay from CLKR ↑
35
ns
t14
MSYNCR ↑ delay from CLKR ↑
70
ns
t15
MSYNCR ↓ delay from CLKR ↑
35
ns
t16
L_MSYNCT ↑ delay from CLKR ↑
70
ns
t17
L_MSYNCT ↓ delay from CLKR ↑
35
ns
t18
L_MSYNCT ↑ delay from MSYNCT ↑
60
ns
t19
L_MSYNCT ↓ delay from MSYNCT ↓
25
ns
Note:
1. Timing measured with 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.
2000 Sep 07
36
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 14. CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider = 1)
t1
CLK_IN (Conventional)
t2
t3
t5
SYNC_IN (Conventional)
CLK_IN (ST-BUS)
t7
t4
t6
t1
t2
t3
t9
t8
SYNC_IN (ST-BUS)
t10b
t10a
CLKR, L_CLKT
FSYNCR, L_FSYNCT
t11b
t11a
t12
t13
t14
t15
MSYNCT
MSYNCR
t18
L_MSYNCT
2000 Sep 07
t19
t16
t17
37
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 14. CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider = 1)
Symbol
Parameter
Min
Typ
Max
t1
CLK_IN period
488
ns
t2
CLK_IN high time
244
ns
t3
CLK_IN low time
t4
SYNC_IN low setup to CLK_IN↓ (PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN↓ (PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN ↓ (PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN ↓ (PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN↓ (ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN ↓ (ST-BUS)
10
t10a
CLKR, L_CLKT↑ delay from CLK_IN ↑ (PEB conventional)
t10b
CLKR, L_CLKT↑ delay from CLK_IN ↓ (ST-BUS)
60
ns
t11a
CLKR, L_CLKT↓ delay from CLK_IN ↓ (PEB conventional)
30
ns
244
Unit
ns
ns
60
ns
t11b
CLKR, L_CLKT↓ delay from CLK_IN ↑ (ST-BUS)
30
ns
t12
FSYNCR, L_FSYNCT ↑ delay from CLKR ↑
70
ns
t13
FSYNCR, L_FSYNCT ↓ delay from CLKR ↑
35
ns
t14
MSYNCR ↑ delay from CLKR ↑
70
ns
t15
MSYNCR ↓ delay from CLKR ↑
35
ns
t16
L_MSYNCT ↑ delay from CLKR ↑
70
ns
t17
L_MSYNCT ↓ delay from CLKR ↑
35
ns
t18
L_MSYNCT ↑ delay from MSYNCT ↑
60
ns
t19
L_MSYNCT↓ delay from MSYNCT ↓
25
ns
Note:
1. Timing measured with 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 15. PEB Network Slave
t1
t2
t3
CLKT
t4
t5
CLKR, L_CLKT
t7
t9
t6
t8
SYNC_IN
FSYNCT
t11
t10
FSYNCR, L_FSYNCT
MSYNCT
t12
t13
t14
t15
MSYNCR
t17
t16
L_MSYNCT
Table 15: PEB Network Slave
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLKT period
488
ns
t2
CLKT high time
244
ns
t3
CLKT low time
244
t4
CLKR, L_CLKT ↑ delay from CLKT ↑
60
ns
t5
CLKR, L_CLKT ↓ delay from CLKT ↓
25
ns
t6
SYNC_IN low setup to CLKR ↓
0
ns
t7
SYNC_IN low hold from CLKR ↓
20
ns
t8
SYNC_IN high setup to CLKR ↓
0
ns
t9
SYNC_IN high hold from CLKR ↓
20
t10
FSYNCR, L_FSYNCT ↑ delay from FSYNCT ↑
ns
ns
60
ns
t11
FSYNCR, L_FSYNCT ↓ delay from FSYNCT ↓
25
ns
t12
MSYNCR ↑ delay from MSYNCT ↑
60
ns
t13
MSYNCR ↓ delay from MSYNCT↓
25
ns
t14
MSYNCR ↑ delay from CLKR ↑
70
ns
t15
MSYNCR ↓ delay from CLKR ↑
35
ns
t16
L_MSYNCT ↑ delay from MSYNCT ↑
60
ns
t17
L_MSYNCT ↓ delay from MSYNCT ↓
25
ns
Note:
1. Timing measured with 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Sep 07
42
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
NOTES
2000 Sep 07
43
Philips Semiconductors – a worldwide company
Argentina: see South America
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Middle East: see Italy
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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 70
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
02/pp44
Date of release: 2000
Sep 07
Document order number:
9397 750 07433