PHILIPS SAA3323GP

INTEGRATED CIRCUITS
DATA SHEET
SAA3323
Drive processor for DCC systems
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
FEATURES
• Operating supply voltage: 2.7 to 3.6 V
• Low power dissipation: 84 mW (typ)
• Single chip digital equalizer, tape formatting and error
correction
• 8-bit flash analog-to-digital converter (ADC) for low
symbol error rate
• Frequency and phase regulation of capstan servo
during playback
• Two switchable Infinite Impulse-Response (IIR) filter
sections
• Choice of Dynamic Random Access Memory (DRAM)
and Static Random Access Memory (SRAM) types for
system Random Access Memory (RAM)
• 10-tap Finite Impulse-Response (FIR) filter per main
data channel, with 8 bit coefficients, identical for all main
channels
• Scratch pad RAM for microcontroller in system RAM
• Integrated interface for Precision Adaptive Sub-band
Coding (PASC) data bus
• 10-tap FIR filter for the AUX channel
• Analog and digital eye outputs
• Three wire microcontroller ‘L3’ interface
• Interrupt line triggered by internal auxiliary envelope
processing e.g. label, counter, and others
• Protection against invalid auxiliary data
• Seamless joins between recordings.
• Robust programmable digital PLL clock extraction unit
• Low power SLEEP mode
GENERAL DESCRIPTION
• Slew rate limited Electromagnetic Compatibility (EMC)
friendly output
The SAA3323 performs the drive processor function in the
DCC system. This function is built up of digital equalizer,
error correction and tape formatting functions. The digital
equalizer is intended for use with DCC read amplifiers
TDA1318 or TDA1380. The tape formatting and error
correction circuit is intended for use with PASC ICs
SAA2003 and SAA2013, and write amplifiers TDA1319 or
TDA1381.
• Digital Compact Cassette (DCC) optimized error
correction
• Programmable symbol synchronization strategy for tape
input data
• Microcontroller control of capstan servo possible during
playback and recording
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
SAA3323H
80
TQFP80(1)
plastic
SOT315-1
SAA3323GP
80
QFP80(1)
plastic
SOT318-2
Note
1. When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference
Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
BLOCK DIAGRAM
handbook, full pagewidth
SAA3323
DIGITALTO-ANALOG
CONVERTER
PHASE
LOCKED
LOOP
ANAEYE
ZERO
CROSSING
FIR (1)
AUXILIARY
ENVELOPE
DETECTION
TAPE
INPUT
BUFFER
SBDIR
SBMCLK
SBEF
SBDA
SBCL
SBWS
SUB-BAND
I 2S
INTERFACE
ANALOG
TO-DIGITAL
CONVERTER
IIR (2)
EQUALIZER
MODULE
WDATA
SPEED
URDA
RESET
SLEEP
CONTROL
INTERFACE
RAM
INTERFACE
8 11
TCLOCK
TAPE
OUTPUT
BUFFER
INTERNAL DATA BUS
ERROR
CORRECTOR
RDSYNC
RDMUX
BIAS
Vref(p)
Vref(n)
L3REF
L3DATA
6
(1) FIR = Finite Impulse-Response.
(2) IIR = Infinite Impulse-Response.
Fig.1 Block diagram.
May 1994
3
L3CLK
L3MODE
PINI
L3INT
PINO2
PINO1
OEN
WEN
A0 to A10
A11 to A16
D0 to D7
MLB761
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PINNING
PIN
SYMBOL
TYPE(1)
DESCRIPTION
QFP80
TQFP80
SBWS
1
79
word select for sub-band PASC interface
I/O (1 mA)
SBCL
2
80
bit clock for sub-band PASC interface
I/O (1 mA)
SBDA
3
1
data line for sub-band PASC interface
I/O (1 mA)
SBDIR
4
2
direction line for sub-band PASC interface
O (1 mA)
SBMCLK
5
3
master clock for sub-band PASC interface
I
URDA
6
4
unreliable data
O (1 mA)
L3MODE
7
5
mode line for L3 interface
I
L3CLK
8
6
bit clock line for L3 interface
I
L3DATA
9
7
serial data line for L3 interface
I/O (2 mA)
L3INT
10
8
L3 interrupt output
O (1 mA)
VDD1
11
9
digital supply voltage
S
VSS1
12
10
digital ground
S
L3REF
13
11
L3 bus timing reference
O (1 mA)
RESET
14
12
reset SAA3323
I
SLEEP
15
13
sleep mode selection of SAA3323
I
CLK24
16
14
24.576 MHz clock input
I
AZCHK
17
15
channel 0 and channel 7 azimuth monitor
O (1 mA)
MCLK
18
16
6.144 MHz clock output
O (1 mA)
TEST3
19
17
TEST3 output; do not connect
O (1 mA)
ERCOSTAT
20
18
ERCO status, for symbol error rate measurements
O (1 mA)
OEN
21
19
output enable for RAM
O (2 mA)
A10/RAS
22
20
address SRAM; RAS DRAM
O (2 mA)
VDD2
23
21
digital supply voltage
S
VSS2
24
22
digital ground
S
D7
25
23
data SRAM
I/O (4 mA)
D6
26
24
data SRAM
I/O (4 mA)
D5
27
25
data SRAM
I/O (4 mA)
D4
28
26
data SRAM
I/O (4 mA)
D3
29
27
data SRAM; data DRAM
I/O (4 mA)
D2
30
28
data SRAM; data DRAM
I/O (4 mA)
D1
31
29
data SRAM; data DRAM
I/O (4 mA)
VDD7
32
30
digital supply voltage for RAM
S
VSS7
33
31
digital ground for RAM
S
D0
34
32
data SRAM; data DRAM
I/O (4 mA)
A0
35
33
address SRAM; address DRAM
O (2 mA)
A1
36
34
address SRAM; address DRAM
O (2 mA)
A2
37
35
address SRAM; address DRAM
O (2 mA)
A3
38
36
address SRAM; address DRAM
O (2 mA)
May 1994
4
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PIN
SYMBOL
TYPE(1)
DESCRIPTION
QFP80
TQFP80
A4
39
37
address SRAM; address DRAM
O (2 mA)
VSS3
40
38
digital ground
S
VDD3
41
39
digital supply voltage
S
A5
42
40
address SRAM; address DRAM
O (2 mA)
A6
43
41
address SRAM; address DRAM
O (2 mA)
A7
44
42
address SRAM; address DRAM
O (2 mA)
A12/PINO5
45
43
address SRAM; Port expander output 5
O (2 mA)
A14/PINO1
46
44
address SRAM; Port expander output 1
O (2 mA)
A16/PINO3
47
45
address SRAM; Port expander output 3
O (2 mA)
A15/PINO4
48
46
address SRAM; Port expander output 4
O (2 mA)
WEN
49
47
write enable for RAM
O (2 mA)
A13/PINO2
50
48
address SRAM; Port expander output 2
O (2 mA)
A8
51
49
address SRAM; address DRAM
O (2 mA)
VDD4
52
50
digital supply voltage
S
VSS4
53
51
digital ground
S
A9/CAS
54
52
address SRAM; CAS for DRAM
O (2 mA)
A11
55
53
address SRAM
O (2 mA)
SPEED
56
54
Pulse Width Modulation (PWM) capstan control output for deck Ot (1 mA)
PINO2
57
55
Port expander output 2
Ot (1 mA)
WDATA
58
56
serial output to write amplifier
O (1 mA)
TCLOCK
59
57
3.072 MHz clock output for tape I/O
O (1 mA)
VSS5
60
58
digital ground
S
VDD5
61
59
digital supply voltage
S
TEST2
62
60
TEST mode select; do not connect
Ipd
RDMUX
63
61
analog multiplexed input from read amplifier
IA
Vref(p)
64
62
ADC positive reference voltage
IA
Vref(n)
65
63
ADC negative reference voltage
IA
SUBSTR
66
64
substrate connection
IA
BIAS
67
65
bias current for ADC
IA
VSSA
68
66
analog ground
S
VDDA
69
67
analog supply voltage
S
ANAEYE
70
68
analog eye pattern output
OA
RDSYNC
71
69
synchronization output for read amplifier
O (1 mA)
VDD6
72
70
digital supply voltage
S
VSS6
73
71
digital ground
S
CHTST1
74
72
channel test pin 1
O (1 mA)
CHTST2
75
73
channel test pin 2
O (1 mA)
TEST0
76
74
TEST mode select; do not connect
Ipd
TEST1
77
75
TEST mode select; do not connect
Ipd
May 1994
5
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PIN
SYMBOL
TYPE(1)
DESCRIPTION
QFP80
TQFP80
PINI
78
76
Port expander input
I
PINO1
79
77
Port expander output 1
O (1 mA)
SBEF
80
78
sub-band PASC error flag line
O (1 mA)
Note
ANAEYE
VDDA
68
67
RDMUX
RDSYNC
69
61
V DD6
70
Vref(p)
V SS6
71
62
CHTST1
72
Vref(n)
CHTST2
73
63
TEST0
74
64 SUBSTR
TEST1
75
BIAS
PINI
76
65
PINO1
77
SSA
SBEF
78
V
SBWS
79
66
SBCL
handbook, full pagewidth
80
1. I = input; IA = analog input; Ipd = input with pull-down resistance; I/O = bidirectional; O = output; OA = analog output;
Ot = 3-state output; S = supply.
SBDA
1
60
TEST2
SBDIR
2
59
VDD5
SBMCLK
3
58
VSS5
URDA
4
57
TCLOCK
L3MODE
5
56
WDATA
L3CLK
6
55
PINO2
L3DATA
7
54
SPEED
L3INT
8
53
A11
V DD1
9
52
A9/CAS
V SS1
10
51
VSS4
L3REF
11
50
V DD4
RESET
12
49
A8
SLEEP
13
48
A13/PINO2
CLK24
14
47
WEN
AZCHK
15
46
A15/PINO4
MCLK
16
45
A16/PINO3
TEST3
17
44
A14/PINO1
ERCOSTAT
18
43
A12/PINO5
OEN
19
42
A7
A10/RAS
20
41
A6
36
37
38
39
40
A4
V SS3
VDD3
A5
30
V DD7
A3
29
D1
35
28
D2
A2
27
D3
A1 34
26
D4
A0 33
25
D5
32
24
D6
D0
23
D7
31
22
VSS2
V SS7
21
V DD2
SAA3323
Fig.2 Pin configuration (SOT315-1; TQFP80).
May 1994
6
MLB762
Philips Semiconductors
Preliminary specification
65 Vref(n)
66 SUBSTR
67 BIAS
68 V SSA
69 VDDA
70 ANAEYE
71 RDSYNC
72 V DD6
SAA3323
73 V SS6
74 CHTST1
75 CHTST2
76 TEST0
77 TEST1
78 PINI
handbook, full pagewidth
79 PINO1
80 SBEF
Drive processor for DCC systems
SBWS
1
64
Vref(p)
SBCL
2
63
RDMUX
SBDA
3
62
TEST2
SBDIR
4
61
VDD5
SBMCLK
5
60
V SS5
URDA
6
59
TCLOCK
L3MODE
7
58
WDATA
L3CLK
8
57
PINO2
L3DATA
9
56 SPEED
L3INT
10
55
A11
V DD1 11
54
A9/CAS
53
V SS4
52
V DD4
VSS1 12
SAA3323
48
A15/PINO4
MCLK
18
47
A16/PINO3
TEST3
19
46
A14/PINO1
ERCOSTAT
20
45
A12/PINO5
OEN
21
44
A7
A10/RAS
22
43
A6
V DD2
23
42
A5
V SS2
24
41
V DD3
7
V SS3
A4
A3
A2
A0
D0
V SS7
V DD7
D1
D2
D3
D4
D5
D6
D7
MLB763
Fig.3 Pin configuration (SOT318-2; QFP80).
May 1994
40
17
39
AZCHK
38
WEN
37
49
A1 36
16
35
CLK24
34
A13/PINO2
33
50
32
15
31
SLEEP
30
A8
29
51
28
14
27
RESET
26
13
25
L3REF
analog
output
sub-band
2
I S
R
baseband
I 2S
SFC3
SAA2003
STEREO
FILTER CODEC
ADC
SAA7366
R
WRAMP
TDA1381
WRITE AMP.
DRP
SAA2023
OR
SAA3323
DRIVE
PROCESSOR
L
analog
input
filtered I2 S
FIXED
HEAD
TAPE
RDAMP
TDA1380
READ AMP.
8
ADAS3
SAA2013
ADAPTIVE
ALLOCATION
IEC958
CAPSTAN
DRIVE
DAC
TDA1305
DIGITAL
AUDIO I/O
TDA1315
Philips Semiconductors
speed control
Drive processor for DCC systems
L
FUNCTIONAL DESCRIPTION
May 1994
RAM
41464
BUFFER
64K x 4
MECHANICS
DRIVERS
search data
analog CC
L output
AUDIO IN/OUT
PASC PROCESSOR
TAPE DRIVE PROCESSING
detect
switch
SYSTEM
MICROCONTROLLER
SAA3323
Fig.4 DCC system block diagram.
MBD620
Preliminary specification
SYSTEM CONTROL
handbook, full pagewidth
analog CC
R output
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
A simplified block diagram of the SAA3323 is shown in
Fig.1.
Table 1
Basic modes of TFE module.
MODE
EXPLANATION
DCC drive processing
DPAP
The SAA3323 provides the following functions for the DCC
drive processing.
audio and SYSINFO (main data) play;
AUX play
DPAR
audio and SYSINFO (main data) play;
AUX record
PLAYBACK MODES
DRAR
audio and SYSINFO (main data) record;
AUX record
• Analog-to-digital conversion
• Tape channel equalization
TFE REGISTERS
• Tape channel data and clock recovery
The TFE module has 8 writable and 5 readable registers
that are accessible via the L3 interface, one write register
(CMD) and four read registers (STATUS0 to STATUS3)
which are directly addressable, the other registers are
indirectly addressable via commands sent to the CMD
register. The registers are named as shown in Table 2.
• 10-to-8 demodulation
• Data placement in system RAM
• C1 and C2 error correction decoding
• Interfacing to sub-band serial PASC interface
Table 2
• Interfacing to microcontroller for SYSINFO and AUX
data
TFE register names.
REGISTER NAME
• Capstan control for tape deck.
RECORD MODES
• Interfacing to sub-band serial PASC interface
READ/WRITE
CMD
W
STATUS0
R
STATUS1
R
STATUS2
R
• C1 and C2 error correction encoding
STATUS3
R
• Formatting for tape transfer
SET0
W
• 8-to-10 modulation
SET1
W
• Interfacing to microcontroller for SYSINFO and AUX
data
SET2
W
SET3(1)
W
SPDDTY
W
BYTCNT
W
RACCNT
W
SPEED
R
• Capstan control for tape deck, programmable by
microcontroller.
SEARCH MODE
• Detection and interpretation of AUX envelope
information
Note
1. The 4 LSBs of register ‘SET3’ set RAM type (RType)
and RAM timing (RTim). See Table 3.
• AUX envelope counting
• Search speed estimation.
For normal operation the 4 MSBs of register ‘SET3’
should be logic 0.
Tape Formatting and Error (TFE) correction module
The TFE module has 3 basic modes of operation as shown
in Table 1.
May 1994
9
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
Table 3
SAA3323
RAM settings by register SET3.
RAM
Table 4
TFE data streams.
DATA STREAM NAME
REGISTER SET3
READ/WRITE
RTYPE 0
bit 0
SYSINFO
R/W
RTYPE 1
bit 1
AUXINFO
R/W
RTim 0
bit 2
Scratch pad RAM
R/W
RTim 1
bit 3
TFE ‘COMMANDS’
TFE DATA STREAMS
These are the commands that need to be sent to the TFE
in order to access the indirectly accessible registers and
the data streams, see Table 5.
The TFE module has three read/write data streams that
are accessible via the L3 interface and they are shown in
Table 4.
Table 5
TFE commands.
COMMAND BYTE
NAME
EXPLANATION
7
6
5
4
3
2
1
0
RDSPEED
0
0
0
0
0
0
0
0
read SPEED register
LDSET0
0
0
0
1
0
0
0
0
load new TFE settings register 0
LDSET1
0
0
0
1
0
0
0
1
load new TFE settings register 1
LDSET2
0
0
0
1
0
0
1
0
load new TFE settings register 2
LDSET3
0
0
0
1
0
0
1
1
load new TFE settings register 3
LDSPDDTY
0
0
0
1
0
1
0
1
load SPDDTY register
LDBYTCNT
0
0
0
1
0
1
1
1
load BYTCNT register
LDRACCNT
0
0
0
1
1
0
0
0
load RACCNT register
RDAUX
0
0
1
0
0
0
0
0
read AUXILIARY information
RDSYS
0
0
1
0
0
0
0
1
read SYSINFO
RDDRAC
Y
Z
1
0
0
0
1
0
read RAM data bytes (8 bits) from quarter YZ
RDWDRAC
Y
Z
1
0
0
0
1
1
read RAM data words (12 bits) from quarter YZ
WRAUX
0
0
1
1
0
0
0
0
write AUXILIARY information
WRSYS
0
0
1
1
0
0
0
1
write SYSINFO
WRDRAC
Y
Z
1
1
0
0
1
0
write RAM data bytes (8 bits) to quarter YZ
WRWDRAC
Y
Z
1
1
0
0
1
1
write RAM data words (12 bits) to quarter YZ
Digital equalizer module
DIGITAL EQUALIZER REGISTERS
The digital equalizer module has 2 basic modes of
operation as shown in Table 6.
The digital equalizer module has 9 write only, 3 read only
and 1 read/write register(s) that are accessible via the
L3 interface, one write register (CMD) and 2 read registers
(STATUS0 and STATUS1) which are directly addressable,
the other registers are indirectly addressable via
commands sent to the CMD register. The registers are
named as shown in Table 7.
Table 6
Basic modes of equalizer module.
MODE
EXPLANATION
Play
main data and AUX channels are
equalized
Search
only AUX channel is processed; AUX
envelope information is processed
May 1994
10
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
Table 7
SAA3323
Digital equalizer register names.
REGISTER NAME
DATA STREAMS
The digital equalizer module has one write only and one
read only data stream that are accessible via the
L3 interface and they are shown in Table 8.
READ/WRITE
CMD
W
STATUS0
R
STATUS1
R
COEFCNT
W
FCTRL
W
CHT1SEL
W
CHT2SEL
W
ANAEYE
W
AEC
Table 8
DATA STREAM NAME
R
INTMASK
W
DEQ2SET
W
CLKSET
W
Table 9
READ/WRITE
FIR coefficients to buffer bank
W
FIR coefficients from active bank
W
DIGITAL EQUALIZER “COMMANDS”
R/W
SSPD
Digital equalizer data streams.
These are the commands that need to be sent to the digital
equalizer in order to access the indirectly accessible
registers and the data streams.
Digital equalizer commands.
COMMAND BYTE
NAME
WRCOEF
EXPLANATION
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
write FIR coefficients to the digital equalizer buffer bank
RDCOEF
0
0
1
0
0
0
0
0
read FIR coefficients from the digital equalizer active bank
LDCOEFCNT
0
0
0
1
0
0
1
1
load FIR coefficient counter
LDFCTRL
0
0
0
1
0
1
0
0
load filter control register
LDT1SEL
0
0
0
1
0
1
1
0
load CHTST1 pin selection register
LDT2SEL
0
0
0
1
0
1
1
1
load CHTST2 pin selection register
LDTAEYE
0
0
0
1
1
0
0
0
load ANAEYE channel selection register
LDAEC
0
0
0
1
1
0
0
1
load AEC counter
RDAEC
0
0
1
0
0
0
1
0
read AEC counter
RDSSPD
0
0
1
0
0
1
0
0
read SEARCH speed register
LDINTMSK
0
0
0
1
0
0
1
0
load interrupt mask register
LDDEQ3SET
0
0
0
1
0
0
0
0
load digital equalizer settings register
LDCLKSET
0
0
0
1
0
0
0
1
load PLL clock extraction settings register
Table 10 Filter control register.
BIT
7
6
5
4
3
2
Meaning
−
−
−
µCS(1)
SH1
SH0
Default
0
0
0
0
1
0
1
0
Reserved
1
1
Note
1. µCS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time
that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient
number 9 has been received.
May 1994
11
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
There are 2 banks of coefficients for both the aux and the
main data channels, namely the ‘buffer’, and the ‘active’
banks. The microcontroller writes only to the ‘buffer’
banks, and reads only from the ‘active’ banks.
Table 11 SH1 and SH2 (FIR output scaling).
SH
EFFECT ON FIR OUTPUT
1
0
0
0
FIR mod 256
0
1
FIR
---------- mod 256
2
1
0
FIR
---------- mod 256
4
1
1
FIR
---------- mod 256
8
The microcontroller can poll the digital equalizer status bit
BKSW to see when the switch occurs. BKSW starts life
LOW, goes HIGH as a result of the bank switching and
goes LOW as result of the complete value of a main data
coefficient being received by the digital equalizer.
The microcontroller sets µCS HIGH before sending the
new set of aux or main data coefficients, the digital
equalizer resets it once the bank switch occurs.
The actual FIR coefficients that are used are a function of
the tape head, read amplifier and type of tape (i.e.
pre-recorded or own recorded) used, such information is
outside of the scope of this data sheet.
Transfer of FIR coefficients
For the main data channels (tracks 0 to 7) there are
10 coefficients (taps) each of 8 bits, where all of the data
channels make use of the same coefficients. The
addresses for the main data coefficients 0 to 9 are
0 to 9dec respectively.
Coefficient address counter (COEFCNT)
This 5 bit counter is used to point to the FIR coefficient to
be transferred to or from the digital equalizer.
There are ten coefficients (taps) each of 8 bits for the aux
channel (CHAUX). The addresses for the auxiliary
coefficients 0 to 9 are 16 to 25dec respectively.
Table 12 Coefficient address counter.
BIT
7
6
5
4
3
2
1
0
Meaning
−
−
−
CC4
CC3
CC2
CC1
CC0
Default
0
0
0
0
0
0
0
0
mode, the SLEEP pin should be taken LOW and the
SAA3323 reset.
Pin explanations and interfacing to other hardware
RESET
CLK24
This is an active HIGH input which resets the SAA3323
and brings it into its default mode, DPAP. This reset does
not affect the contents of the FIR filter coefficients in the
digital equalizer. This should be connected to the system
reset, which can be driven by the microcontroller. The
duration of the reset pulse should be at least 15 µs.
This is the 24.576 MHz clock input and should be
connected directly to the SAA2003 (pin CLK24).
Sub-band serial PASC interface connections
The timing for the sub-band serial PASC interface is given
in Figs 5 to 7.
SLEEP
This pin is an active HIGH input which puts the SAA3323
in a low power consumption SLEEP mode. This pin should
be connected to the DCC SLEEP signal, which can be
driven by the microcontroller. The CLK24 clock may be
stopped and the VREFP and VREFN inputs brought to
ground while the SAA3323 is in ‘sleep’ mode to further
reduce power consumption. When recovering from sleep
May 1994
12
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full SBCL(in)
pagewidth
SBWS(in)
SBDA(in)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SBCL(in)
SBWS(in)
SBDA(in)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
bit number
SBCL(in)
V IH
VOH
SBWS(in)
V IH
VOH
SBDA(in)
V IH
VOH
2 x t MCLK
40 ns
40 ns
MGB381
Fig.5 Sub-band serial PASC interface timing; DRAR mode.
May 1994
13
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, fullSBCL(out)
pagewidth
SBWS(out)
SBDA(out)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SBEF(out)
SBCL(out)
SBWS(out)
SBDA(out)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
bit number
SBEF(out)
SBMCLK(in)
V IH
V IL
SBCL(out)
VOH
V OL
60 ns
SBWS(out)
VOH
V OL
SBDA(out)
VOH
V OL
7 ns
VOH
V OL
SBDA(out)
MGB382
7 ns
Fig.6 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 1.
May 1994
14
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full
pagewidth
SBCL(in)
SBWS(in)
SBDA(out)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SBEF(out)
SBCL(in)
SBWS(in)
SBDA(out)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
bit number
SBEF(out)
SBCL(in)
V IH
V IL
SBWS(in)
V IH
V IL
2 x t MCLK
40 ns
40 ns
VOH
VOL
SBDA(out)
t MCLK
(40
t MCLK
(40
85) ns
VOH
VOL
SBDA(out)
40) ns
MGB383
Fig.7 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 0.
SBMCLK
SBCL
This is the sub-band master clock input for the sub-band
serial PASC interface. The frequency of this signal is
nominally 6.144 MHz. When the SAA3323 is used with
SAA2003 this pin is tied to ground, and the TFE settings
bit ‘DRPMAS’ set to logic 1.
This input/output pin is the bit clock line for the sub-band
serial PASC interface to the SAA2003. When used with
SAA2003 this pin is input only. It has a nominal frequency
of 768 kHz.
SBWS
SBDIR
This input/output pin is the word select line for the
sub-band serial PASC interface to the SAA2003. When
used with SAA2003 this pin is input only. It has a nominal
frequency of 12 kHz.
This output pin is the sub-band serial PASC bus direction
signal, it indicates the direction of transfer on the sub-band
serial PASC bus. This pin connects directly to the SBDIR
pin on the SAA2003. The transfer directions are shown in
Table 13.
SBDA
This input/output pin is the serial data line for the sub-band
serial PASC interface to the SAA2003.
Table 13 PASC bus transfer directions.
SBDIR
DIRECTION
1
SAA3323 to SAA2003 transfer (audio play)
0
SAA2003 to SAA3323 transfer (audio record)
May 1994
SBEF
This active HIGH output pin is the error-per-byte line for
the sub-band serial PASC interface to the SAA2003.
15
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
the URDA pin of the SAA2003. URDA goes active as a
result of a reset, a mode change from mode DRAR to
DPAP, or if the SAA3323 has had to re-synchronize with
the incoming data from tape.
URDA
This active HIGH output pin indicates that the main data
(audio), the SYSINFO and the AUXILIARY data are NOT
usable, regardless of the state of the corresponding
reliability flags. The state of this pin is reflected in the
URDA bit of STATUS byte 0, which can be read by the
microcontroller. This pin should be connected directly to
handbook, full pagewidth
SNUM
The position of the first sub-band serial PASC bytes in a
tape frame is shown in Figs 8 and 9.
0
1
SBWS
L3REF
'FIRST BYTE"
SBDA
MGB384
byte 0
byte 1
byte 2
Fig.8 Position of first sub-band serial PASC bytes in a tape frame in DPAP/DPAR mode.
handbook, full pagewidth
SNUM
3
0
SBWS
L3REF
'FIRST BYTE'
SBDA
MGB385
byte 0
byte 1
byte 2
Fig.9 Position of first sub-band serial PASC bytes in a tape frame in DRAR mode.
May 1994
16
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
RAM connections
OEN
The SAA3323 has been designed to operate with DRAMs
and SRAMs. Suitable DRAMs are 64K × 4-bit or
256K × 4-bit configurations operating in page mode, with
an access time of 80 to 100 ns. The timing for read, write
and refresh cycles for DRAMs is shown in Figs 10 to 12.
The timing for SRAMs is shown in Figs 13 to 19.
This output pin is the output enable (active LOW) for the
RAM, it connects directly to the output enable pin of the
RAM.
WEN
This output pin is the write enable (active LOW) for the
RAM, it connects directly to the write enable pin of the
RAM.
For fast SRAMs: (these values are subject to verification
during characterization in). The conditions (most critical at
the required VDD) are shown in Table 14.
A0 TO A8
Table 14 Fast SRAM conditions.
CONDITION(1)
When SAA3323 is used with DRAM these output pins are
the multiplexed column and row address lines. When the
64K × 4-bit DRAM is used, pins A0 to A7 should be
connected to the DRAM address input pins, and pin A8
should be left unconnected. When using the 256K × 4-bit
DRAM the address pins A0 to A8 should be connected to
the address input pins of the DRAM.
TIME
Write pulse duration
tW ≤ 140 ns
Data set-up to rising WEN
tsu ≤ 72 ns
Write cycle time
Tcy ≤ 200 ns
Read access time
tACC ≤ 240 ns
When SAA3323 is used with SRAM these are the lower
address pins and should be connected directly to the
SRAM address pins.
Note
1. The SAA3323 should work in: RType = ‘01’;
RTim = ‘00’ mode.
A11
A9/CAS
This output pin is the an address pin for the SRAM and
when SRAM is used they should be connected directly to
the address pins of the SRAM. When DRAM is used this
pin should not be connected.
When SAA3323 is used with SRAM this output pin is
Address line 9, and should be connected directly to the
corresponding address pin on the SRAM. When SAA3323
is used with DRAM this output pin is the column address
strobe (active LOW), it connects directly to the column
address strobe pin of the DRAM.
A10 AND A12 TO A16
These output pins are the upper address pins for the
SRAM and when SRAM is used they should be connected
directly to the address pins of the SRAM. When DRAM is
used or when the small SRAM is used all or some of these
pins become available as Port expander outputs.
A10/RAS
When SAA3323 is used with SRAM this output pin is
Address line 10, and should be connected to the
corresponding address pin of the SRAM. When SAA3323
is used with DRAM this output pin is the row address
strobe (active LOW), it connects directly to the row
address strobe pin of the DRAM.
May 1994
17
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 15 Port expander outputs.
PIN
PORT EXPANDER
OUTPUT
PIN NAME
CONDITIONS
QFP80
TQFP80
A14/PINO1
46
44
PINO1
RType = 00
A13/PINO2
50
48
PINO2
RType = 00
A16/PINO3
47
45
PINO3
RType = 00 or RType = 01
A15/PINO4
48
46
PINO4
RType = 00 or RType = 01
A12/PINO5
45
43
PINO5
RType = 00
D0 TO D3
When SAA3323 is used with SRAM these I/O pins form the lower nibble of the data bus connection to the RAM, and
should be connected to the corresponding data I/O pins of the SRAM. When SAA3323 is used with DRAM these
input/output pins are the data lines for the RAM, they should be connected directly to the DRAM data I/O pins.
D4 TO D7
These input/output pins are the upper nibble of the data bus for use with SRAM, and when SRAM is being used they
should be connected directly to the corresponding SRAM I/O pins.
handbook, full pagewidth
WEN
OEN
t RAS
A10/RAS
t RP
A9/CAS
t CAS
,,,,
,,,,
,,,,
,,,,,
,,,,
,,,,
,,,,
,,,,,
,,,,
,
,,,,,,,,
,
t ASC
t ASR
A0 to A8
t RCD
t RAH
ROW ADDRESS
t CP
t CAH
COLUMN ADDRESS
t CAC
D0 to D3
COLUMN ADDRESS
NIBBLE 0 DATA
t OEZ
NIBBLE 1 DATA
t RAC
NIBBLE 2 DATA
MGB386
Fig.10 DRAM read cycle timing.
May 1994
COLUMN ADDRESS
t OFF
18
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t WCS
handbook, full pagewidth
t WCH
WEN
OEN
t RAS
A10/RAS
t RP
t RCD
t CAS
,,,,,
,,,,
,,,,
,,,,,
,,,,,
,,,,
,,,,
,,,,,
,,,,
,,,,
,,,,,
A9/CAS
t ASC
t ASR
A0 to A8
t RAH
ROW ADDRESS
D0 to D3
t CP
t CAH
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
NIBBLE 0 DATA
NIBBLE 1 DATA
NIBBLE 2 DATA
t DS
t DH
MGB387
Fig.11 DRAM write cycle timing.
handbook, full pagewidth
WEN
OEN
t RP
t RAS
A10/RAS
A9/CAS
,,,,
t ASR
A0 to A8
t RAH
ROW ADDRESS
D0 to D3
MGB388
Fig.12 DRAM refresh cycle timing.
May 1994
19
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full pagewidth WEN
,,,
,,,,
,,,,
,,,,,,
,,,
,,,,
,,,,
,,
,,,,
,,,
,,,,,,
,,
,,,,,,,
,
OEN
A0 to A16
ADDRESS
ADDRESS
t AA
D0 to D7
t OH
t OHZ
DATA
DATA
READ
READ
MGB389
t OLZ
Fig.13 Fast SRAM read cycle timing.
t WP
handbook, full pagewidth
t WP
WEN
OEN
,,
,,,,
,
,,,,,
,,,,,
,,,
,,,
,
,,,
,,,,,,,
,,,
A0 to A16
tAW
t WC
ADDRESS
ADDRESS
D0 to D7
DATA
t DH1
WRITE
t DHO1
t OLZ
t DW1
t DW2
DATA
tAA
DATA
MGB390
t OHZ
t DH2
READ MODIFY WRITE
Fig.14 Fast SRAM write cycle timing; RTim = “00”.
May 1994
20
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t WP
handbook, full pagewidth
t WP
WEN
OEN
,,,
,,,,,,,,,
,,,,,
,,
,,,
,,
,,
,,,,
,,,,,
tAW
t WC
A0 to A16
ADDRESS
ADDRESS
t DHO1
t OLZ
t DW2
t DAH
t DW1
D0 to D7
DATA
t DDH
DATA
tAA
WRITE
t DAH
DATA
MGB391
t OHZ
t DDH
READ MODIFY WRITE
Fig.15 Fast SRAM write cycle timing; RTim = “01”.
t WP
handbook, full pagewidth
t WP
WEN
OEN
,,
,,,,
,,,,,,
,,,,,
,,,,,,
,,,,,,
,,,,,
,,,
,,
,,,,,,
A0 to A16
tAW
t WC
ADDRESS
ADDRESS
t OLZ
t DW1
D0 to D7
DATA
t DH1
WRITE
t DHO1
t DW2
DATA
tAA
DATA
t OHZ
t DH2
t WOA
READ MODIFY WRITE
Fig.16 Fast SRAM write cycle timing; RTim = “10”.
May 1994
21
MGB392
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full pagewidth WEN
OEN
,,,
,,,
,,,,,,
,,,,,
,,,
,,,,
,,,
,,,
,,,,
,,,
A0 to A16
D0 to D7
MGB393
WRITE
READ MODIFY WRITE
Fig.17 Fast SRAM write cycle timing; RTim = “11”.
handbook, full pagewidthWEN
OEN
,,
,,,,,
,,,,
,,,,,,
,,,
,
,,
,,
,,,,,,,
,
A0 to A16
ADDRESS
t OLZ
D0 to D7
ADDRESS
t OHZ
DATA
t AA
DATA
t OH
READ
MGB394
READ
Fig.18 Slow SRAM read cycle timing.
May 1994
22
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t WP
t WP
handbook, full pagewidth
WEN
OEN
,,,
,,,,
,
,,,
,,,,,,
,,,,
,,,,
,,,,
,,,,
A0 to A16
t AW
t WC
t AW
t WC
ADDRESS
ADDRESS
t DW1
D0 to D7
t DW2
DATA
DATA
t DH
MGB395
t DH
WRITE
WRITE
Fig.19 Slow SRAM write cycle timing.
Table 16 Timing values for Figs 10 to 12.
SYMBOL
Table 17 Timing values for Figs 13 to 17.
VALUE (ns)
SYMBOL
VALUE (ns)
tRP
≥110
tWP
≥140
tRAS
≥510
tAW
≥180
tRCD
≥70
tWC
≥200
tCP
≥30
tDW
≥72
tCAS
≥100
tDM
≥25
tASR
≥100
tAA
≤240
tRAH
≥25
tHC
≥250
tASC
≥30
tCAM
≥100
tDS
≥25
tDH
≥100
tWP
≥225
tWCS
≥30
tAW
≥260
tWCH
≥100
tWC
≥300
tRAC
≤160
tDW
≥140
tCAC
≤80
tDM
≥25
tAA
≤280
May 1994
Table 18 Timing values for Figs 18 and 19.
SYMBOL
23
VALUE (ns)
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Read/write connections
RDSYNC
TCLOCK
This output line provides synchronization information for
the read Amplifier data transfers. The relationship between
TCLOCK, RDSYNC and the channel information carried
by the RDMUX line is given in Fig.20. This pin should be
connected directly to the RDSYNC pin of the read
amplifier. When the digital equalizer in SAA3323 is in
search mode this pin will be HIGH ensuring that only the
AUX channel is processed by the SAA3323.
This output pin is the 3.072 MHz clock output for the read
and write amplifiers, it should be connected directly to the
WCLOCK pin of the write amplifier and to the RDCLK pin
of the read amplifier.
RDMUX
This input pin carries the time multiplexed analog tape
channel signals from the read amplifier.
WDATA
This output pin is the multiplexed data and control line for
the write amplifier. Figure 21 shows the manner in which
this information is multiplexed onto WDATA. The WDATA
pin should be connected directly to the WDATA pin of the
write amplifier.
Vref(n) AND Vref(p)
These are the lower and upper voltage reference inputs for
the ADC in the digital equalizer part of SAA3323.
BIAS
This pin defines a bias current for the ADC. It should be
connected to the analog supply voltage VDDA via a 47 kΩ
resistor.
handbook, full pagewidthTCLOCK
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
RDMUX
RDSYNC
MGB396
Fig.20 RDMUX, RDSYNC and TCLOCK timing.
TCLOCK
handbook, full pagewidth
Fig.21 WDATA and TCLOCK timing.
May 1994
24
TCH7
TCHAUX
TCH6
TCH5
TCH4
TCH3
TCH2
TCH1
TCH0
TERAUX
TAUPLB
SYNC
TDAPLB
WDATA
MGB397
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Tape deck capstan control connections
SPEED
This pin outputs a pulse width modulated signal that may
be used for controlling the tape capstan of the deck.
Operation of the SPEED control signal
Table 19 gives the sources that determine the duty factor
of the SPEED signal. Note that the 3-state SPEED output
may be put into high-impedance state by programming the
TFE setting by bit HiZSpd.
Table 19 SPEED signal duty factor.
MODE
µCSPD
SOURCE FOR
SPEED DUTY
FACTOR
DPAP
0
tape(1)
DPAP
1
µC(2)
DPAR
0
tape(1)
DPAR
1
µC(2)
DRAR
0
50%(3)
DRAR
1
µC(2)
Notes
1. “Tape” means that the duty factor has been calculated
from the played back main data tape signal. When
tape is the source for the duty factor of the SPEED
signal, the type of regulation can be chosen with the
TFE settings bits EnFReg and SeINBand.
2. “µC” means that the microcontroller programs the duty
factor via the SPDDTY register.
3. “50%” means that the duty factor is fixed at 50%.
May 1994
25
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
MEA717
100 %
91 %
duty
factor
speed
50 %
9%
0
+ 2 blocks
+ 10.6 ms
0
+ 1.65 blocks
+ 8.8 ms
– 1.65 blocks
– 8.8 ms
– 2 blocks
– 10.6 ms
Fig.22 SPEED regulation duty factor as a function of phase characteristic.
If EnFReg is programmed ‘LOW’ then there is phase
regulation of the capstan speed. The period of the pulse
width modulated SPEED signal is 41.66 µs. The SAA3323
performs a new calculation to determine the duty factor of
SPEED once every 21.33 ms, giving a sampling rate of
approximately 46.9 Hz. This calculation is basically a
phase comparison between the incoming Main Data tape
frame and an internally generated reference. The SPEED
duty factor as a function of phase characteristic is shown
in Fig.22. As shown the duty factor increases
monotonously from approximately 9% when the incoming
Main Data tape frame is 1.65 tape blocks (8.8 ms) too
early up to 91% when it is 1.65 tape blocks (8.8 ms) too
late. Outside of a ±2 tape blocks range the pulse width
characteristic overflows and repeats itself forming a
sawtooth pattern. The SAA3323 has an internal buffer of
±8.8 ms outside of which the phase information is invalid.
If EnFReg is programmed ‘HIGH’ then the above
description is over-ridden with frequency information. If the
incoming main data bit rate deviation from the nominal
96000 bits/s rate is less than the Phase Only Threshold
(POT) then the control is as described above in the phase
control description. If the deviation is more than the
Frequency Only Threshold (FOT) then the SPEED
information is gated with the phase information resulting in
the SPEED signal being continuously HIGH or LOW while
the condition continues. If the deviation is between the
POT and the FOT then the frequency information is gated
with the Phase information for 50% of the time.
The deviation thresholds POT and FOT are programmable
via the TFE settings bit SeINBand.
Table 20 POT and FOT deviation thresholds.
SeINBand
POT
(DEVIATION FROM NOMINAL)
FOT
(DEVIATION FROM NOMINAL)
0
±6%
±9%
1
±3%
±4.5%
May 1994
26
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
If SLEEP is ‘HIGH’ then the state of the SPEED signal will
be the state that it was in just before the SAA3323 went
into sleep. Thus if SPEED was HIGH just before sleep it
will stay HIGH during sleep. The same applies if it was
LOW or if it was in ‘high-Z’ state. Note that a reset of the
SAA3323 will take the SPEED signals out of ‘high-Z’ state.
Table 21 Timing values for Fig.23.
TIME(1)
SYMBOL
Microcontroller connections
L3REF
This active LOW output pin indicates the start of a time
segment, it goes LOW for 5.2 µs once every 42.66 ms
approximately and can be used for generating interrups for
the microcontroller. If a re-synchronization occurs then the
time between the occurrences van vary. This pin can be
connected directly to the interrupt input of the
microcontroller.
L3CLK
tW1
T + tsu (L3MODE) + th (L3MODE); tw1 ≥ 200 ns
td1
T + tsu (L3MODE) + th (L3CLK); td1 ≥ 200 ns
th2
T + tsu (L3CLK) + th (L3MODE); th2 ≥ 200 ns
td2
T + tsu (L3CLK) + td (L3DATA); td2 ≤ 250 ns
td5
0 ≤ td5 ≤ 50 ns
tcL
T + tsu (L3CLK) + th (L3CLK); tcL ≥ 200 ns
tcH
T + tsu (L3CLK) + th (L3CLK); tcH ≥ 200 ns
tsu1
T + tsu (L3DATA) + th (L3CLK); tsu1 ≤ 200 ns
th1
T + tsu (L3CLK) + th (L3DATA); th1 ≤ 35 ns
td3
2 × T + tsu (L3MODE) + td (L3DATA); td3 ≤ 250 ns
th3
T + th (L3CLK) + td (L3DATA); th3 ≥ 50 ns
td4
2 × T + tsu (L3CLK) + td (L3DATA); td4 ≤ 410 ns
td4(2)
3 × T + tsu (L3CLK) + td (L3DATA); td4 ≤ 575 ns
This input pin is the clock line for the microcontroller
interface.
Notes
L3DATA
2. td4 is the delay time between the last bit of a byte and
first bit of the next byte, if no ‘halt’ is used.
1. T is the period of the master clock on the chip.
This input/output pin is the serial data line for the
microcontroller interface.
L3MODE
This input determines the type of transfer that is occurring
between the microcontroller and the SAA3323. If L3MODE
is LOW then a device address can be sent by the
microcontroller. If L3MODE is HIGH then a data transfer
may be occurring.
L3INT
This pin carries interrupts from the digital equalizer
module. It can also be programmed to reflect the state of
the AENV, LABEL and VIRGIN signals.
May 1994
27
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t W1
handbook, full pagewidth
L3MODE
t h2
t d1
L3CLK
t d5
t d5
L3DATA
DRP to
microcontroller
a.
L3MODE
t cL
t cH
t h2
L3CLK
t d1
t h1
L3DATA
microcontroller
to DRP
0
1
2
t su1
3
4
5
6
7
b.
L3MODE
t cL
t cH
L3CLK
t h2
t h1
t d1
L3DATA
microcontroller
to DRP
0
1
2
3
4
5
6
7
c.
t su1
L3MODE
t cL
t cH
t h2
L3CLK
t d1
L3DATA
DRP to
microcontroller
0
t d2
t d3
t d5
t h3
1
2
3
4
5
7
MGB398
t d4
d.
a. Halt mode.
b. Addressing mode.
c. Data mode (transfer from microcontroller to SAA3323).
d. Data mode (transfer from SAA3323 to microcontroller).
Fig.23 L3 interface timing and typical transfers (1).
May 1994
6
28
L3CLK
L3DATA
TFE3 WCMD
LDSET0
TFE3 WDAT
SET0 DATA
TFE3 WCMD
LDSET1
TFE3 WDAT
RDSYS
TFE3 RDAT
SET1 DATA
a.
L3MODE
L3CLK
L3DATA
TFE3 RSTAT
STATUS0
DATA
STATUS1
DATA
STATUS2
DATA
STATUS3
DATA
b.
L3MODE
L3CLK
Philips Semiconductors
Drive processor for DCC systems
May 1994
L3MODE
L3DATA
TFE3 WCMD
LDBYCYNT
TFE3 WDAT
D8HEX
TFE3 WCMD
SYSINFO(8)
SYSINFO(9)
29
c.
L3MODE
L3CLK
L3DATA
TFE3 WCMD
LDBYCYNT
TFE3 WDAT
D8HEX
TFE3 WCMD
RDSYS
TFE3 RSTAT
STATUS0
DATA
TFE3 RDAT
SYSINFO(8)
MGB399
L3MODE
L3CLK
L3DATA
STATUS0
DATA
TFE3 RDAT
SYSINFO(9)
Preliminary specification
Fig.24 L3 interface timing and typical transfers (2).
SAA3323
a. Write settings bytes 0 and 1 to TFE3 part of SAA3323.
b. Read all 4 status bytes from TFE part of SAA3323.
c. Read 2 SYSINFO bytes starting at byte 8 (in high-speed transfer part of program).
d. Read 2 SYSINFO bytes starting at byte 8 (in low-speed transfer part of program).
d.
handbook, full pagewidth
TFE3 RSTAT
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SAA3323 test pins
PINO1
TEST0 TO TEST3
This output pin is connected directly to the PINO1 bit of the
TFE settings 0 register. The microcontroller can set or
reset this pin.
These input pins are for test only, do not connect.
AZCHK
PINO2 TO PINO5
This output pin indicates the occurrence of a tape channel
sync symbol on tape channels TCH0 and TCH7, the
distance between the pulses for the TCH0 and TCH7
channels gives a measure of the azimuth error between
the tape and head alignment. Figure 25 shows the typical
timing for this signal.
Depending upon the type and the size of system RAM
used, some or all of these Port expander output pins may
be available, (please see Section “RAM connections”
“A10 and A12 to A16” on interfacing to the RAM pins).
Supply pins
ERCOSTAT
VDD1 TO VDD6
This output pin can be connected to a symbol error rate
measurement system.
These are the supply pins, all of these pins must be
connected. We recommend that each power supply pin
pair (i.e. VDD1 to VSS1, VDD2 to VSS2, etc.) be decoupled
using a 22 nF capacitor as close as is physically possible
to the pins of the SAA3323.
Port expansion pins
PINI
This input pin is connected directly to the PINI bit in the
status byte 1, it can be read by the microcontroller, and
may be used for any CMOS level compatible input signals.
VSS1 TO VSS6
These are the supply ground pins, all of which must be
connected.
Duration of the one tape block
5.3 ms
handbook, full pagewidth
AZCHK
(8 periods MCLK)
1.3 µs
MEA705
This is a measure of the azimuth error.
Nominal Inter Frame Gap (IFG) lasts 660 µs.
Fig.25 AZCHK timing.
May 1994
30
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
internally to all the supply ground pins (VSS1 to VSS6),
however it should always be connected externally.
VDD7
This is the supply pin for the output buffers to the data lines
of the system RAM. It should always be connected
externally. Decouple this pin with a 22 nF capacitor to the
VSS7 pin.
Auxiliary envelope detection
INTMASK
INTMASK is a interrupt mask register. This register sets
the mode of operation for the interrupt interface, and is
writable only.
VSS7
This is the ground supply pin for the output buffers of the
data lines of the system RAM. This pin is connected
Table 22 Interrupt mask register.
BIT
7
Meaning
Default
6
5
4
3
2
1
0
BP1
BP0
Vup(1)
AEup(2)
AEdn(3)
Lup(4)
Ldn(5)
ECZ(6)
0
0
0
0
0
0
0
0
Notes
1. Vup ≡ rising edge of VIRGIN interrupt.
2. AEup ≡ rising edge of AUX envelope interrupt.
3. AEdn ≡ falling edge of AUX envelope interrupt.
4. Lup ≡ rising edge of LABEL interrupt.
5. Ldn ≡ falling edge of LABEL interrupt.
6. ECZ ≡ AUX envelope counter has just reached zero interrupt.
The AUX envelope information is only valid when the
digital equalizer is in search mode and when the tape
speed is between the values of
3 to 48 × nominal tape speed. The timing relationships
between the AUX channel input signal, AENV, LAB and
VIR are shown in Figs 26 to 28. The delays td1 and td2 are
between 0.25 and 0.5tAUX (AUX envelope periods). The
delays td3, td4, td5 and td6 are between 2 and 6tAUX
(AUX envelope periods).
BP1 AND BP0 (BYPASS)
If any of the bypass bits are HIGH then the interrupts are
not passed on to the microcontroller, instead the level of
the corresponding signal is available an the interrupt pin.
Table 23 BP1 and BP0.
BP
EFFECT OF BYPASS
1
0
0
0
no bypass
0
1
LAB on L3INT pin; note 1
1
0
AENV on L3INT pin; note 2
1
1
VIR on L3INT pin; note 3
When using the digital equalizer in search mode first
program the digital equalizer to search mode, then
program the INTMASK register.
MASK
If the BP1 and BP0 bits are LOW then the mask bits take
effect. Any combination of the mask bits may be HIGH,
enabling the corresponding interrupts. The interrupt pin
L3INT is active LOW when used for interrupts and active
HIGH when used for bypassing. So if it is not in bypass
mode and at least one of the interrupts has occurred it will
go LOW and stays LOW until DEQ status byte 0 has been
read. Extra interrupts that occur after the first interrupt and
before the DEQ status byte 0 is read are seen in the status
register. Extra interrupts that occur after the status byte
Notes
1. LAB = LABEL (HIGH if a LABEL condition is detected
in the envelope of the AUX channel).
2. AENV = envelope of the AUX channel (1 bit binary).
3. VIR = VIRGIN (indicated by the total [continuous]
absence of signal on the AUX channel).
May 1994
31
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
has been read will generate a new interrupt. Interrupts that are already noted in the digital equalizer Status 0 are cleared
by reading it.
Table 24 Digital equalizer STATUS0.
BIT
Meaning
7
6
5
4
3
2
1
0
BKSW(1)
TEST
Vup(2)
AEup(3)
AEdn(4)
Lup(5)
Ldn(6)
ECZ(7)
Notes
1. BKSW (filter bank switched) indicates that the last main data coefficients sent to the digital equalizer have been
activated.
2. Vup indicates whether an interrupt caused by the rising edge of VIRGIN has occurred.
3. AEup indicates whether an interrupt caused by the rising edge of AUX envelope has occurred.
4. AEdn indicates whether an interrupt caused by the falling edge of AUX envelope has occurred
5. Lup indicates whether an interrupt caused by the rising edge of LABEL has occurred.
6. Ldn indicates whether an interrupt caused by the falling edge of LABEL has occurred.
7. ECZ indicates that the AUX envelope counter has reached zero.
t AUX
handbook, full pagewidth
RDMUX
AENV
t d1
MGB400
t d2
Fig.26 AUX channel envelope to AENV delays.
t AUX
handbook, full pagewidth
AENV
(internal)
LAB
t d3
t d4
Fig.27 AENV to LAB delays.
May 1994
32
MGB401
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t AUX
handbook, full pagewidth
AENV
(internal)
Vir
t d5
MGB402
t d6
Fig.28 AENV to VIR delays.
Table 25 Digital equalizer STATUS1.
BIT
Meaning
7
6
5
4
3
2
1
0
−
−
−
−
−
VIR(1)
AENV(2)
LAB(3)
Notes
1. VIR gives the state of the VIRGIN signal.
2. AENV represents the state of the AENV signal.
3. LAB gives the state of the LAB signal.
AUX envelope count (AECNT) register
This 16 bit register is used for loading the AUX envelope
counter and for reading the state of that counter, it is
therefore readable and writable as 2 bytes. Least
Significant Byte first.
Table 26 AECNT register.
AECNT
BIT
Meaning
LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
27
26
25
24
23
22
21
20
215
214
213
212
211
210
29
28
Search speed (SSPD) register
 SR 
51.2
Search speed =  2  ×  -----------  × normal speed
SV
Table 27 Search speed register.
BIT
Meaning
7
6
5
4
3
2
1
0
SVF(1)
SV4(2)
SV3(2)
SV2(2)
SV1(2)
SV0(2)
SR1(3)
SR0(3)
Notes
1. SVF speed validation flag, if HIGH then the search speed measurement is invalid.
2. SV4 to SV0 search speed value.
3. SR1 and SR0 search speed range.
May 1994
33
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
ANAEYE register
Table 28 ANAEYE register analog eye pattern selection register.
BIT
7
6
5
4
3
2
1
0
Meaning
−
−
−
AEN(1)
ACHN3(2)
ACHN2(2)
ACHN1(2)
ACHN0(2)
Default
0
0
0
0
0
0
0
0
Notes
1. AEN analog eye pattern output enable. If this bit is LOW the Digital-to-Analog Converter (DAC) is switched off and
the output is HIGH.
2. ACHN3 to ACHN0 select channel for analog eye output.
Table 29 ACHN3 to ACHN0 channel selections for analog eye output.
ACHN
CHANNEL ON ANAEYE
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
AUX
T1sel register
Table 30 T1SEL register CHTST1 pin selection register.
BIT
7
6
5
4
3
2
1
0
Meaning
−
T1F2
T1F1
T1F0
T1C3
T1C2
T1C1
T1C0
Default
0
0
0
0
0
0
0
0
Table 31 T1C3 to T1C0 CHTST1 pin channel selections.
T1C
CHANNEL ON CHTST1
May 1994
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
AUX
34
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 32 T1F2 to T1F0 CHTST1 pin function selections.
T1F
FUNCTION OF CHTST1 PIN
2
1
0
0
0
0
off; logic 0
0
0
1
digital eye pattern
0
1
0
sliced data
0
1
1
bit clock
1
0
0
clock extraction frequency
The digital eye pattern is in 8 bits two’s complement notation, the sliced data and the bit clock give the current binary
state of the corresponding signals, and the clock extraction frequency output is in 8 bits offset binary format. The timing
diagrams for the digital eye pattern output and the clock extraction frequency output are shown in Fig.29.
T2sel register
Table 33 T2SEL register CHTST2 pin selection register.
BIT
7
6
5
4
3
2
1
0
Meaning
−
T2F2
T2F1
T2F0
T2C3
T2C2
T2C1
T2C0
Default
0
0
0
0
0
0
0
0
Table 34 T2C3 to T2C0 CHTST2 pin channel selections.
T2C
Table 35 T2F2 to T2F0 CHTST2 pin function selections.
T2F
3
2
1
0
CHANNEL ON
CHTST2
0
0
0
0
0
0
0
0
off; logic 0
0
0
0
1
1
0
0
1
digital eye pattern
0
0
1
0
2
0
1
0
sliced data
0
0
1
1
3
0
1
1
bit clock
0
1
0
0
4
1
0
0
clock extraction frequency
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
AUX
May 1994
FUNCTION OF CHTST2 PIN
35
2
1
0
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full pagewidth
RDSYNC
TCLOCK
MCLK
LSB
0
CHTST
MSB
1
2
3
4
5
6
7
0
1
2
3
MGB403
Fig.29 CHTST1 and CHTST2 output timing.
Table 36 DEQSET digital equalizer settings.
BIT
7
6
5
4
3
2
1
0
Meaning
−
−
−
−
−
ACup(1)
DM1
DM0
Default
0
0
0
0
0
0
0
0
Note
1. ACup is the AUX envelope counter direction is up. This setting caused the AUX envelope counter increment or to
decrement by 1 every rising edge of the AUX envelope signal AENV.
DM1 and DM0
Table 37 DM1 and DM0 digital equalizer mode of
operation.
DM
MODE OF OPERATION OF
DIGITAL EQUALIZER
1
0
0
0
normal(1)
0
1
search(2)
1
0
off(3)
1
1
off(3)
Notes
1. In normal mode the main data channels and the AUX
channel are processed (equalized), the AUX channel
envelope information is not processed.
2. In search mode only the AUX channel is processed by
the digital equalizer.
3. Off means that the digital equalizer is put to sleep (low
power), this can be used for example in portable
recording equipment. RDSYNC is HIGH if off mode.
Also note that the other digital equalizer registers are
not addressable while the digital equalizer is in off
mode.
May 1994
36
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
CLKSET
Table 38 CLKSET clock extraction settings.
BIT
7
LEAE(1)
Meaning
Default
1
6
5
4
3
2
1
0
FR1
FR0
GNOR
GE1
GE0
RD1
RD0
0
0
1
1
0
1
0
Note
1. LEAE (leakage enable): this setting enables a leakage function in the PLL clock extraction loop filter. This gives a
slightly improved performance with high SER tapes at the cost of a slight decrease in dynamic performance. For
home (static) applications program this bit to logic 1 and for portable applications to logic 0.
Table 39 FR1 and FR0 clock extraction frequency range
control.
FR
1
0
Table 40 GNOR gain in normal frequency range mode of
clock extraction.
GNOR
EFFECT ON PLL FREQUENCY
LOOP
0
0
range ±8%
0
1
range ±16%
1
0
range ±22%
1
1
range ±28%
EFFECT ON GAIN IN NORMAL RANGE
0
gain 2; for portable (mobile) applications
1
gain 1; for home (static) applications
Table 41 GE1 and GE0 gain in extended frequency
range mode of clock extraction.
GE
EFFECT ON PLL GAIN IN EXTENDED
RANGE
Note that in the (FR = 0) range the clock extraction stays
in its normal range only, hence it does not enter the
extended range.
1
0
0
0
gain 2
0
1
gain 3
Figure 30 shows the lock characteristic of the clock
extraction PLL.
1
0
gain 4
1
1
gain 5; do not use
MGB404
handbook, full pagewidth
30
28% frequency loop range limitation
bit rate
deviation
(%)
22% frequency loop range limitation
(3)
20
16% frequency loop range limitation
(2)
(1)
8% frequency loop range limitation
10
(1) Gain 4.
0
102
10
3
(2) Gain 3.
(3) Gain 2.
f (Hz)
10
4
Fig.30 Clock extraction PLL lock characteristic.
May 1994
37
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
The 128 bytes in each tape frame contain SYSINFO. The
SYSINFO bytes can for convenience, be considered as
being grouped into 4 SYSINFO blocks with:
SYSBLK0 → SI0 to SI31, SYSBLK1 → SI31 to SI63, etc.
RD1 and RD0 return delay
This is the delay before returning to normal mode after
being in ‘extended range mode’ (i.e. the number of
consecutive channel clock bit periods where the bit clock
frequency falls within the normal range before the clock
extraction returns to normal frequency mode).
In modes DPAP and DRAR SYSINFO transfers may occur
in two ways:
1. 4 blocks of 36 bytes, one block being transferred to the
SAA3323 in each time segment.
Table 42 RD1 and RD0 return delay.
RD
2. 1 block of 128 bytes being transferred in time
segment 1.
DELAY IN BITS TO RETURN TO
NORMAL MODE
1
0
0
0
64
0
1
128
1
0
256
1
1
512
In mode DRAR SYSINFO must be transferred as 4 blocks
of 32 bytes, one block in each segment.
Figures 31 to 34 show the offsets between the SYSINFO
and AUX and the time segment counter, for the various
modes of operation of the SAA3323.
SYSINFO and AUX data offsets in the SAA3323
AUX data consists of 4 blocks of 36 bytes, one block being
transferred in each (n) time segment.
Table 43 Block offsets with respect to time segment.
MODE
DESCRIPTION
DPAP
SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0; if AUX and
main were recorded simultaneously then AUXBLK = (SNUM + 1) MOD4; else read and interpret
1 AUX block in each time segment.
DRAR
SYSBLK = SNUM; AUXBLK = (SNUM + 1) MOD4
DPAR
SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0
May 1994
38
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SNUM
0 1
2
3
0
1
2
3
0
1
2
3
0
1
2
AUX BLK
1
3
0
1
2
3
0
1
2
3
0 1
2
3
2
,,,,,,,,,,,
,,,,,,,,,,,
SYS BLK
3
1
2
3
0
1
2
3
SYS BLK *
AUX, MAIN
DATA INPUT
FROM TAPE
0
0 1
0
1
2
3
0
1
2
3
2
3
0
1
0
1
2
3
0
1
2
3
2
3
0
1
0 1
0
1
2
3
2
3
0
1
2
MLB413
Fig.31 SYSINFO and AUX block delays in DPAP mode; audio and AUX simultaneously recorded.
SNUM
0 1
AUX BLK
DEPENDS ON PHASE OF AUX WRT MAIN DATA CHANNELS
SYS BLK
SYS BLK *
AUX, MAIN
DATA INPUT
FROM TAPE
2
3
0
1
2
3
0
1
2
3
0
1
2
,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,,,,,,
,,
3
0
1
2
3
0
1
2
3
0 1
0
1
2
3
0
1
2
3
2
3
0
1
0
1
2
3
0
1
2
3
2
3
0
1
0 1
0
1
2
3
2
3
0
1
2
MLB414
Fig.32 SYSINFO and AUX block delays in DPAP mode; audio and AUX separately recorded.
May 1994
39
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
handbook, full pagewidth
SAA3323
SNUM
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
AUX BLK
1
2
3
0
1
2
3
0
1
2
3
0 1
2
3
SYS BLK
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
AUX, MAIN
DATA OUTPUT
TO TAPE
3
0
1
2
3
0
1
2
3
0
1
2
3
0 1
MBG405
Fig.33 SYSINFO and AUX block delays in DRAR mode.
SNUM
AUX BLK
SYS BLK
SYS BLK *
MAIN DATA
INPUT
FROM TAPE
,,,,,
,,,,
,,,,,
,,,,
,,,,,,
,,,
,
,,
,
,,,
,,,
,,,
,,
,,,,
,,,,,,
,,
,,
,,,,
,,,
,, ,,,
,,,,
0 1
2
3
,,,,,
1 2 3 0
,,,,,
,,,,,
AUX OUTPUT
TO TAPE
3
0
1
2
0
1
2
3
0
1
2
1
2
3
0
1
2
3
3
0
1
2
3
0
1
0
1
2
3
0 1
1
0
1
2
3
2
3
0
1
,,,,,,
0 1 2 3 0
,,,,,,
,,,,,,
3
0
1
2
3
0 1
,,,,,,
0 1 2 3
,,,,,,
,,,,,,
0
1
2
3
0
1
2
3
2
3
0
1
2
3
0
1
2
3
0
1
2
3
1
40
2
,,,
0 1
,,,
,,,
Fig.34 SYSINFO and AUX block delays in DPAR mode.
May 1994
2
MLB416
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
the scratch pad RAM may be written and read in 8 bit or
12 bit units.
Scratch pad RAM
The SAA3323 provides the microcontroller with a scratch
pad RAM that the microcontroller can use for whatever it
likes. The size of the scratch pad depends upon the size
and type of RAM used with the SAA3323. The locations in
The RAM may be viewed as having up to 4 quarters, the
availability of these quarters for the scratch pad RAM is
given in Table 44.
Table 44 Availability of RAM quarters for the scratch pad RAM.
RTYPE
AVAILABLE RAM QUARTERS YZ(1)
TYPE OF RAM USED
1
0
0
0
DRAM 64K × 4
00
0
0
DRAM 256K × 4
00, 01, 10 and 11
0
1
SRAM 32K × 8 fast
00
1
0
SRAM 128K × 8 fast
00, 01, 10 and 11
1
1
SRAM (2×) 32K × 8 slow
00
1
1
SRAM 128K × 8 slow
00 and 10
Note
1. In RAM quarter YZ = 00, the scratch pad is arranged as 6 pages, where each page consists of 7 columns × 64 rows.
The pages are numbered 0 to 5, the columns 1 to 7 and the rows 0 to 63.
This gives a total of (6 × 7 × 64) 2688 locations.
In each of the RAM quarters YZ = 01, 10 and 11 the scratch pad is arranged as 6 pages where each page consists
of 8 columns × 448 rows. The pages are numbered 0 to 5, the columns 0 to 7 and the rows 0 to 447. This gives then
a total of (6 × 8 × 448) 21504 locations per RAM quarter YZ.
During communication with the scratch pad RAM, the
RAM quarter YZ is chosen when sending the RDDRAC,
RDWDRAC, WRDRAC or WRWDRAC commands to the
TFE module.
The 8 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 1 byte per
memory location, therefore the byte counter will increment
after each byte transfer.
Use of the scratch pad RAM outside the specified ranges
is not allowed and it may upset the operation of the
SAA3323.
The 12 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 2 bytes
per memory location. The first byte contains the 4 Most
Significant Bits (MSBs) of the memory location in its
4 Least Significant Bits (LSBs) positions. The other bit
positions being ‘don’t care’. The second byte contains the
8 LSBs of the memory location. The byte counter is
incremented after the transfer of the second byte.
As with SYSINFO and AUX transfers can occur at high
speed at all times except the second half of time
segment 0, that is when the status bit SLOWTFR is HIGH.
When SLOWTFR is HIGH the microcontroller must poll the
status bit RFBT to investigate when a transfer can occur.
The RACCNT and BYTCNT registers are used for
addressing the scratch pad.
Two addressing modes are available for the scratch pad,
namely random access and auto-increment. For random
access mode the address of each location is sent by the
microcontroller to the SAA3323 before each location
transfer. For auto-increment mode the address of the first
location is sent by the microcontroller before the first
location transfer, auto-incrementing of the row occurs then
for all transfers until the end of the column.
May 1994
For RAM quarter YZ = 00 the mapping of the scratch pad
RAM address onto the RACCNT and BYTCNT registers is
shown in Table 45.
41
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 45 Mapping of scratch pad RAM address for RAM quarter YZ = 00.
REGISTER
BIT
Value
RACCNT
BYTCNT
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P2
P1
P0
C2
C1
C0
1
1
R6
R5
R4
R3
R2
R1
R0
For The other three quarters of the RAM the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT
registers is shown in Table 46.
Table 46 Mapping of scratch pad RAM address for RAM quarter YZ = 01, 10 and 11.
REGISTER
BIT
Value
RACCNT
BYTCNT
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P2
P1
P0
C2
C1
C0
R8
R7
R6
R5
R4
R3
R2
R1
R0
Mode changes
Mode change DRAR to DPAP
The possible mode changes for the TFE are shown in
Table 47.
This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
Writing of Main and AUX data stops immediately after the
mode change.The time segment jumps back to logic 0,
URDA goes HIGH and stays HIGH for 5 time segments
(i.e. approximately 213.3 ms) after which it goes LOW, as
shown in Fig.37.
Table 47 Mode changes.
CURRENT
MODE
NEW MODE
DPAP
DRAR
DPAR
DPAP
−
yes
yes
DRAR
yes
−
no
DPAR
yes
no
−
Mode change DPAR to DPAP
This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
The writing of AUX data to tape stops immediately after the
mode change. The first AUX read from tape can be
expected during the following time segment 0 or 1 (i.e.
approximately 128 to 170.67 ms after the mode change),
as shown in Fig.38.
TIMING FOR SAA3323 MODE CHANGES
Mode change DPAP to DRAR
This mode change occurs at the end of the time segment
in which the TFE module receives the new settings.
Writing of the first Main and AUX data to tape starts at the
start of the time segment 1 which occurs 2 ‘end of time
segment 3’ s after the mode change. The delay to writing
to tape is approximately 222 ms, as shown in Fig.35.
Mode change DPAP to search
This mode change occurs almost instantaneously,
program the digital equalizer module in SAA3323 to go to
search mode, then program the interrupt mask register to
select the required type of interrupt.
If ‘seamless appending’ is required the new settings
should be sent to the TFE module during time segment 2.
Mode change search to DPAP
Mode change DPAP to DPAR
This mode change occurs almost instantaneously,
program the interrupt mask register to disable interrupts
program the digital equalizer module of SAA3323 to go to
normal mode. A re-synchronization will most likely occur
when as result of the data being read from tape, thus
causing URDA to go HIGH.
This mode change occurs at the first end of time
segment 2 after the TFE module receives the new
settings. Output of AUX to tape begins at the start of the
following time segment 1, (i.e. approximately 85.3 ms after
the mode change), as shown in Fig.36.
May 1994
42
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
andbook, halfpage
SNUM
0 1
2 3 0
DPAP
MODE
1
2
3
0
1
SAA3323
handbook, halfpage
2
DRAR
NEW MODE
MODE
DRAR
AUXILIARY
TAPE OUT
MEA707 - 2
Fig.35 Mode change to DRAR.
handbook, halfpage
SNUM
1
MODE
DRAR
NEW MODE
URDA
2
3
0 0
1
2 3
3
0 1
2
3 0
1
2
DPAR
DPAR
≈ 85.3 ms
MEA708 - 2
Fig.36 Mode change to DPAR.
0
handbook, halfpage
1
SNUM
MODE
DPAP
NEW MODE
DPAP
AUXILIARY
TAPE OUT
≈ 213.3 ms
MEA709 - 1
AUXILIARY
TO
MICROCONTROLLER
Fig.37 Mode change from DRAR.
May 1994
2
DPAP
NEW MODE
≈ 222 ms
AUXILIARY, MAIN
TAPE OUT
1
SNUM
1
2
3
0
DPAR
1
2
3
1
2
DPAP
DPAP
≈ 128 ms
≈ 170.66 ms
Fig.38 Mode change from DPAR.
43
0
MEA710 - 2
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
VDD
supply voltage
VI
input voltage
II
CONDITIONS
MIN.
MAX.
UNIT
2.7
3.6
V
−0.5
VDD + 0.5
V
input current
−10
+10
mA
note 1
VO
output voltage
tbf
tbf
V
IO
output current
−20
+20
mA
IDD
supply current
−
100
mA
ISS
supply current
−100
−
mA
Ptot
total power dissipation
−
500
mW
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−40
+85
°C
Ves1
electrostatic handling
note 2
−2000
+2000
V
Ves2
electrostatic handling
note 3
−200
+200
V
Notes
1. The input voltage must not exceed maximum supply voltage unless otherwise specified.
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
DC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
IDD
supply current
2.7
tbf
3.6
V
digital plus analog;
see Fig.39
−
28.1
−
mA
inputs with internal
pull-down to VSS;
all other inputs to VSS
or VDD
−
−
100
µA
Inputs CLK24, L3CLK, L3MODE, PINI, SLEEP and SBMCLK
VIL
LOW level input voltage
−
−
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
−
−
V
II
input current
−10
−
+10
µA
VI = 0 V to VDD;
Tamb = 25 °C
Inputs TEST0, TEST1 and TEST2
VIL
LOW level input voltage
−
−
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
−
−
V
II
input current
−
400
µA
May 1994
VI = VDD; Tamb = 25 °C 25
44
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SYMBOL
PARAMETER
SAA3323
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input RESET
VtLH
positive-going threshold
−
−
0.8VDD
V
VtHL
negative-going threshold
0.2VDD
−
−
V
Vhys
hysteresis (VtLH to VtHL)
−
0.3VDD
−
V
Outputs AZCHK, CHTST1, CHTST2, ERCOSTAT, L3INT, L3REF, MCLK, PINO3, RDSYNC, SBDIR, SBEF, URDA,
TCLOCK and WDATA
VOH
HIGH level output voltage
IO = 1 mA
VDD − 0.5
−
−
V
VOL
LOW level output voltage
IO = −1 mA
−
−
0.4
V
Outputs A0 to A8, A9/CAS, A10/RAS, OEN and WEN
VOH
HIGH level output voltage
IO = 2 mA
VDD − 0.5
−
−
V
VOL
LOW level output voltage
IO = −2 mA
−
−
0.4
V
Outputs SPEED and PINO2
VOH
HIGH level output voltage
IO = 1 mA
VDD − 0.5
−
−
V
VOL
LOW level output voltage
IO = −1 mA
−
−
0.4
V
IOZ
3-state leakage current
VI = 0 V to VDD;
Tamb = 25 °C
−10
−
+10
µA
Inputs/outputs SBCL, SBDA and SBWS
VOH
HIGH level output voltage
IO = 1 mA
VDD − 0.5
−
−
V
VOL
LOW level output voltage
IO = −1 mA
−
−
0.4
V
VIL
LOW level input voltage
outputs in 3-state
−
−
0.3VDD
V
VIH
HIGH level input voltage
outputs in 3-state
0.7VDD
−
−
V
IOZ
3-state leakage current
VI = 0 V to VDD;
Tamb = 25 °C
−10
−
+10
µA
Inputs/outputs A11 to A16 and L3DATA
VOH
HIGH level output voltage
IO = 2 mA
VDD − 0.5
−
−
V
VOL
LOW level output voltage
IO = −2 mA
−
−
0.4
V
VIL
LOW level input voltage
outputs in 3-state
−
−
0.3VDD
V
VIH
HIGH level input voltage
outputs in 3-state
0.7VDD
−
−
V
IOZ
3-state leakage current
VI = 0 V to VDD;
Tamb = 25 °C
−10
−
+10
µA
Inputs/outputs D0 to D7
VOH
HIGH level output voltage
IO = 4 mA
VDD − 0.5
−
−
V
VOL
LOW level output voltage
IO = −4 mA
−
−
0.4
V
VIL
LOW level input voltage
outputs in 3-state
−
−
0.8
V
VIH
HIGH level input voltage
outputs in 3-state
2
−
−
V
IOZ
3-state leakage current
VI = 0 V to VDD;
Tamb = 25 °C
−10
−
+10
µA
May 1994
45
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Average current consumption
MLB778
60
I DD
(mA)
max
40
typ
min
20
0
2.0
2.5
3.0
3.5
VDD (V)
4.0
Fig.39 Average current consumption.
AC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; CL = 10 pF on all outputs; see Fig.40; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock inputs
input capacitance
−
−
10
pF
fCLK24
clock frequency
24
24.576
25
MHz
t24L
pulse width LOW
12
−
−
ns
t24H
pulse width HIGH
12
−
−
ns
CI
CLK24
SBMCLK
fSBMCLK
clock frequency
6.144
12.5
MHz
tSCL
pulse width LOW
30
−
−
ns
tSCH
pulse width HIGH
30
−
−
ns
May 1994
46
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SYMBOL
PARAMETER
SAA3323
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock output MCLK
CL
load capacitance
−
−
20
pF
td
delay time from SLEEP HIGH to
SLEEP active
−
20
−
ns
fMCLK
clock frequency
6.144
6.25
MHz
tMCL
MCLK pulse width LOW
50
−
−
ns
tMCH
MCLK pulse width HIGH
50
−
−
ns
tpd
propagation delay time from rising
edge of CLK24
−
−
65
ns
input capacitance
−
−
10
pF
Inputs
CI
L3CLK, L3MODE AND RESET
tsu
set-up time to rising edge of MCLK
35
−
−
ns
th
hold time from rising edge of MCLK
0
−
−
ns
tsu
set-up time to rising edge of MCLK
60
−
−
ns
th
hold time from rising edge of MCLK
0
−
−
ns
load capacitance
−
−
20
pF
propagation delay time from falling
edge of CLK24
−
−
50
ns
PINI
Outputs
CL
A0 TO A8
tpd
A9/CAS, A10/RAS AND OEN
tpd
propagation delay time from falling
edge of CLK24
−
−
50
ns
td
delay time from SLEEP HIGH to
SLEEP active
−
20
−
ns
−
−
50
ns
−
−
50
ns
−
20
−
ns
−
−
45
ns
−
−
55
ns
WEN
tpd
propagation delay time
from falling edge of CLK24
from falling edge of WEN to rising
edge of CLK24
td
long write pulse
mode
delay time from SLEEP HIGH to
SLEEP active
AZCHK, CHTST1, CHTST2, L3INT, PINO3, RDSYNC, SBEF AND WDATA
tpd
propagation delay time from rising
edge of MCLK
ERCOSTAT, L3REF, SBDIR, SPEED, PINO2, URDA AND TCLOK
tpd
May 1994
propagation delay time from rising
edge of MCLK
47
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SYMBOL
PARAMETER
SAA3323
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs/outputs
CI
input capacitance
−
−
10
pF
CL
load capacitance
−
−
20
pF
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tpd
propagation delay time from falling
edge of CLK24
−
−
55
ns
td
delay time from SLEEP HIGH to
SLEEP active
−
20
−
ns
tsu
set-up time to falling edge of CLK24
5
−
−
ns
th
hold time from falling edge of CLK24
15
−
−
ns
tpd
propagation delay time
from falling edge of CLK24
−
−
50
ns
from rising edge of CLK24
early write mode −
−
50
ns
A11 TO A16
D0 TO D3
D4 TO D7
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tsu
set-up time to falling edge of CLK24
5
−
−
ns
th
hold time from falling edge of CLK24
15
−
−
ns
tpd
propagation delay time
from falling edge of CLK24
−
−
50
ns
from rising edge of CLK24
early write mode −
−
50
ns
L3DATA
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tsu
set-up time to rising edge of MCLK
35
−
−
ns
th
hold time from rising edge of MCLK
0
−
−
ns
tpd
propagation delay time
from rising edge of MCLK
−
−
50
ns
from L3MODE
−
−
45
ns
−
25
−
ns
SBCL AND SBWS
td
delay time from SLEEP HIGH to
SLEEP active
tsu
set-up time to rising edge of MCLK
40
−
−
ns
th
hold time from rising edge of MCLK
0
−
−
ns
tpd
propagation delay time
May 1994
from rising edge of SBMCLK
−
−
60
ns
from rising edge of MCLK
(3-state control)
−
−
55
ns
48
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SYMBOL
PARAMETER
SAA3323
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SBDA
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tsu
set-up time to rising edge of MCLK
35
−
−
ns
th
hold time from rising edge of MCLK
0
−
−
ns
tpd
propagation delay time from rising
edge of MCLK
−
−
55
ns
t 24H
handbook, full pagewidth
V IH
CLK24
V
t su1
t h1
t 24L
V IH
IN1
V IL
t d2
t d1
VOH
OUT1
VOL
t pd
t MCL
t d4
VOH
MCLK
VOL
t MCH
t h2
t su2
V IH
IN2
V IL
td
VOH
OUT2
SBMCLK
VOL
t SCL
V IH
t d5
V IL
t SCH
VOH
OUT3
VOL
MGB407
Fig.40 Timing for AC characteristics.
May 1994
IL
49
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
ADC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; CL = 10 pF on TCLOCK output; see Fig.41; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AC RDMUX ADC resolution
−
8
−
bits
Vref(p)
positive reference voltage
−
−
VDD − 0.5
V
Vref(n)
negative reference voltage
0
−
−
V
∆Vref
Vref(p) to Vref(n)
2.0
−
−
V
Zi
input impedance
Vref(p) to Vref(n)
700
1200
1500
Ω
Vref(n) to VSS
−
650
−
Ω
−
−
15
pF
CI
input capacitance (RDMUX)
II
input current
−
−
90
µA
DNL
differential non-linearity
−
−
±0.99
LSB
24
−
−
dB
40
−
−
ns
−20 dB (FS);
100 to 500 kHz
S/(THD+N) signal-to-total harmonic
distortion plus noise ratio
Timing
Tcy
cycle time of CLK24
td1
TCLOCK delay time from
rising edge of CLK24
CL = 10 pF
−
−
80
ns
tsu
RDMUX set-up time to falling
edge of CLK24
Zsource < 150 Ω
60
−
−
ns
th
RDMUX hold time from falling
edge of CLK24
40
−
−
ns
handbook, full pagewidth
t d1
V IH
V IL
CLK24
t d2
Tcy
V
OH
VOL
TCLOCK
t d3
CLK ADC
t su
RDMUX
th
SAMPLE(1)
t d4
TESTBUS
DATA SAMPLE(1-3)
DATA SAMPLE(1-2)
MGB408
Fig.41 ADC timing.
May 1994
50
V IH
V IL
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
DAC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
DIGEYE/ANAEYE resolution
Vo
May 1994
ANAEYE output voltage
ZL > 1 MΩ
51
MIN.
TYP.
MAX.
−
6
−
−
(VDD − 1.1) −
to VDD
UNIT
bits
V
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PACKAGE OUTLINES
handbook, full pagewidth
seating plane
S
0.1 S
14.3
13.7
80
61
B
1.45
60 1.05 (4x)
1
pin 1 index
0.15 M B
0.5
12.1 14.3
11.9 13.7
0.25
0.13
20
41
40
21
0.5
0.25
0.13
1.45
(4x)
1.05
0.15 M A
12.1
11.9
X
A
1.5
1.3
0.70
0.58
1.7
1.5
0.18
0.12
0.16
0.04
detail X
MBB947
0.7
0.3
0 to 4
o
Dimensions in mm.
Fig.42 Plastic thin quad flatpack; 80 leads; body 12 × 12 × 1.4 mm (SOT315-1; TQFP80).
May 1994
52
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full pagewidth
seating plane
S
0.10 S
18.2
17.6
B
80
65
64
1
1.0
(4x)
0.6
pin 1 index
0.20 M B
0.8
20.1 24.2
19.9 23.6
0.45
0.30
41
24
25
40
0.8
0.45
0.30
1.2
(4x)
0.8
0.20 M A
14.1
13.9
X
A
2.90
2.65
1.4
1.2
0.25
0.05
3.2
2.7
0.25
0.14
1.0
0.6
detail X
0 to 7 o
MSA394 - 1
Dimensions in mm.
Fig.43 Plastic quad flatpack; 80 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off
height (SOT318-2; QFP80).
May 1994
53
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic quad flatpacks
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
May 1994
54
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
May 1994
55
Philips Semiconductors – a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02)805 4455, Fax. (02)805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,
Tel. (01)60 101-1236, Fax. (01)60 101-1211
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
Tel. (31)40 783 749, Fax. (31)40 788 399
Brazil: Rua do Rocio 220 - 5th floor, Suite 51,
CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. (011)821-2327, Fax. (011)829-1849
Canada: INTEGRATED CIRCUITS:
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477
Chile: Av. Santa Maria 0760, SANTIAGO,
Tel. (02)773 816, Fax. (02)777 6730
Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,
77621 BOGOTA, Tel. (571)249 7624/(571)217 4609,
Fax. (571)217 4549
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. (032)88 2636, Fax. (031)57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. (9)0-50261, Fax. (9)0-520971
France: 4 Rue du Port-aux-Vins, BP317,
92156 SURESNES Cedex,
Tel. (01)4099 6161, Fax. (01)4099 6427
Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,
P.O. Box 10 63 23, 20043 HAMBURG,
Tel. (040)3296-0, Fax. (040)3296 213.
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (01)4894 339/4894 911, Fax. (01)4814 240
Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,
6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. (852)424 5121, Fax. (852)428 6729
India: Philips INDIA Ltd, Components Dept,
Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. (022)4938 541, Fax. (022)4938 722
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,
P.O. Box 4252, JAKARTA 12950,
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01)640 000, Fax. (01)640 200
Italy: PHILIPS COMPONENTS S.r.l.,
Viale F. Testi, 327, 20162 MILANO,
Tel. (02)6752.3302, Fax. (02)6752 3300.
Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5028, Fax. (03)3740 0580
Korea: (Republic of) Philips House, 260-199 Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
Mexico: Philips Components, 5900 Gateway East, Suite 200,
EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
Tel. (040)783749, Fax. (040)788399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09)849-4160, Fax. (09)849-7811
Philips Semiconductors
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546.
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474
Portugal: PHILIPS PORTUGUESA, S.A.,
Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)14163160/4163333, Fax. (01)14163174/4163366.
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (65)350 2000, Fax. (65)251 6500
South Africa: S.A. PHILIPS Pty Ltd., Components Division,
195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494.
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03)301 6312, Fax. (03)301 42 43
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
Tel. (0)8-632 2000, Fax. (0)8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. (01)488 2211, Fax. (01)481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West
Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382.
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (662)398-0141, Fax. (662)398-3319.
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (0 212)279 2770, Fax. (0212)269 3094
United Kingdom: Philips Semiconductors Limited, P.O. Box 65,
Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. (071)436 41 44, Fax. (071)323 03 42
United States: INTEGRATED CIRCUITS:
811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
SCD31
© Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp56
Document order number:
Date of release: May 1994
9397 732 30011