MC14503B Hex Non-Inverting 3-State Buffer The MC14503B is a hex non–inverting buffer with 3–state outputs, and a high current source and sink capability. The 3–state outputs make it useful in common bussing applications. Two disable controls are provided. A high level on the Disable A input causes the outputs of buffers 1 through 4 to go into a high impedance state and a high level on the Disable B input causes the outputs of buffers 5 and 6 to go into a high impedance state. http://onsemi.com MARKING DIAGRAMS • 3–State Outputs • TTL Compatible — Will Drive One TTL Load Over Full 16 PDIP–16 P SUFFIX CASE 648 Temperature Range • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Two Disable Controls for Added Versatility • Pin for Pin Replacement for MM80C97 and 340097 MC14503BCP AWLYYWW 1 16 SOIC–16 D SUFFIX CASE 751B 14503B AWLYWW 1 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Parameter Symbol VDD Vin, Vout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 16 Value Unit – 0.5 to +18.0 V – 0.5 to VDD + 0.5 V Iin Input Current (DC or Transient) per Pin ± 10 mA Iout Output Current (DC or Transient) per Pin ± 25 mA PD Power Dissipation, per Package (Note 3.) 500 mW Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 MC14503B AWLYWW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION TA v SOEIAJ–16 F SUFFIX CASE 966 1 Device Package Shipping MC14503BCP PDIP–16 2000/Box MC14503BD SOIC–16 48/Rail MC14503BDR2 SOIC–16 2500/Tape & Reel MC14503BF SOEIAJ–16 See Note 1. MC14503BFEL SOEIAJ–16 See Note 1. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Publication Order Number: MC14503B/D MC14503B PIN ASSIGNMENT DIS A 1 16 VDD IN 1 2 15 DIS B OUT 1 3 14 IN 6 IN 2 4 13 OUT 6 OUT 2 5 12 IN 5 IN 3 6 11 OUT 5 OUT 3 7 10 IN 4 VSS 8 9 OUT 4 TRUTH TABLE LOGIC DIAGRAM Inn Appropriate Disable Input Outn 0 0 0 1 0 1 X 1 High Impedance DISABLE B IN 5 IN 6 IN 1 X = Don’t Care IN 2 IN 3 IN 4 DISABLE A 15 12 11 14 13 2 3 4 5 6 7 10 9 1 VDD = PIN 16 VSS = PIN 8 CIRCUIT DIAGRAM ONE OF TWO/FOUR BUFFERS VDD * INn OUTn * DISABLE * INPUT VSS TO OTHER BUFFERS * Diode protection on all inputs (not shown) http://onsemi.com 2 OUT 5 OUT 6 OUT 1 OUT 2 OUT 3 OUT 4 MC14503B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Î ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ (4.) Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc Input Voltage “0” Level (VO = 3.6 or 1.4 Vdc) (VO = 7.2 or 2.8 Vdc) (VO = 11.5 or 3.5 Vdc) VIL 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 4.5 5.0 5.0 10 15 – 4.3 – 5.8 – 1.2 – 3.1 – 8.2 — — — — — – 3.6 – 4.8 – 1.02 – 2.6 – 6.8 – 5.0 – 6.1 – 1.4 – 3.7 – 14.1 — — — — — – 2.5 – 3.0 – 0.7 – 1.8 – 4.8 — — — — — IOL 4.5 5.0 10 15 2.2 2.6 6.5 19.2 — — — — 1.8 2.1 5.5 16.1 2.1 2.3 6.2 25 — — — — 1.2 1.3 3.8 11.2 — — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IQ 5.0 10 15 — — — 1.0 2.0 4.0 — — — 0.002 0.004 0.006 1.0 2.0 4.0 — — — 30 60 120 µAdc Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs) (All outputs switching, 50% Duty Cycle) IT 5.0 10 15 Three–State Output Leakage Current ITL 15 Vin = VDD (VO = 1.4 or 3.6 Vdc) (VO = 2.8 or 7.2 Vdc) (VO = 3.5 or 11.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (2.5 µA/kHz) f + IDD IT = (6.0 µA/kHz) f + IDD IT = (10 µA/kHz) f + IDD ± 0.1 — — ± 0.0001 ± 0.1 µAdc — ± 3.0 4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006. http://onsemi.com 3 µAdc MC14503B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C) Characteristic Symbol All Types VDD VCC Typ (8.) Max 5.0 10 15 45 23 18 90 45 35 5.0 10 15 45 23 18 90 45 35 5.0 10 15 75 35 25 150 70 50 5.0 10 15 75 35 25 150 70 50 Unit Output Rise Time tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.3 ns/pF) CL + 8.0 ns tTLH = (0.2 ns/pF) CL + 8.0 ns tTLH ns Output Fall Time tTHL = (0.5 ns/pF) CL + 20 ns tTHL = (0.3 ns/pF) CL + 8.0 ns tTHL = (0.2 ns/pF) CL + 8.0 ns tTHL Turn–Off Delay Time, all Outputs tPLH = (0.3 ns/pF) CL + 60 ns tPLH = (0.15 ns/pF) CL + 27 ns tPLH = (0.1 ns/pF) CL + 20 ns tPLH Turn–On Delay Time, all Outputs tPHL = (0.3 ns/pF) CL + 60 ns tPHL = (0.15 ns/pF) CL + 27 ns tPHL = (0.1 ns/pF) CL + 20 ns tPHL 3–State Propagation Delay Time Output “1” to High Impedance tPHZ 5.0 10 15 75 40 35 150 80 70 ns Output “0” to High Impedance tPLZ 5.0 10 15 80 40 35 160 80 70 ns High Impedance to “1” Level tPZH 5.0 10 15 65 25 20 130 50 40 ns High Impedance to “0” Level tPZL 5.0 10 15 100 35 25 200 70 50 ns ns ns ns 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. DISABLE INPUT 20 ns 20 ns VDD 90% VDD 16 50% INPUT INPUT OUTPUT VSS 90% OUTPUT CL tTLH tPLH Figure 1. Switching Time Test Circuit and Waveforms (tTLH, tTHL, tPHL, and tPLH) http://onsemi.com 4 VSS tPHL tPLH PULSE GENERATOR 10% VOH 50% 10% VOL tTHL tPHL MC14503B DISABLE INPUT DISABLE INPUT PULSE GENERATOR VDD tPHZ, tPZH CIRCUIT tPLZ, tPZL CIRCUIT PULSE GENERATOR VDD 16 16 OUTPUT INPUT 1k 8 VSS OUTPUT INPUT CL 8 20 ns VSS 20 ns VDD 90% 50% DISABLE INPUT 1k 10% tPZL tPLZ VOH 90% 10% OUTPUT FOR tPZH, tPZL CIRCUIT VSS ≈ VOL + 0.05 V tPHZ tPZH OUTPUT FOR tPHZ, tPLZ CIRCUIT ≈ VOH – 0.15 V 90% 10% Figure 2. 3–State AC Test Circuit and Waveforms (tPLZ, tPHZ, tPZH, tPZL) http://onsemi.com 5 VOL CL MC14503B PACKAGE DIMENSIONS PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C DIM A B C D F G H J K L M S L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C SEATING PLANE J M D 16 PL 0.25 (0.010) MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC–16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– –T– INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 M T B S A S http://onsemi.com 6 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC14503B PACKAGE DIMENSIONS SOEIAJ–16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966–01 ISSUE O 16 LE 9 Q1 M_ E HE 1 L 8 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX ––– 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 ––– 0.78 INCHES MIN MAX ––– 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 ––– 0.031 MC14503B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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