ONSEMI NTR4502PT1G

NTR4502P
Power MOSFET
−30 V, −1.95 A, Single, P−Channel,
SOT−23
Features
•
•
•
•
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Leading Planar Technology for Low Gate Charge / Fast Switching
Low RDS(ON) for Low Conduction Losses
SOT−23 Surface Mount for Small Footprint (3 X 3 mm)
Pb−Free Packages are Available
V(BR)DSS
−30 V
−1.95 A
240 mW @ −4.5 V
Applications
•
•
•
•
ID Max (Note 1)
RDS(on) TYP
155 mW @ −10 V
P−Channel MOSFET
S
DC to DC Conversion
Load/Power Switch for Portables and Computing
Motherboard, Notebooks, Camcorders, Digital Camera’s, etc.
Battery Charging Circuits
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−30
V
Gate−to−Source Voltage
VGS
±20
V
ID
−1.95
A
Parameter
Drain Current (Note 1)
t < 10 s
TA = 25°C
TA = 70°C
Power Dissipation
(Note 1)
t < 10 s
Continuous Drain Current
(Note 1)
Steady
State
Power Dissipation
(Note 1)
TA = 25°C
PD
ID
TA = 70°C
1.25
Drain
3
W
−1.13
A
−0.90
PD
tp = 10 ms
IDM
−6.8
A
TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode)
IS
−1.25
A
Lead Temperature for Soldering Purposes
(1/8 in from case for 10 s)
TL
260
°C
Operating Junction and Storage Temperature
MARKING DIAGRAM/
PIN ASSIGNMENT
−1.56
Steady State
Pulsed Drain Current
D
0.4
W
TR2
M
G
ORDERING INFORMATION
Max
Unit
NTR4502PT1
Junction−to−Ambient – Steady State (Note 1)
RqJA
300
°C/W
NTR4502PT1G
Junction−to−Ambient – t = 10 s (Note 1)
RqJA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq. pad size
(Cu area = 1.127 in sq. [1 oz] including traces).
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 4
1
= Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
Symbol
Parameter
2
Source
1
Gate
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
Device
THERMAL RESISTANCE RATINGS
TR2 M G
G
SOT−23
CASE 318
STYLE 21
NTR4502PT3
NTR4502PT3G
Package
Shipping†
SOT−23
3000 / Tape & Reel
SOT−23
(Pb−Free)
3000 / Tape & Reel
SOT−23
10000 / Tape & Reel
SOT−23
(Pb−Free)
10000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTR4502P/D
NTR4502P
Electrical Characteristics (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = −250 mA
−30
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
VGS = 0 V, VDS = −30 V
V
TJ = 25°C
−1
TJ = 55°C
−10
IGSS
VDS = 0 V, VGS = ±20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = −250 mA
Drain−to−Source On Resistance
RDS(on)
VGS = −10 V, ID = −1.95 A
mA
±100
nA
−3.0
V
155
200
mW
VGS = −4.5 V, ID = −1.5 A
240
350
gFS
VDS = −10 V, ID=−1.25 A
3
S
Input Capacitance
CISS
VGS = 0 V, f = 1 MHz, VDS = −15 V
200
pF
Output Capacitance
COSS
80
Reverse Transfer Capacitance
CRSS
50
ON CHARACTERISTICS (Note 3)
Forward Transconductance
−1.0
CHARGES AND CAPACITANCES
VGS = −10 V, VDS = −15 V; ID = −1.95 A
10
nC
5.2
10
ns
12
20
td(OFF)
19
35
tf
17.5
30
−1.2
Total Gate Charge
QG(TOT)
6
Threshold Gate Charge
QG(TH)
0.3
Gate−to−Source Charge
QGS
1
Gate−to−Drain Charge
QGD
1.7
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
VGS =−10 V, VDD = −15 V,
ID = −1.95 A, RG = 6 W
DRAIN−SOURCE DIODE CHARACTERISTICS (Note 3)
Forward Diode Voltage
VSD
VGS = 0 V, IS = −1.25 A
−0.8
Reverse Recovery Time
tRR
VGS = 0 V, dISD/dt = 100 A/ms, IS = −1.25 A
23
2. Surface−mounted on FR4 board using 1 in sq. pad size (Cu area = 1.127 in sq. [1 oz] including traces).
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
V
ns
NTR4502P
VGS = −4.0 V
VGS = −5.0 V
4
VGS = −3.6 V
VGS = −7.0 V
3
VGS = −3.4 V
VGS = −10 V
VGS = −3.2 V
2
VGS = −3.0 V
1
0
VGS = −2.8 V
VGS = −2.6 V
VGS = −2.4 V
0
1
2
3
4
5
6
7
8
9
VDS = −10 V
5
TJ = 25°C
VGS = −3.8 V
−ID, DRAIN CURRENT (A)
−ID, DRAIN CURRENT (A)
5
TJ = 25°C
TJ = 100°C
3
2
1
0
10
TJ = −55°C
4
1
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.4
ID = −1.95 A
TJ = 25°C
0.3
0.25
0.2
0.15
0.1
3
4
5
6
7
8
9
10
−VGS, GATE−TO−SOURCE VOLTAGE (V)
5
6
7
TJ = 25°C
VGS = −4.5 V
0.25
0.2
VGS = −10 V
0.15
0.1
1
1.5
2
2.5
3
3.5
4
4.5
5
−ID, DRAIN CURRENT (A)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
1.8
ID = −1.9 A
VGS = −10 V
1.6
VGS = 0 V
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
4
0.3
Figure 3. On−Resistance versus
Gate−to−Source Voltage
1.4
1.2
1
0.8
0.6
−50
3
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
0.35
2
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 150°C
100
10
TJ = 100°C
1
−25
0
25
50
75
100
125
150
2
TJ, JUNCTION TEMPERATURE (°C)
6
10
14
18
22
26
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
30
NTR4502P
500
C, CAPACITANCE (pF)
VDS = 0 V
400
CISS
300
CRSS
TJ = 25°C
VGS = 0 V
CISS
200
COSS
100
CRSS
0
10
5
0
5
10
15
20
25
30
−VGS −VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (V)
−VGS, GATE−TO−SOURCE VOLTAGE
(V)
12
18
QT
10
15
8
12
9
6
QGS
QGD
4
6
2
3
ID = −1.95 A
TJ = 25°C
0
0
0
1
2
3
4
5
6
−VDS, DRAIN−TO−SOURCE VOLTAGE
(V)
Figure 7. Capacitance Variation
7
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
100
3
VDS = −15 V
ID = −1.95 V
VGS = −10 V
tf
td(off)
t, TIME (ns)
−IS, SOURCE CURRENT
TJ = 25°C
tr
10
td(on)
1
2.5
2
1.5
1
0.5
0
1
10
100
0.3
0.6
0.9
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
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4
1.2
NTR4502P
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. 318−01 THRU −07 AND −09 OBSOLETE, NEW
STANDARD 318−08.
D
SEE VIEW C
3
HE
E
c
1
DIM
A
A1
b
c
D
E
e
L
L1
HE
2
e
b
0.25
q
A
L
A1
MIN
0.89
0.01
0.37
0.09
2.80
1.20
1.78
0.10
0.35
2.10
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.13
0.18
2.90
3.04
1.30
1.40
1.90
2.04
0.20
0.30
0.54
0.69
2.40
2.64
MIN
0.035
0.001
0.015
0.003
0.110
0.047
0.070
0.004
0.014
0.083
INCHES
NOM
0.040
0.002
0.018
0.005
0.114
0.051
0.075
0.008
0.021
0.094
MAX
0.044
0.004
0.020
0.007
0.120
0.055
0.081
0.012
0.029
0.104
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
L1
VIEW C
SOLDERING FOOTPRINT*
0.95
0.037
0.95
0.037
2.0
0.079
0.9
0.035
SCALE 10:1
0.8
0.031
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTR4502P/D