DG3535/DG3536 Vishay Siliconix New Product 0.25- Low-Voltage Dual SPDT Analog Switch FEATURES D D D D D BENEFITS Low Voltage Operation Low On-Resistance - rON: 0.25 W @ 2.7 V −69 dB OIRR @ 2.7 V, 100 kHz MICRO FOOTr Package ESD Protection >2000 V D D D D D APPLICATIONS Reduced Power Consumption High Accuracy Reduce Board Space 1.6-V Logic Compatible High Bandwidth D D D D D D Cellular Phones Speaker Headset Switching Audio and Video Signal Routing PCMCIA Cards Battery Operated Systems Relay Replacement DESCRIPTION The DG3535/DG3536 is a sub 1-W (0.25 W @ 2.7 V ) dual SPDT analog switches designed for low voltage applications. The DG3535/DG3536 is built on Vishay Siliconix’s high-density low voltage CMOS process. An eptiaxial layer is built in to prevent latchup. The DG3535/DG3536 contains the additional benefit of 2,000-V ESD protection. The DG3535/DG3536 has on-resistance matching (less than 0.05 W @ 2.7 V) and flatness (less than 0.2 W @ 2.7 V) that are guaranteed over the entire voltage range. Additionally, low logic thresholds makes the DG3535/DG3536 an ideal interface to low voltage DSP control signals. As a committed partner to the community and the environment, Vishay Siliconix manufactures this product with the lead (Pb)-free device terminations. For MICRO FOOT analog switching products manufactured with tin/silver/copper (SnAgCu) device terminations, the lead (Pb)-free “—E1” suffix is being used as a designator. The DG3535/DG3536 has fast switching speed with break-before-make guaranteed. In the On condition, all switching elements conduct equally in both directions. Off-isolation and crosstalk is −69 dB @ 100 kHz. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG3535/DG3536 1 2 A NC2 IN2 B GND C NC1 MICRO FOOT 10-Bump 3 4 V+ COM2 NO2 IN1 NO1 COM1 NC1 NO2 COM2 NC2 DG3535 Top View IN1 COM1 V+ NO1 IN2 1 2 A NO2 IN2 B GND C NO1 GND Device Marking 3 COM2 4 NC2 A1 Locator XXX 3535 DG3536 Top View IN1 COM1 V+ TRUTH TABLE Logic NC1 and NC2 NO1 and NO2 0 ON OFF 1 OFF ON ORDERING INFORMATION Temp Range Package Part Number -40 to 85°C MICRO FOOT: 10-Bump (4x3, 0.5-mm Pitch, 238-mm Bump Height) DG3535DB-T5—E1 DG3535DB-T1—E1 DG3536DB-T5—E1 NC1 3535 = Example Base Part Number xxx = Data/Lot Traceabiliity Code Document Number: 72961 S-50130—Rev. D, 24-Jan-05 www.vishay.com 1 DG3535/DG3536 Vishay Siliconix New Product ABSOLUTE MAXIMUM RATINGS Reference to GND V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 V IN, COM, NC, NOa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+ + 0.3 V) Continuous Current (NO, NC, COM) . . . . . . . . . . . . . . . . . . . . . . . "300 mA Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "500 mA (Pulsed at 1 ms, 10% duty cycle) Storage Temperature (D Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Package Solder Reflow Conditionsb IR/Convection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C ESD per Method 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2 kV Power Dissipation (Packages)c MICRO FOOT: 10-Bump (4x3 mm)d . . . . . . . . . . . . . . . . . . . . . . . . . 457 mW Notes: a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. Refer to IPC/JEDEC (J-STD-020B). c. All bumps welded or soldered to PC Board. d. Derate 5.7 mW/_C above 70_C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS (V+ = 3 V) Test Conditions Otherwise Unless Specified Parameter V+ = 3 V, "10%, VIN = 0.5 or 1.4 Ve Limits −40 to 85_C Tempa Minb VNO, VNC, VCOM Full 0 rON Room Full Symbol Typc Maxb Unit V+ V Analog Switch Analog Signal Ranged On-Resistanced rON Flatnessd rON Flatness On-Resistance Match Between Channelsd DrDS(on) Switch Off Leakage Current INO(off), INC(off) ICOM(off) Channel-On Leakage Current ICOM(on) V = 2.7 V+ 2 7 V, V VCOM = 0.6/1.5 0 6/1 5 V INO, INC = 100 mA V+ = 3.3 V, VNO, VNC = 0.3 V/3 V VCOM = 3 V/0.3 V V+ = 3.3 V, VNO, VNC = VCOM = 0.3 V/3 V 0.25 0.4 0.5 Room 0.15 Room 0.05 Room Full −2 −20 2 20 Room Full −2 −20 2 20 Room Full −2 −20 2 20 1.4 W nA Digital Control Input High Voltaged VINH Full Input Low Voltage VINL Full Input Capacitance Input Current Full Cin IINL or IINH 0.5 VIN = 0 or V+ Full 10 1 V pF 1 mA Dynamic Characteristics Turn-On Time tON Turn-Off Time tOFF VNO or VNC = 2.0 2 0 V, V RL = 50 W, W CL = 35 pF Break-Before-Make Time Room Full 52 82 90 Room Full 43 73 78 td VNO or VNC = 2.0 V, RL = 50 W, CL = 35 pF Full Charge Injectiond QINJ CL = 1 nF, VGEN = 1.5 V, RGEN = 0 W Room 21 Off-Isolationd OIRR Room −69 Crosstalkd XTALK Room −69 CNO(off) Room 145 CNC(off) Room 145 Room 406 Room 406 Room Full 0.001 NO, NC Off Capacitanced Channel On Capacitanced Channel-On CNO(on) RL = 50 W, W CL = 5 pF, pF f = 100 KHz VIN = 0 or V+, V+ f = 1 MHz CNC(on) 1 ns 6 pC dB pF Power Supply Power Supply Current I+ VIN = 0 or V+ 1.0 1.0 mA Notes: a. Room = 25°C, Full = as determined by the operating suffix. b. Typical values are for design aid only, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. www.vishay.com 2 Document Number: 72961 S-50130—Rev. D, 24-Jan-05 DG3535/DG3536 Vishay Siliconix New Product TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) rON vs. VCOM and Supply Voltage rON vs. Analog Voltage and Temperature (NC1) 0.7 0.8 T = 25_C IS = 100 mA V+ = 1.8 V 0.5 V+ = 2.0 V 0.4 V+ = 2.7 V V+ = 3.0 V 0.3 0.2 0.0 0.0 0.6 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 85_C 0.4 25_C 0.2 0.1 0.0 0.0 4.0 0.5 1.0 VCOM − Analog Voltage (V) Supply Current vs. Temperature 2.0 2.5 3.0 Supply Current vs. Input Switching Frequency 100 mA 10 mA V+ = 3.0 V VIN = 0 V I+ − Supply Current (A) I+ − Supply Current (nA) 1.5 VCOM − Analog Voltage (V) 100000 10000 −40_C 0.3 V+ = 3.3 V 0.1 V+ = 3.0 V IS = 100 mA 0.7 r ON − On-Resistance ( W ) r ON − On-Resistance ( W ) 0.6 1000 100 V+ = 3 V 1 mA 100 mA 10 mA 1 mA 100 nA 10 nA 10 −60 1 nA −40 −20 0 20 40 60 80 100 10 100 Temperature (_C) Leakage Current vs. Temperature 10 K 100 K 1M 10 M Leakage vs. Analog Voltage 10000 300 250 V+ = 3.0 V INO(off), INC(off) 10 ICOM(on) 150 Leakage Current (pA) 100 V+ = 3.0 V 200 ICOM(on) ICOM(off) 1000 Leakage Current (pA) 1K Input Switching Frequency (Hz) 100 INO(off), INC(off) 50 0 −50 −100 −150 −200 ICOM(off) −250 1 −60 −40 −20 0 20 40 Temperature (_C) Document Number: 72961 S-50130—Rev. D, 24-Jan-05 60 80 100 −300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VCOM − Analog Voltage (V) www.vishay.com 3 DG3535/DG3536 Vishay Siliconix New Product TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) 100 10 90 t ON / t OFF − Switching Time (ns) Insertion Loss, Off-Isolation Crosstalk vs. Frequency Switching Time vs. Temperature tON V+ = 2 V 80 −10 60 Loss, OIRR, X TALK (dB) 70 tON V+ = 3 V 50 tOFF V+ = 3 V 40 30 tOFF V+ = 2 V 20 Loss −50 V+ = 3.0 V RL = 50 W −70 10 0 −60 −90 −40 −20 0 20 40 60 80 100 1M 100 K Switching Threshold vs. Supply Voltage 1G Charge Injection vs. Analog Voltage 2.00 300 250 1.75 200 1.50 Q − Charge Injection (pC) − Switching Threshold (V) 100 M 10 M Frequency (Hz) Temperature (_C) VT OIRR XTALK −30 1.25 1.00 0.75 0.50 150 100 50 V+ = 2.0 V 0 V+ = 3.0 V −50 −100 −150 −200 0.25 −250 0.00 0 1 2 3 4 5 −300 0.0 6 0.5 V+ − Supply Voltage (V) 1.0 1.5 2.0 2.5 3.0 VCOM − Analog Voltage (V) TEST CIRCUITS V+ Logic Input V+ Switch Input NO or NC VOUT IN Logic Input RL 300 W GND CL 35 pF 0V tON RL tOFF Logic “1” = Switch On Logic input waveforms inverted for switches that have the opposite logic sense. CL (includes fixture and stray capacitance) ǒ tr t 5 ns tf t 5 ns 0.9 x VOUT Switch Output 0V VOUT + VCOM 50% VINL Switch Output COM VINH Ǔ R L ) R ON FIGURE 1. Switching Time www.vishay.com 4 Document Number: 72961 S-50130—Rev. D, 24-Jan-05 DG3535/DG3536 Vishay Siliconix New Product TEST CIRCUITS V+ Logic Input V+ VNO VNC COM NO VINH tr t 5 ns tf t 5 ns VINL VO NC RL 300 W IN CL 35 pF GND VNC = VNO VO 90% Switch 0V Output tD tD CL (includes fixture and stray capacitance) FIGURE 2. Break-Before-Make Interval V+ DVOUT VOUT V+ Rgen NC or NO + COM IN VOUT IN On Off CL = 1 nF VIN = 0 − V+ On Q = DVOUT x CL GND IN depends on switch configuration: input polarity determined by sense of switch. FIGURE 3. Charge Injection V+ V+ 10 nF 10 nF V+ V+ NC or NO IN COM COM RL Analyzer COM 0V, 2.4 V Meter 0 V, 2.4 V GND IN NC or NO HP4192A Impedance Analyzer or Equivalent GND f = 1 MHz VCOM Off Isolation + 20 log V NOńNC FIGURE 4. Off-Isolation Document Number: 72961 S-50130—Rev. D, 24-Jan-05 FIGURE 5. Channel Off/On Capacitance www.vishay.com 5 DG3535/DG3536 Vishay Siliconix New Product PACKAGE OUTLINE MICRO FOOT: 10-BUMP (4 X 3, 0.5-mm PITCH, 0.238-mm BUMP HEIGHT) 10 O 0.150 X 0.229 Note 2 Solder Mask O X Pad Diameter +0.1 Silicon 0.5 A2 A A1 Bump Note 1 0.5 3 4 Recommended Land Pattern 2 1 b Diameter A e Index-Bump A1 Note 3 B E e XXX 3535 C S S e e Top Side (Die Back) e D NOTES (Unless Otherwise Specified): 1. Bump is Lead Free Sn/Ag/Cu. 2. Non-solder mask defined copper landing pad. 3. Laser Mark on silicon die back; back-lapped, no coating. Shown is not actual marking; sample only. MILLIMETERS* INCHES Dim Min Max Min Max A 0.688 0.753 0.0271 0.0296 A1 0.218 0.258 0.0086 0.0102 A2 0.470 0.495 0.0185 0.0195 b 0.306 0.346 0.0120 0.0136 D 1.980 2.020 0.0780 0.0795 E 1.480 1.520 0.0583 0.0598 0.5 BASIC e S 0.230 0.0197 BASIC 0.270 0.0091 0.0106 * Use millimeters as the primary measurement. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72961. www.vishay.com 6 Document Number: 72961 S-50130—Rev. D, 24-Jan-05