ONSEMI MC34060AD

MC34060A, MC33060A
Fixed Frequency, PWM,
Voltage Mode Single Ended
Controllers
The MC34060A is a low cost fixed frequency, pulse width
modulation control circuit designed primarily for single–ended
SWITCHMODE power supply control.
The MC34060A is specified over the commercial operating
temperature range of 0° to +70°C, and the MC33060A is specified
over an automotive temperature range of –40° to +85°C.
• Complete Pulse Width Modulation Control Circuitry
• On–Chip Oscillator with Master or Slave Operation
• On–Chip Error Amplifiers
• On–Chip 5.0 V Reference, 1.5% Accuracy
• Adjustable Dead–Time Control
• Uncommitted Output Transistor Rated to 200 mA Source or Sink
• Undervoltage Lockout
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MARKING
DIAGRAMS
14
14
1
SO–14
D SUFFIX
CASE 751A
MC3x060AD
AWLYWW
1
14
PDIP–14
P SUFFIX
CASE 646
14
MC3x060AP
AWLYYWW
1
1
x
= 3 or 4
A
= Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
PIN CONNECTIONS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Noninv
Input
1
Inv
Input
2
Compen/PWM
Comp Input
3
Dead-Time
Control
4
11 N.C.
CT
5
10 VCC
RT
6
Ground
7
+
Error
Amp 1
-
Error
2 Amp
VCC
+
Noninv
14 Input
-
Inv
13 Input
5.0 V
ref
0.1V
12 Vref
Oscillator
9
C
8
E
Q1
(Top View)
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 3
1
Publication Order Number:
MC34060A/D
MC34060A, MC33060A
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
42
V
Collector Output Voltage
VC
42
V
Collector Output Current (Note 1)
IC
500
mA
Amplifier Input Voltage Range
Vin
–0.3 to +42
V
Power Dissipation @ TA ≤ 45°C
PD
1000
mW
Operating Junction Temperature
TJ
125
°C
Storage Temperature Range
Tstg
–55 to +125
°C
Operating Ambient Temperature Range
For MC34060A
For MC33060A
TA
°C
0 to +70
–40 to +85
THERMAL CHARACTERISTICS
Characteristics
Symbol
P Suffix
Package
D Suffix
Package
Unit
RθJA
80
120
°C/W
TA
45
45
°C
Thermal Resistance, Junction–to–Ambient
Derating Ambient Temperature
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
Condition/Value
VCC
7.0
15
40
V
Collector Output Voltage
VC
–
30
40
V
Collector Output Current
IC
–
–
200
mA
Amplifier Input Voltage
Vin
–0.3
–
VCC –2
V
Current Into Feedback Terminal
Ifb
–
–
0.3
mA
Reference Output Current
Iref
–
–
10
mA
Timing Resistor
RT
1.8
47
500
kΩ
Timing Capacitor
CT
0.00047
0.001
10
µF
Oscillator Frequency
fosc
1.0
25
200
kHz
–
–0.3
–
5.3
V
PWM Input Voltage (Pins 3 and 4)
1. Maximum thermal limits must be observed.
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2
MC34060A, MC33060A
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 µF, RT = 12 kΩ, unless otherwise noted. For typical values TA = 25°C,
for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
Vref
4.925
4.9
4.85
5.0
–
–
5.075
5.1
5.1
V
Line Regulation (VCC = 7.0 V to 40 V, IO = 10 mA)
Regline
–
2.0
25
mV
Load Regulation (IO = 1.0 mA to 10 mA)
Regload
–
2.0
15
mV
Short Circuit Output Current (Vref = 0 V)
ISC
15
35
75
mA
IC(off)
–
2.0
100
µA
Emitter Off–State Current (VCC = 40 V, VCE = 40 V, VE = 0 V)
IE(off)
–
–
–100
µA
Collector–Emitter Saturation Voltage (Note 2)
Common–Emitter
(VE = 0 V, IC = 200 mA)
Emitter–Follower
(VC = 15 V, IE = –200 mA)
Vsat(C)
–
1.1
1.5
V
Vsat(E)
–
1.5
2.5
–
–
100
100
200
200
–
–
40
40
100
100
REFERENCE SECTION
Reference Voltage (IO = 1.0 mA, TA 25°C)
TA = Tlow to Thigh – MC34060A
TA = Tlow to Thigh – MC33060A
OUTPUT SECTION
Collector Off–State Current (VCC = 40 V, VCE = 40 V)
Output Voltage Rise Time (TA = 25°C)
Common–Emitter (See Figure 12)
Emitter–Follower (See Figure 13)
tr
Output Voltage Fall Time (TA = 25°C)
Common–Emitter (See Figure 12)
Emitter–Follower (See Figure 13)
tr
ns
ns
ERROR AMPLIFIER SECTION
Input Offset Voltage (VO[Pin 3] = 2.5 V)
VIO
–
2.0
10
mV
Input Offset Current (VC[Pin 3] = 2.5 V)
IIO
–
5.0
250
nA
Input Bias Current (VO[Pin 3] = 2.5 V)
IIB
–
–0.1
–2.0
µA
Input Common Mode Voltage Range
(VCC = 40 V)
VICR
0 to
VCC –2.0
–
–
V
VIR(INV)
–0.3 to
VCC–2.0
–
–
V
AVOL
70
95
–
dB
Unity–Gain Crossover Frequency
(VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)
fc
–
600
–
kHz
Phase Margin at Unity–Gain
(VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)
φm
–
65
–
deg.
Common Mode Rejection Ratio
(VCC = 40 V, Vin = 0 V to 38 V))
CMRR
65
90
–
dB
Power Supply Rejection Ratio
(∆VCC = 33 V, VO = 2.5 V, RL = 2.0 kΩ)
PSRR
–
100
–
dB
Inverting Input Voltage Range
Open–Loop Voltage Gain
(∆VO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)
Output Sink Current (VO[Pin 3] = 0.7 V)
IO–
0.3
0.7
–
mA
Output Source Current (VO[Pin 3] = 3.5 V)
IO+
–2.0
–4.0
–
mA
2. Low duty cycle techniques are used during test to maintain junction temperature as close to ambient temperatures as possible.
Thigh = +85°C for MC33060A
Tlow = –40°C for MC33060A
= 0°C for MC34060A
= +70°C for MC34060A
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3
MC34060A, MC33060A
ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V, CT = 0.01 µF, RT = 12 kΩ, unless otherwise noted.
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
VTH
–
3.5
4.5
V
II
0.3
0.7
–
mA
Input Bias Current (Pin 4)
(Vin = 0 V to 5.25 V)
IIB(DT)
–
–1.0
–10
µA
Maximum Output Duty Cycle
(Vin = 0 V, CT = 0.01 µF, RT = 12 kΩ)
(Vin = 0 V, CT = 0.001 µF, RT = 47 kΩ)
DCmax
90
–
96
92
100
–
–
0
2.8
–
3.3
–
9.7
9.5
9.0
–
10.5
–
–
25
11.3
11.5
11.5
–
σfosc
–
1.5
–
%
Frequency Change with Voltage
(VCC = 7.0 V to 40 V)
∆fosc(∆V)
–
0.5
2.0
%
Frequency Change with Temperature
(∆TA =Tlow to Thigh)
(CT = 0.01 µF, RT = 12 kΩ)
∆fosc(∆T)
–
–
4.0
–
–
–
PWM COMPARATOR SECTION (Test circuit Figure 11)
Input Threshold Voltage
(Zero Duty Cycle)
Input Sink Current
(V[Pin 3] = 0.7 V)
DEAD–TIME CONTROL SECTION (Test circuit Figure 11)
Input Threshold Voltage (Pin 4)
(Zero Duty Cycle)
(Maximum Duty Cycle)
%
VTH
V
OSCILLATOR SECTION
fosc
Frequency
(CT = 0.01 µF, RT = 12 kΩ, TA = 25°C)
TA = Tlow to Thigh – MC34060A
TA = Tlow to Thigh – MC33060A
(CT = 0.001 µF, RT = 47 kΩ)
Standard Deviation of Frequency*
(CT = 0.001 µF, RT = 47 kΩ)
kHz
%
UNDERVOLTAGE LOCKOUT SECTION
Turn–On Threshold (VCC increasing, Iref = 1.0 mA)
Vth
4.0
4.7
5.5
V
Hysteresis
VH
50
150
300
mV
TOTAL DEVICE
Standby Supply Current
(Pin 6 at Vref, all other inputs and outputs open)
(VCC = 15 V)
(VCC = 40 V)
ICC
Average Supply Current
(V[Pin 4] = 2.0 V, CT = 0.001 µF, RT = 47 kΩ). See Figure 11.
IS
mA
–
–
5.5
7.0
10
15
–
7.0
–
N
*Standard deviation is a measure of the statistical distribution about the mean as derived from the formula; σ =
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4
Σ (xn –x)2
n–1
N–1
mA
MC34060A, MC33060A
6
RT
CT
Dead-Time
Control
Reference
Regulator
Oscillator
5
0.12V
4
0.7V
-
VCC
Ref Out
+
VTH
9
PWM.
Comparator
1
1
2
Error Amp
1
12
-
≈ 0.7mA
-
Undervoltage
Lockout
-
+
+
+
Dead-Time
Comparator
10
2
3
Feedback/PWM
Comparator Input
Q1 8
+
Collector
Emitter
13
14
Error Amp
2
7
Gnd
This device contains 46 active transistors.
Figure 1. Block Diagram
Description
The MC34060A is a fixed–frequency pulse width
modulation control circuit, incorporating the primary
building blocks required for the control of a switching power
supply (see Figure 1). An internal–linear sawtooth oscillator
is frequency–programmable by two external components,
RT and CT. The approximate oscillator frequency is
determined by:
fosc Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
capacitor CT to either of two control signals. The output is
enabled only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase in control–signal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
1.2
RT • CT
For more information refer to Figure 3.
Capacitor CT
Feedback/P.W.M.
Comparator
Dead-Time Control
Output Q1,
Emitter
Figure 2. Timing Diagram
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5
MC34060A, MC33060A
APPLICATIONS INFORMATION
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
common mode input range from –0.3 V to (VCC –2.0 V), and
may be used to sense power supply output voltage and
current. The error–amplifier outputs are active high and are
ORed together at the noninverting input of the pulse–width
modulator comparator. With this configuration, the
amplifier that demands minimum output on time, dominates
control of the loop.
The MC34060A has an internal 5.0 V reference capable
of sourcing up to 10 mA of load currents for external bias
circuits. The reference has an internal accuracy of ±5% with
a typical thermal drift of less than 50 mV over an operating
temperature range of 0° to +70°C.
The control signals are external inputs that can be fed into
the dead–time control, the error amplifier inputs, or the
feed–back input. The dead–time control comparator has an
effective 120 mV input offset which limits the minimum
output dead time to approximately the first 4% of the
sawtooth–cycle time. This would result in a maximum duty
cycle of 96%. Additional dead time may be imposed on the
output by setting the dead time–control input to a fixed
voltage, ranging between 0 V to 3.3 V.
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent on–time, established by the dead time
control input, down to zero, as the voltage at the feedback
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A VOL , OPEN LOOP VOLTAGE GAIN (dB)
f osc , OSCILLATOR FREQUENCY (Hz)
500 k
VCC = 15 V
0.001 µF
100 k
10 k
CT = 0.01 µF
1.0 µF
1.0 k
500
1.0 k
5.0 k 10 k 20 k
50 k 100 k 200 k 500 k 1.0 M
RT, TIMING RESISTANCE (Ω)
2.0 k
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0
20
18
100
16
80
14
12
CT = 0.001 µF
10
8.0
6.0
AVOL
θ
10
0.01 µF
4.0
100 k
VCC = 15 V
CT = 0.001
RT = 47 k
60
40
20
2.0
0
500
1.0 k
10 k
100 k
fosc, OSCILLATOR FREQUENCY (Hz)
0
500 k
0
Figure 5. Percent Deadtime versus
Oscillator Frequency
3.5
V CE(SAT) , SATURATION VOLTAGE (V)
2.0
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
3.0
DEAD-TIME CONTROL VOLTAGE (V)
Figure 6. Percent Duty Cycle versus
Dead–Time Control Voltage
1.9
V CE(SAT) , SATURATION VOLTAGE (V)
100
1.0 k
10 k
f, FREQUENCY (Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
1.0 M
Figure 4. Open Loop Voltage Gain and Phase
versus Frequency
PERCENT DUTY CYCLE (%)
% DT, PERCENT DEADTIME, Q1 OUTPUT
Figure 3. Oscillator Frequency
versus Timing Resistance
VCC = 15 V
∆VO = 3.0 V
RL = 2.0 kΩ
θ , EXCESS PHASE (DEGREES)
MC34060A, MC33060A
0
100
200
300
IE, EMITTER CURRENT (mA)
400
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
500
0
100
200
300
400
IC, COLLECTOR CURRENT (mA)
Figure 8. Common–Emitter Configuration
Output Saturation Voltage versus
Collector Current
Figure 7. Emitter–Follower Configuration
Output Saturation Voltage versus
Emitter Current
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7
500
MC34060A, MC33060A
VTH , UNDERVOLTAGE LOCKOUT THRESHOLD (V)
10
I CC, SUPPLY CURRENT (mA)
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
0
5.0
10
15
20
25
30
35
40
VCC, SUPPLY VOLTAGE (V)
6.0
5.5
Turn On
5.0
Turn Off
4.5
4.0
0
5.0
10
15
20
25
30
35
40
IL, REFERENCE LOAD CURRENT (mA)
Figure 9. Standby Supply Current
versus Supply Voltage
Figure 10. Undervoltage Lockout Thresholds
versus Reference Load Current
VCC = 15V
+
Vin
Test
Inputs
Error Amplifier
Under Test
Feedback
RT
CT
(+)
(-)
Error
(+)
(-)
Feedback
Terminal
(Pin 3)
+
Vref
-
50kΩ
Output
C
E
Ref
Out
Gnd
Other Error
Amplifier
Figure 11. Error Amplifier Characteristics
Figure 12. Deadtime and Feedback Control
15V
RL
68Ω
C
CL
15pF
Output
Transistor
15V
Output
Transistor
VC
C
E
RL
68Ω
E
90%
VC
150Ω
2W
VCC
DeadTime
VE
CL
15pF
90%
90%
90%
VE
10%
10%
tr
10%
tf
10%
tr
tf
Figure 14. Emitter–Follower Configuration
and Waveform
Figure 13. Common–Emitter Configuration
and Waveform
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8
MC34060A, MC33060A
VO
To Output
Voltage of
System
Vref
R1
1
+
3
Vref
-
2
1
+
Error
Amp
R2
R2
3
Error
Amp
-
2
R1
Positive Output Voltage
Negative Output Voltage
R1
VO = Vref (1 +
)
R2
R1
VO = -Vref (1 +
)
R2
VO
To Output
Voltage of
System
Figure 15. Error Amplifier Sensing Techniques
R1
Vref
Output
Q
DT
6
RT
5
4
+
CT
R2
Output
47k
0.001
Max % On Time ≈ 92 -
Q
160
R
1+ 1
R2
DT
4
R2
Figure 16. Deadtime Control Circuit
Figure 17. Soft–Start Circuit
Vref
6
RT
Master
5
RT
R1
Vref
CT
CT
Vref
6
5
RT
Slave
CT
(Additional
Circuits)
Figure 18. Slaving Two or More Control Circuits
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9
-
CS
MC34060A, MC33060A
150µH @ 2.0A
Vin = 8.0V to 40V
Vout
Tip 32
5.0V/1.0A
47
4.7k
0.01
47k
1
MC34060A
+
0.01
13
12
E
Gnd
Vref
4
10/16V
150
+
4.7k
CT
5
+
MR850
-
DT
4.7k
9
Comp
14
4.7k
C
-
3
+
75
+
2
1.0M
50/50
10
VCC
8
7
RT
6
0.001
47k
390
0.1
Test
Conditions
Results
Line Regulation
Vin = 8.0 V to 40 V, IO = 1.0 A
25 mV
0.5%
Load Regulation
Vin = 12 V, IO = 1.0 mA to 1.0 A
3.0 mV
0.06%
Output Ripple
Vin = 12 V, IO = 1.0 A
75 mV p–p P.A.R.D.
Short Circuit Current
Vin = 12 V, RL = 0.1 Ω
1.6 A
Efficiency
Vin = 12 V, IO = 1.0 A
73%
Figure 19. Step–Down Converter with Soft–Start
and Output Current Limiting
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10
1000
6.3V
MC34060A, MC33060A
150µH @ 4.0A
Vin = 8.0V to 26V
20µH @ 1.0A
*
MR850
Vout
28V/
0.5A
22k
10
0.05
33k
4.7k
50/35V
1
2
2.7M
3
+
14
3.9k
13
12
VCC
+
C
-
9
Comp
+
MC34060A
+
-
E
Vref
Gnd
DT
4.7k
4
CT
8
300
Tip 111
7
0.1
RT
6
5
0.001
47k
470
390
Test
Conditions
Results
Line Regulation
Vin = 8.0 V to 26 V, IO = 0.5 A
Load Regulation
Vin = 12 V, IO = 1.0 mA to 0.5 A
Output Ripple
Vin = 12 V, IO = 0.5 A
24 mV p–p P.A.R.D.
Efficiency
Vin = 12 V, IO = 0.5 A
75%
*Optional circuit to minimize output ripple
Figure 20. Step–Up Converter
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11
40 mV 0.14%
5.0 mV 0.18%
+
470/
35V
*
470/
35V
MC34060A, MC33060A
Vin = 8.0V to 40V
Tip 32C
Vout
MR851
20µH *
@ 1.0A
47
-15V/
0.25A
30k
10
0.01
47k
7.5k
50/50V
1
2
1.0M
3
+
14
0.01
13
12
C
-
150µH
@ 2.0A
MC34060A
+
-
E
Vref
Gnd
DT
10/16V
4
CT
+
*
330/
+ 16V
330/
16V
8
7
RT
5
6
0.001
4.7k
3.3k
9
Comp
10k
47k
75
VCC
+
47k
820
1.0
Test
Conditions
Results
Line Regulation
Vin = 8.0 V to 40 V, IO = 250 mA
52 mV
0.35%
Load Regulation
Vin = 12 V, IO = 1.0 to 250 mA
47 mV
0.32%
Output Ripple
Vin = 12 V, IO = 250 mA
Short Circuit Current
Vin = 12 V, RL = 0.1 Ω
Efficiency
Vin = 12 V, IO = 250 mA
10 mV p–p P.A.R.D.
330 mA
86%
*Optional circuit to minimize output ripple
Figure 21. Step–Up/Down Voltage Inverting Converter
with Soft–Start and Current Limiting
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12
T2
1N4003
3 each
0.0047 UL/CSA
*
T1
*
*
2200/10V
3/200
Vac
1N4934
1N4001
+
*
180/200V
1
1N4742
1.0A
47/25V
22k
2
T
15Ω
Cold
2.2M
7.5k
1N4687
6.8k
3
14
13
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13
12
8.2k
C
Comp
1.5k
1N4937
E
Gnd
Vref
DT
4
CT
RT
5
6
10/25V
8
10/35V
L3
Common
+
10/35V
1N4934
200
0.001
10
47
47k
1.0
11k
Conditions
MJE
13005
+
MPS
A55
7
1N4148
Test
+
MPS
A05
MC34060A
-
27k
0.01
9
+
+
Pout
25k
1000/25V
12/075A
+
-12/0.75A
-
*Optional R.F.I. Filter
Vout
5.0k
+
+
100/10V
5.0V/3.0A
+
L2
1N4934
1000/25V
+
+
2.7k
Results
Line Regulation 5.0 V
V in = 95 Vac to 135 Vac, IO = 3.0 A
20 mV 0.40%
Line Regulation ±12 V
V in = 95 Vac to 135 Vac, IO = ±0.75 A
52 mV 0.26%
Load Regulation 5.0 V
V in = 115 Vac, IO = 1.0 A to 4.0 A
476 mV 9.5%
Load Regulation ±12 V
V in = 115 Vac, IO = ±0.4 A to ±0.9 A
Output Ripple 5.0 V
V in = 115 Vac, IO = 3.0 A
45 mV p–p P.A.R.D.
Output Ripple ±12 V
V in = 115 Vac, IO = ±0.75 A
75 mV p–p P.A.R.D.
Efficiency
V in = 115 Vac, IO 5.0 V = 3.0 A
IO ±12 V = ±0.75 A
300 mV 2.5%
74%
T1 – Coilcraft W2961
T2 – Core: Coilcraft 11–464–16,
0.025″ gap in each leg.
Bobbin: Coilcraft 37–573
Windings:
Primary, 2 each, 75 turns #25 Awg Bifilar wound
Feedback: 15 turns #26 Awg
Secondary, 5.0 V, 6 turns @33 Awg Bifilar wound
Secondary, 2 each, 14 turns #24 Awg Bifilar wound
L1 – Coilcraft Z7156, 15 µH @ 5.0 A
L2, L3 – Coilcraft Z7157, 25 µH @ 1.0 A
Figure 22. 33 W Off–Line Flyback Converter with Soft–Start and Primary Power Limiting
MC34060A, MC33060A
115 Vac
± 20%
33k
0.01
10
VCC
L1
1N5824
MC34060A, MC33060A
ORDERING INFORMATION
Device
Operating
Temperature Range
MC34060AD
MC34060ADR2
Package
Shipping
SO–14
55 Units/Rail
SO–14
2500 Tape & Reel
MC34060AP
PDIP–14
25 Units/Rail
MC33060AD
SO–14
55 Units/Rail
SO–14
2500 Tape & Reel
PDIP–14
25 Units/Rail
MC33060ADR2
TA= 0° to +70°C
TA= –40° to +85°C
MC33060AP
http://onsemi.com
14
MC34060A, MC33060A
PACKAGE DIMENSIONS
PDIP–14
P SUFFIX
CASE 646–06
ISSUE M
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
N
C
–T–
SEATING
PLANE
J
K
H
D 14 PL
G
M
0.13 (0.005)
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
--10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
--10
0.38
1.01
M
SO–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
F
R X 45 C
–T–
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
K
M
T B
S
A
S
http://onsemi.com
15
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019
MC34060A, MC33060A
SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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16
MC34060A/D