ETC UC3842B/D

UC3842B, UC3843B,
UC2842B, UC2843B
High Performance
Current Mode Controllers
The UC3842B, UC3843B series are high performance fixed
frequency current mode controllers. They are specifically designed for
Off–Line and dc–to–dc converter applications offering the designer a
cost–effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle–by–cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8–pin dual–in–line and surface
mount (SO–8) plastic package as well as the 14–pin plastic surface
mount (SO–14). The SO–14 package has separate power and ground
pins for the totem pole output stage.
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off–line converters. The UCX843B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
• Trimmed Oscillator for Precise Frequency Control
• Oscillator Frequency Guaranteed at 250 kHz
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
VCC
Vref
8(14)
5.0V
Reference
R
2(3)
Output
Compensation
1(1)
7(11)
6(10)
Power
Ground
5(8)
Latching
PWM
Error
Amplifier
Current
Sense
3(5) Input
Gnd
8
1
SO–8
D1 SUFFIX
CASE 751
8
1
SO–14
D SUFFIX
CASE 751A
14
1
PIN CONNECTIONS
Compensation
Voltage Feedback
Current Sense
RT/CT
1
8
2
7
3
6
4
5
Vref
VCC
Output
Gnd
(Top View)
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Vref
NC
VCC
VC
Output
Gnd
Power Ground
(Top View)
Output
+
-
PDIP–8
N SUFFIX
CASE 626
VC
Oscillator
4(7)
Voltage
Feedback
Input
VCC
Undervoltage
Lockout
Vref
Undervoltage
Lockout
R
RT/CT
7(12)
http://onsemi.com
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 17 of this data sheet.
5(9)
Pin numbers in parenthesis are for the D suffix SO-14 package.
Figure 1. Simplified Block Diagram
 Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1
Publication Order Number:
UC3842B/D
UC3842B, UC3843B, UC2842B, UC2843B
MAXIMUM RATINGS
Symbol
Value
Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec)
Rating
VCC, VC
30
V
Total Power Supply and Zener Current
(ICC + IZ)
30
mA
IO
1.0
A
Output Current, Source or Sink (Note 1.)
Output Energy (Capacitive Load per Cycle)
W
5.0
µJ
Current Sense and Voltage Feedback Inputs
Vin
– 0.3 to + 5.5
V
Error Amp Output Sink Current
IO
10
mA
PD
RθJA
862
145
mW
°C/W
PD
RθJA
702
178
mW
°C/W
PD
RθJA
1.25
100
W
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature
UC3842B, UC3843B
UC2842B, UC2843B
UC3842BV, UC3843BV
TA
Storage Temperature Range
Tstg
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SO–14 Case 751A
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
D1 Suffix, Plastic Package, SO–8 Case 751
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
°C
0 to + 70
– 25 to + 85
–40 to +105
°C
– 65 to +150
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2.], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 3.], unless otherwise noted.)
UC284XB
Characteristics
UC384XB, XBV
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Vref
4.95
5.0
5.05
4.9
5.0
5.1
V
Line Regulation (VCC = 12 V to 25 V)
Regline
–
2.0
20
–
2.0
20
mV
Load Regulation (IO = 1.0 mA to 20 mA)
Regload
–
3.0
25
–
3.0
25
mV
mV/°C
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Temperature Stability
TS
–
0.2
–
–
0.2
–
Total Output Variation over Line, Load, and Temperature
Vref
4.9
–
5.1
4.82
–
5.18
V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C)
Vn
–
50
–
–
50
–
µV
Long Term Stability (TA = 125°C for 1000 Hours)
Output Short Circuit Current
S
–
5.0
–
–
5.0
–
mV
ISC
– 30
– 85
–180
– 30
– 85
–180
mA
49
48
225
52
–
250
55
56
275
49
48
225
52
–
250
55
56
275
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
fOSC
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V)
∆fOSC/∆V
–
0.2
1.0
–
0.2
1.0
%
Frequency Change with Temperature
TA = Tlow to Thigh
∆fOSC/∆T
–
1.0
–
–
0.5
–
%
Oscillator Voltage Swing (Peak–to–Peak)
VOSC
–
1.6
–
–
1.6
–
V
Discharge Current (VOSC = 2.0 V)
TJ = 25°C
TA = Tlow to Thigh (UC284XB, UC384XB)
TA = Tlow to Thigh (UC384XBV)
Idischg
7.8
7.5
–
8.3
–
–
8.8
8.8
–
7.8
7.6
7.2
8.3
–
–
8.8
8.8
8.8
mA
1. Maximum Package power dissipation limits must be observed.
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = +70°C for UC3842B, UC3843B
Tlow = 0°C for UC3842B, UC3843B
–25°C for UC2842B, UC2843B
+85°C for UC2842B, UC2843B
–40°C for UC3842BV, UC3843BV
+105°C for UC3842BV, UC3843BV
http://onsemi.com
2
UC3842B, UC3843B, UC2842B, UC2843B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 4.], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 5.], unless otherwise noted.)
UC284XB
Characteristics
UC384XB, XBV
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
VFB
2.45
2.5
2.55
2.42
2.5
2.58
V
IIB
–
– 0.1
–1.0
–
– 0.1
– 2.0
µA
AVOL
65
90
–
65
90
–
dB
BW
0.7
1.0
–
0.7
1.0
–
MHz
PSRR
60
70
–
60
70
–
dB
ISink
2.0
– 0.5
12
–1.0
–
–
2.0
– 0.5
12
–1.0
–
–
5.0
6.2
–
5.0
6.2
–
–
–
0.8
–
1.1
–
–
–
0.8
0.8
1.1
1.2
2.85
–
3.0
–
3.15
–
2.85
2.85
3.0
3.0
3.15
3.25
0.9
–
1.0
–
1.1
–
0.9
0.85
1.0
1.0
1.1
1.1
PSRR
–
70
–
–
70
–
dB
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 5.0 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Unity Gain Bandwidth (TJ = 25°C)
Power Supply Rejection Ratio (VCC = 12 V to 25 V)
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
mA
ISource
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
(UC284XB, UC384XB)
(UC384XBV)
V
VOH
VOL
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6. & 7.)
(UC284XB, UC384XB)
(UC384XBV)
AV
Maximum Current Sense Input Threshold (Note 6.)
(UC284XB, UC384XB)
(UC384XBV)
Vth
Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 6.)
V/V
V
IIB
–
– 2.0
–10
–
– 2.0
–10
µA
tPLH(In/Out)
–
150
300
–
150
300
ns
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA)
VOL
High State
VOH
–
–
–
13
–
12
0.1
1.6
–
13.5
–
13.4
0.4
2.2
–
–
–
–
–
–
–
13
12.9
12
0.1
1.6
1.6
13.5
13.5
13.4
0.4
2.2
2.3
–
–
–
VOL(UVLO)
–
0.1
1.1
–
0.1
1.1
V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
tr
–
50
150
–
50
150
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
tf
–
50
150
–
50
150
ns
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
Input Bias Current
Propagation Delay (Current Sense Input to Output)
OUTPUT SECTION
V
(UC284XB, UC384XB)
(UC384XBV)
(ISource = 20 mA) (UC284XB, UC384XB)
(UC384XBV)
(ISource = 200 mA)
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC)
UCX842B, BV
UCX843B, BV
Vth
Minimum Operating Voltage After Turn–On (VCC)
UCX842B, BV
UCX843B, BV
V
VCC(min)
V
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B
Thigh = +70°C for UC3842B, UC3843B
–25°C for UC2842B, UC2843B
+85°C for UC2842B, UC2843B
–40°C for UC3842BV, UC3843BV
+105°C for UC3842BV, UC3843BV
6. This parameter is measured at the latch trip point with VFB = 0 V.
7. Comparator gain is defined as: AV ∆V Output Compensation
∆V Current Sense Input
http://onsemi.com
3
UC3842B, UC3843B, UC2842B, UC2843B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 8.], RT = 10 k, CT = 3.3 nF, for typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 9.], unless otherwise noted.)
UC284XB
Characteristics
UC384XB, BV
Symbol
Min
Typ
Max
Min
Typ
Max
DC(max)
94
–
–
96
–
–
–
–
0
94
93
–
96
96
–
–
–
0
–
0.3
0.5
–
0.3
0.5
–
12
17
–
12
17
30
36
–
30
36
–
Unit
PWM SECTION
%
Duty Cycle
Maximum (UC284XB, UC384XB)
Maximum (UC384XBV)
Minimum
DC(min)
TOTAL DEVICE
ICC + IC
Power Supply Current
Startup (VCC = 6.5 V for UCX843B,
Startup (VCC 14 V for UCX842B, BV)
Operating (Note 8.)
Power Supply Zener Voltage (ICC = 25 mA)
mA
VZ
V
8. Adjust VCC above the Startup threshold before setting to 15 V.
9. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = +70°C for UC3842B, UC3843B
Tlow = 0°C for UC3842B, UC3843B
–25°C for UC2842B, UC2843B
+85°C for UC2842B, UC2843B
–40°C for UC3842BV, UC3843BV
+105°C for UC3842BV, UC3843BV
80
100
% DT, PERCENT OUTPUT DEADTIME
R T, TIMING RESISTOR (k Ω)
50
20
8.0
5.0
2.0
0.8
10 k
VCC = 15 V
TA = 25°C
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1. CT = 10 nF
50 2. CT = 5.0 nF
3. CT = 2.0 nF
4. CT = 1.0 nF
20 5. CT = 500 pF
6. CT = 200 pF
10 7. CT = 100 pF
D max , MAXIMUM OUTPUT DUTY CYCLE (%)
I dischg , DISCHARGE CURRENT (mA)
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
6
7
VCC = 15 V
TA = 25°C
2.0
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0 M
Figure 3. Output Deadtime
versus Oscillator Frequency
9.0
-25
1
5
Figure 2. Timing Resistor
versus Oscillator Frequency
7.0
-55
3
2
5.0
1.0
10 k
1.0 M
4
100
125
100
90
80
Idischg = 7.5 mA
70
Idischg = 8.8 mA
60
50
40
0.8
Figure 4. Oscillator Discharge Current
versus Temperature
1.0
2.0
3.0
4.0
RT, TIMING RESISTOR (kΩ)
VCC = 15 V
CT = 3.3 nF
TA = 25°C
5.0 6.0 7.0 8.0
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
http://onsemi.com
4
UC3842B, UC3843B, UC2842B, UC2843B
VCC = 15 V
AV = -1.0
TA = 25°C
20 mV/DIV
2.50 V
VCC = 15 V
AV = -1.0
TA = 25°C
3.0 V
20 mV/DIV
2.55 V
2.5 V
2.45 V
2.0 V
0.5 µs/DIV
1.0 µs/DIV
80
Gain
60
40
Phase
0
30
60
90
20
120
0
150
100
10 k
100 k
180
10 M
1.0 M
VCC = 15 V
1.0
0.8
TA = 25°C
0.6
TA = 125°C
0.4
TA = -55°C
0.2
0
0
2.0
4.0
6.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄ ÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
VCC = 15 V
-4.0
-8.0
-12
TA = -55°C
TA = 125°C
-16
-20
TA = 25°C
0
1.2
f, FREQUENCY (Hz)
0
-24
1.0 k
I SC , REFERENCE SHORT CIRCUIT CURRENT (mA)
-20
10
∆ Vref , REFERENCE VOLTAGE CHANGE (mV)
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25°C
φ, EXCESS PHASE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
100
Figure 7. Error Amp Large Signal
Transient Response
Vth, CURRENT SENSE INPUT THRESHOLD (V)
Figure 6. Error Amp Small Signal
Transient Response
20
40
60
80
100
120
8.0
ÄÄÄ
ÄÄÄ
110
VCC = 15 V
RL ≤ 0.1 Ω
90
70
50
-55
-25
0
25
50
75
100
Iref, REFERENCE SOURCE CURRENT (mA)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
http://onsemi.com
5
125
∆ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV
∆ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV
UC3842B, UC3843B, UC2842B, UC2843B
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
2.0 ms/DIV
VCC = 12 V to 25
TA = 25°C
2.0 ms/DIV
0
-2.0
Source Saturation
(Load to Ground)
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90%
TA = -55°C
2.0
TA = 25°C
200
Gnd
400
600
10%
800
IO, OUTPUT LOAD CURRENT (mA)
50 ns/DIV
Figure 14. Output Saturation Voltage
versus Load Current
Figure 15. Output Waveform
V O , OUTPUT VOLTAGE
25
20 V/DIV
20
15
10
5
0
0
100 ns/DIV
10
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
UCX842B
VCC = 30 V
CL = 15 pF
TA = 25°C
UCX843B
0
Sink Saturation
(Load to VCC)
I CC , SUPPLY CURRENT (mA)
1.0
I CC , SUPPLY CURRENT
VCC = 15 V
80 µs Pulsed Load
120 Hz Rate
TA = -55°C
3.0
0
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄ
ÄÄÄÄ ÄÄÄ
ÄÄÄ
ÄÄÄÄ ÄÄ
VCC
TA = 25°C
-1.0
Figure 13. Reference Line Regulation
100 mA/DIV
Vsat, OUTPUT SATURATION VOLTAGE (V)
Figure 12. Reference Load Regulation
20
30
40
VCC, SUPPLY VOLTAGE (V)
Figure 16. Output Cross Conduction
Figure 17. Supply Current versus Supply Voltage
http://onsemi.com
6
UC3842B, UC3843B, UC2842B, UC2843B
PIN FUNCTION DESCRIPTION
Pin
8–Pin
14–Pin
Function
1
1
Compensation
2
3
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
3
5
Current
Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4
7
RT/CT
6
10
Output
7
12
VCC
This pin is the positive supply of the control IC.
8
14
Vref
This is the reference output. It provides charging current for capacitor C T through resistor RT.
8
Power
Ground
11
VC
9
Gnd
This pin is the control circuitry ground return and is connected back to the power
source ground.
2,4,6,13
NC
No connection. These pins are not internally connected.
5
Gnd
Description
This pin is the Error Amplifier output and is made available for loop compensation.
The Oscillator frequency and maximum Output duty cycle are programmed by
connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz
is possible.
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin.
This pin is a separate power ground return that is connected back to the power source. It is
used to reduce the effects of switching transient noise on the control circuitry.
The Output high state (VOH) is set by the voltage applied to this pin. With a separate
power source connection, it can reduce the effects of switching transient noise on the
control circuitry.
http://onsemi.com
7
UC3842B, UC3843B, UC2842B, UC2843B
OPERATING DESCRIPTION
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft–start interval
(Figures 24, 25). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
The UC3842B, UC3843B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost–effective solution
with minimal external components. A representative block
diagram is shown in Figure 18.
Rf(min) ≈
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 2 shows RT versus Oscillator Frequency
and Figure 3, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency.
The oscillator thresholds are temperature compensated to
within ±6% at 50 kHz. Also because of industry trends
moving the UC384X into higher and higher frequency
applications, the UC384XB is guaranteed to within ±10% at
250 kHz. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 4 and 5.
In many noise–sensitive applications it may be desirable
to frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 21. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi–unit
synchronization is shown in Figure 22. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved.
3.0 (1.0 V) + 1.4 V
= 8800 Ω
0.5 mA
Current Sense Comparator and PWM Latch
The UC3842B, UC3843B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle–by–cycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground–referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
Ipk =
V(Pin 1) – 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 23. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 27).
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
non–inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is –2.0 µA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 32). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the non–inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when pin 1 is at its lowest state (VOL).
http://onsemi.com
8
UC3842B, UC3843B, UC2842B, UC2843B
VCC
VCC
Vref
2.5V
RT
CT
R
Output/
Compensation 1(1)
(See
Text)
Output
Q1
6(10)
+ 1.0mA
S
2R
R
Error
Amplifier
VC
7(11)
Vref
UVLO
Oscillator
4(7)
Voltage
Feedback
Input 2(3)
+
-
3.6V
+
-
VCC
UVLO
Internal
Bias
R
7(12)
36V
Reference
Regulator
8(14)
Vin
R
1.0V
Q
Power Ground
PWM
Latch
Current Sense
Comparator
Gnd
5(8)
Current Sense Input
3(5)
5(9)
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package.
Pin numbers in parenthesis are for the D suffix SO-14 package.
= Sink Only Positive True Logic
Figure 18. Representative Block Diagram
Capacitor CT
Latch
Set" Input
Output/
Compensation
Current Sense
Input
Latch
Reset" Input
Output
Small RT/Large CT
Large RT/Small CT
Figure 19. Timing Diagram
http://onsemi.com
9
RS
UC3842B, UC3843B, UC2842B, UC2843B
Undervoltage Lockout
Design Considerations
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The Vref comparator
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in off–line converter applications where
efficient bootstrap startup techniques are required
(Figure 34). The UCX843B is intended for lower voltage
dc–to–dc converter applications. A 36 V zener is connected
as a shunt regulator from VCC to ground. Its purpose is to
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage (VCC) for
the UCX842B is 11 V and 8.2 V for the UCX843B.
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate pins
for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 26 shows proper
power and control ground connections in a current–sensing
power MOSFET application.
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise–generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2, until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small ∆I (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn–on (t2) is increased
by ∆I + ∆I m2/m1. The minimum current at the next cycle (t3)
decreases to (∆I + ∆I m2/m1) (m2/m1). This perturbation is
multiplied by m2/m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn–on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the ∆I perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short–
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
http://onsemi.com
10
UC3842B, UC3843B, UC2842B, UC2843B
(A)
∆I
Control Voltage
m2
m1
Inductor
Current
l l m2
m1
l l m2 m2
m1 m1
Oscillator Period
t0
t1
Vref
8(14)
t2
External
Sync
Input
m3
∆I
m1
Bias
RT
t3
(B)
Control Voltage
R
0.01
Osc
4(7)
CT
+
2R
2(3)
47
m2
R
Inductor
Current
R
EA
1(1)
Oscillator Period
t4
5(9)
t5
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of CT to go more than 300 mV below ground.
t6
Figure 20. Continuous Current Waveforms
Figure 21. External Clock Synchronization
VCC
Vin
7(12)
5.0V Ref
8(14)
8(14)
RA
RB
6
3
5.0k
2
C
R
Q
2R
S
5.0k
MC1455
2(3)
EA
1(1)
f 1.44
(RA 2RB)C
D(max) RB
RA 2RB
R
2R
R
EA
1.0V
R
R1
5(9)
To Additional
UCX84XBs
Figure 22. External Duty Cycle Clamp and
Multi–Unit Synchronization
S
1.0 mA
2(3)
1
6(10)
VClamp
+
R2
+
7
Q1
Osc
4(7)
Osc
4(7)
7(11)
+
-
R
4
5.0k
+
-
Bias
R
Bias
8
R
5
R
Q
5(8)
Comp/Latch
3(5)
1(1)
5(9)
VClamp ≈
1.67
R2
1
R1
+ 0.33x10-3
R1R1R2R2
Where: 0 ≤ VClamp ≤ 1.0 V
Ipk(max) VClamp
RS
Figure 23. Adjustable Reduction of Clamp Level
http://onsemi.com
11
RS
UC3842B, UC3843B, UC2842B, UC2843B
VCC
Vin
7(12)
5.0V Ref
8(14)
Bias
5.0V Ref
8(14)
R
R
1.0 mA
EA
1.0M
Q
C
1.0V
R1
3(5)
MPSA63
1.67
RR21 1
5(9)
tSoft-Start ≈ 3600C in µF
tSoftStart In 1 Figure 24. Soft–Start Circuit
VPin 5 (12)
Where: 0 ≤ VClamp ≤ 1.0 V
VC
R1R2
C
R1 R2
3VClamp
5.0V Ref
RS Ipk rDS(on)
rDM(on) RS
VClamp
RS
VCC
D
(11)
(10)
5.0V Ref
+
-
SENSEFET
S
G
7(11)
+
-
K
Q1
M
6(10)
S
Q
S
(8)
R
Comp/Latch
RS
1/4 W
Vin
7(12)
Then : VPin5 0.075Ipk
+
-
(5)
Ipk(max) Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft–Start
If: SENSEFET = MTP10N10M
RS = 200
R
RS
Vin
VCC
+
-
5(8)
Comp/Latch
5(9)
VClamp 1(1)
C
Q
1(1)
R
2R
R
1.0V
R2
S
1.0mA
6(10)
S
R
2R
R
EA
2(3)
+
2(3)
VClamp
+
Osc
4(7)
Q1
Osc
4(7)
+
-
7(11)
+
-
Bias
R
+
-
R
Power Ground:
To Input Source
Return
Comp/Latch
Q
5(8)
3(5)
R
C
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over-current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25.
RS
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 26. Current Sensing Power MOSFET
Figure 27. Current Waveform Spike Suppression
http://onsemi.com
12
UC3842B, UC3843B, UC2842B, UC2843B
VCC
Vin
IB
7(12)
Vin
+
0
5.0V Ref
+
-
Base Charge
Removal
7(11)
+
-
C1
Rg
Q1
Q1
6(10)
6(10)
S
Q
R
5(8)
5(8)
Comp/Latch
3(5)
RS
3(5)
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in
the gate-source circuit.
The totem pole output can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C1.
Figure 28. MOSFET Parasitic Oscillations
Figure 29. Bipolar Transistor Drive
Vin
VCC
8(14)
R
Isolation
Boundary
5.0V Ref
Q1
+
0
50% DC
6(10)
Comp/Latch
0
-
2(3)
25% DC
5(8)
V(Pin1) 1.4 NS
Ipk Np
3RS
R
3(5)
C
RS
NS
1.0 mA
+
-
Q
+
VGS Waveforms
7(11)
S
Osc
4(7)
+
-
+
-
R
Bias
7(12)
R
RS
EA
2R
R
1(1)
MCR
101
2N
3905
5(9)
2N
3903
NP
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
Figure 30. Isolated MOSFET Drive
Figure 31. Latched Shutdown
http://onsemi.com
13
UC3842B, UC3843B, UC2842B, UC2843B
From VO
2.5V
Ri
+
1.0mA 2R
2(3)
Cf
Rd
EA
Rf
R
1(1)
Rf ≥ 8.8 k
5(9)
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
From VO
Rp
Cp
2.5V
Ri
+
1.0mA
2(3)
Cf
Rd
2R
R
EA
Rf
1(1)
5(9)
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
Figure 32. Error Amplifier Compensation
VCC
Vin
7(12)
36V
8(14)
RT
MPS3904
RSlope
From VO
CT
Ri
Rd
5.0V Ref
R
R
+
-
Rf
1(1)
7(11)
Osc
4(7)
+
2(3)
Cf
+
-
Bias
EA
1.0mA
-m
S
2R
R
R
1.0V
6(10)
Q
Comp/Latch
m
- 3.0m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
Figure 33. Slope Compensation
http://onsemi.com
14
5(8)
3(5)
RS
UC3842B, UC3843B, UC2842B, UC2843B
+
MDA
202
4.7k
250
3300
pF
56k
115 Vac
1N4935
7(12)
+
8(14)
10k
68
4.7k
100
pF
6(10)
R
EA
150k
3(5)
470pF
Figure 34. 27 W Off–Line Flyback Regulator
Results
Line Regulation: 5.0 V
±12 V
Vin = 95 to 130 Vac
∆ = 50 mV or ± 0.5%
∆ = 24 mV or ± 0.1%
Load Regulation: 5.0 V
Vin = 115 Vac,
Iout = 1.0 A to 4.0 A
Vin = 115 Vac,
Iout = 100 mA to 300 mA
∆ = 300 mV or ± 3.0%
±12 V
Efficiency
MTP
4N50
1N5819
1.0k
5(9)
Output Ripple:
2.7k
5(8)
Comp/Latch
Conditions
5.0 V
±12 V
5.0V/4.0A
5.0V RTN
+ L2
10
+
12V/0.3A
±12V RTN
1000
Q
1(1)
Test
1000
+
22
S
2(3)
+
MUR110
680pF
+
+
1000
MUR110
+
10
+
-12V/0.3A
L3
7(11)
Osc
4(7)
4700pF
18k
+
47
+
-
Bias
R
2200
1N4937
5.0V Ref
R
T1
1N4935
100
0.01
L1
MBR1635
4.7Ω
∆ = 60 mV or ± 0.25%
Vin = 115 Vac
40 mVpp
80 mVpp
Vin = 115 Vac
70%
All outputs are at nominal load currents, unless otherwise noted
http://onsemi.com
15
0.5
1N4937
L1 - 15 µH at 5.0 A, Coilcraft Z7156
L2, L3 - 25 µH at 5.0 A, Coilcraft Z7157
T1 - Primary: 45 Turns #26 AWG
Secondary ±12 V: 9 Turns #30 AWG
(2 Strands) Bifiliar Wound
Secondary 5.0 V: 4 Turns (six strands)
#26 Hexfiliar Wound
Secondary Feedback: 10 Turns
#30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance
of 1.0 mH
UC3842B, UC3843B, UC2842B, UC2843B
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
Shipping
UC384XBD
SO–14
55 Units/Rail
UC384XBDR2
SO–14
2500 Tape & Reel
UC384XBD1
SO–8
98 Units/Rail
SO–8
2500 Tape & Reel
UC384XBN
PDIP–8
50 Units/Rail
UC3842BN1
PDIP–8
50 Units/Rail
UC284XBD
SO–14
55 Units/Rail
UC2843BDR2
SO–14
2500 Tape & Reel
UC384XBD1R2
UC284XBD1
TA = 0° to +70°C
SO–8
98 Units/Rail
SO–8
2500 Tape & Reel
UC284XBN
PDIP–8
50 Units/Rail
UC3843BVD
SO–14
55 Units/Rail
UC384XBVDR2
SO–14
2500 Tape & Reel
SO–8
98 Units/Rail
SO–8
2500 Tape & Reel
PDIP–8
50 Units/Rail
TA = –25° to +85°C
UC284XBD1R2
UC384XBVD1
TA = –40° to +105°C
UC384XBVD1R2
UC3843BVN
X indicates either a 2 or 3 to define specific device part numbers.
http://onsemi.com
16
UC3842B, UC3843B, UC2842B, UC2843B
MARKING DIAGRAMS
PDIP–8
N SUFFIX
CASE 626
8
8
UC384xBN
FAWL
YYWW
8
UC3843BVN
AWL
YYWW
1
UC284xBN
AWL
YYWW
1
1
SO–8
D1 SUFFIX
CASE 751
8
8
384xB
ALYW
8
384xB
ALYWV
1
1
284xB
ALYW
1
SO–14
D SUFFIX
CASE 751A
14
14
UC384xBD
AWLYWW
1
14
UC384xBVD
AWLYWW
1
UC284xBD
AWLYWW
1
x
A
WL, L
YY, Y
WW, W
= 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
http://onsemi.com
17
UC3842B, UC3843B, UC2842B, UC2843B
PACKAGE DIMENSIONS
PDIP–8
N SUFFIX
CASE 626–05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
SO–8
D1 SUFFIX
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
http://onsemi.com
18
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
UC3842B, UC3843B, UC2842B, UC2843B
PACKAGE DIMENSIONS
SO–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
F
R X 45 C
–T–
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
K
M
T B
S
A
S
http://onsemi.com
19
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019
UC3842B, UC3843B, UC2842B, UC2843B
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)
Email: ONlit–[email protected]
French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET)
Email: ONlit–[email protected]
English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)
Email: [email protected]
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–[email protected]
Toll–Free from Mexico: Dial 01–800–288–2872 for Access –
then Dial 866–297–9322
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–[email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy, UK, Ireland
For additional information, please contact your local
Sales Representative.
http://onsemi.com
20
UC3842B/D