MC74AC253, MC74ACT253 Dual 4−Input Multiplexer with 3−State Outputs The MC74AC253/74ACT253 is a dual 4−input multiplexer with 3−state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems. • • • • w Multifunctional Capability Noninverting 3−State Outputs Outputs Source/Sink 24 mA ′ACT253 Has TTL Compatible Inputs http://onsemi.com DIP−16 N SUFFIX CASE 648 16 1 These devices are available in Pb−free package(s). Specifications herein apply to both standard and Pb−free devices. Please see our website at www.onsemi.com for specific Pb−free orderable part numbers, or contact your local ON Semiconductor sales office or representative. VCC OEb S0 I3b I2b I1b I0b Zb 16 15 14 13 12 11 10 9 16 1 16 1 2 3 4 5 6 7 8 OEa S1 I3a I2a I1a I0a Za GND 16 Figure 1. Pinout: 16−Lead Packages Conductors (Top View) FUNCTION I0a−I3a Side A Data Inputs I0b−I3b Side B Data Inputs S0, S1 Common Select Inputs OEa Side A Output Enable Input OEb Side B Output Enable Input Za, Zb 3−State Outputs 1 TSSOP−16 DT SUFFIX CASE 948F EIAJ−16 M SUFFIX CASE 966 ORDERING INFORMATION Device PIN NAME PIN 1 SO−16 D SUFFIX CASE 751B Package Shipping MC74AC253N PDIP−16 25 Units/Rail MC74ACT253N PDIP−16 25 Units/Rail MC74AC253D SOIC−16 48 Units/Rail MC74ACT253D SOIC−16 48 Units/Rail MC74AC253DR2 SOIC−16 2500 Tape & Reel MC74ACT253DR2 SOIC−16 2500 Tape & Reel MC74AC253DT TSSOP−16 96 Units/Rail MC74ACT253DT TSSOP−16 96 Units/Rail MC74AC253DTR2 TSSOP−16 2500 Tape & Reel MC74ACT253DTR2 TSSOP−16 2500 Tape & Reel MC74AC253M EIAJ−16 50 Units/Rail MC74ACT253M EIAJ−16 50 Units/Rail MC74AC253MEL EIAJ−16 2000 Tape & Reel MC74ACT253MEL EIAJ−16 2000 Tape & Reel DEVICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 6 1 Publication Order Number: MC74AC253/D MC74AC253, MC74ACT253 TRUTH TABLE Select Inputs Data Inputs Output Enable Outputs S0 S1 I0 I1 I2 I3 OE Z X L L H H L L H H X L L L L H H H H X L H X X X X X X X X X L H X X X X X X X X X L H X X X X X X X X X L H H L L L L L L L L Z L H L H L H L H OEa I0a I1a I2a I3a I0b I1b I2b I3b OEb S0 S1 Za Zb Figure 2. Logic Symbol Address inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance FUNCTIONAL DESCRIPTION supplied to the two select inputs. The logic equations for the outputs are shown: The MC74AC253/74ACT253 contains two identical 4−input multiplexers with 3−state outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4−input multiplexers have individual Output Enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2−pole, 4−position switch, where the position of the switch is determined by the logic levels OEb I3b I2b I1b I0b Za = OEa•(I0a•S1•S0+I1a•S1•S0+ I2a•S1•S0+I3a•S1•S0) Zb = OEb•(I0b•S1•S0+I1b•S1•S0+ I2b•S1•S0+I3b•S1•S0) If the outputs of 3−state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3−state devices whose outputs are tied together are designed so that there is no overlap. S0 S1 I3a Zb NOTE: I2a I1a I0a Za This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram http://onsemi.com 2 OEa MC74AC253, MC74ACT253 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature −65 to +150 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Min Typ Max Unit ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − − − 140 °C −40 25 85 °C V V ns/V tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA 1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. http://onsemi.com 3 ns/V MC74AC253, MC74ACT253 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 VOL Maximum Low Level Output Voltage V V IOUT = −50 μA *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 μA V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 μA VI = VCC, GND IOZ Maximum 3−State Current 5.5 − ±0.5 ±5.0 μA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 μA VIN = VCC or GND IOLD IOHD ICC †Minimum Dynamic Output Current Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. http://onsemi.com 4 MC74AC253, MC74ACT253 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol VCC* (V) Parameter 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Sn to Zn 3.3 5.0 2.0 2.0 − − 15.5 11.0 2.0 1.5 17.5 12.5 ns 3−6 tPHL Propagation Delay Sn to Zn 3.3 5.0 2.5 2.0 − − 16.0 11.5 2.0 1.5 18.0 13.0 ns 3−6 tPLH Propagation Delay In to Zn 3.3 5.0 1.5 1.5 − − 14.5 10.0 1.5 1.5 17.0 11.5 ns 3−5 tPHL Propagation Delay In to Zn 3.3 5.0 2.0 1.5 − − 13.0 9.5 1.5 1.5 15.0 11.0 ns 3−5 tPZH Output Enable Time 3.3 5.0 1.5 1.5 − − 8.0 6.0 1.0 1.0 8.5 6.5 ns 3−7 tPZL Output Enable Time 3.3 5.0 1.5 1.5 − − 8.0 6.0 1.0 1.0 9.0 7.0 ns 3−8 tPHZ Output Disable Time 3.3 5.0 2.0 2.0 − − 9.5 8.0 1.5 1.5 10.0 8.5 ns 3−7 tPLZ Output Disable Time 3.3 5.0 1.5 1.5 − − 8.0 7.0 1.0 1.0 9.0 7.5 ns 3−8 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. http://onsemi.com 5 MC74AC253, MC74ACT253 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = −40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA VOL Maximum Low Level Output Voltage V V IOUT = −50 μA *VIN = VIL or VIH −24 mA IOH −24 mA IOUT = 50 μA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 μA VI = VCC, GND ΔICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOZ Maximum 3−State Current 5.5 − ±0.5 ±5.0 μA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 μA VIN = VCC or GND IOLD IOHD ICC †Minimum Dynamic Output Current Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. http://onsemi.com 6 MC74AC253, MC74ACT253 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Sn to Zn 5.0 2.0 − 11.5 2.0 13.0 ns 3−6 tPHL Propagation Delay Sn to Zn 5.0 3.0 − 13.0 2.5 14.5 ns 3−6 tPLH Propagation Delay In to Zn 5.0 2.5 − 10.0 2.0 11.0 ns 3−5 tPHL Propagation Delay In to Zn 5.0 3.5 − 11.0 3.0 12.5 ns 3−5 tPZH Output Enable Time 5.0 2.0 − 7.5 1.5 8.5 ns 3−7 tPZL Output Enable Time 5.0 2.0 − 8.0 1.5 9.0 ns 3−8 tPHZ Output Disable Time 5.0 3.0 − 9.5 2.5 10.0 ns 3−7 tPLZ Output Disable Time 5.0 2.5 − 7.5 2.0 8.5 ns 3−8 * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 50 pF VCC = 5.0 V MARKING DIAGRAMS DIP−16 SO−16 MC74AC157N AWLYYWW AC157 AWLYWW MC74ACT157N AWLYYWW ACT157 AWLYWW A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 7 TSSOP−16 EIAJ−16 AC 157 ALYW 74AC157 ALYW ACT 157 ALYW 74ACT157 ALYW MC74AC253, MC74ACT253 PACKAGE DIMENSIONS PDIP−16 N SUFFIX 16 PIN PLASTIC DIP PACKAGE CASE 648−08 ISSUE R −A− 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C DIM A B C D F G H J K L M S L S SEATING PLANE −T− K H G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SO−16 D SUFFIX 16 PIN PLASTIC SOIC PACKAGE CASE 751B−05 ISSUE J −A− 16 9 1 8 −B− P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 8 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74AC253, MC74ACT253 PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX 16 PIN PLASTIC TSSOP PACKAGE CASE948F−01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K K1 2X L/2 16 9 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ J1 S 0.25 (0.010) A −V− M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D DETAIL E H G EIAJ−16 M SUFFIX 16 PIN PLASTIC EIAJ PACKAGE CASE966−01 ISSUE O 16 LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) http://onsemi.com 9 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.031 MC74AC253, MC74ACT253 Notes http://onsemi.com 10 MC74AC253, MC74ACT253 Notes ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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