ONSEMI MC74LCX257

MC74LCX257
Low−Voltage CMOS Quad
2−Input Multiplexer
With 5.0 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The MC74LCX257 is a high performance, quad 2−input
multiplexer with 3−state outputs operating from a 2.3 to 3.6 V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX257 inputs to be safely driven from 5.0 V devices.
Four bits of data from two sources can be selected using the Select
input. The four outputs present the selected data in the true
(non−inverted) form. The outputs may be switched to a high
impedance state by placing a logic HIGH on the Output Enable (OE)
input. Current drive capability is 24 mA at the outputs.
Features
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
16
1
1
16
16
Designed for 2.3 to 3.6 V VCC Operation
5.0 V Tolerant − Interface Capability with 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
Pb−Free Packages are Available*
LCX257
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
LCX
257
ALYW
1
16
SOEIAJ−16
M SUFFIX
CASE 966
16
74LCX257
ALYW
1
1
A
L, WL
Y
W, WW
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 3
1
Publication Order Number:
MC74LCX257/D
MC74LCX257
VCC
OE
I0c
I1c
Zc
I0d
I1d
Zd
16
15
14
13
12
11
10
9
I0a
I1a
I0b
I1b
1
S
2
I0a
3
I1a
4
5
Za
I0b
6
I1b
7
8
Zb
GND
I0c
I1c
Figure 1. Pinout: 16−Lead Plastic Package
(Top View)
I0d
I1d
OE
2
4
5
7
14
12
11
9
10
15
PIN NAMES
Pins
Function
Source 0 Data Inputs
l1n
Source 1 Data Inputs
OE
Output Enable Input
S
Select Input
Zn
Outputs
TRUTH TABLE
Inputs
H
L
X
Z
Outputs
OE
S
l0n
l1n
Zn
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
=
=
=
=
High Voltage Level
Low Voltage Level
High or Low Voltage Level and Transitions are Acceptable
High Impedance State
For ICC reasons, DO NOT FLOAT Inputs
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2
Zc
13
Figure 2. Logic Diagram
l0n
Zb
6
1
S
Za
3
Zd
MC74LCX257
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VI
Value
Condition
Unit
−0.5 to +7.0
V
DC Input Voltage
−0.5 ≤ VI ≤ +7.0
V
VO
DC Output Voltage
−0.5 ≤ VI ≤ +7.0
Output in 3−State
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State (Note 1)
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
V
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating
Data Retention Only
Min
Type
Max
Unit
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
(HIGH or LOW State)
(3−State)
IOH
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
−24
−12
−8
mA
IOL
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
+24
+12
+8
mA
TA
Operating Free−Air Temperature
−40
+85
°C
t/V
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V,
VCC = 3.0 V
0
10
ns/V
ORDERING INFORMATION
Package
Shipping†
MC74LCX257DR2
SOIC−16
2500 Tape & Reel
MC74LCX257DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LCX257DT
TSSOP−16*
96 Units / Rail
MC74LCX257DTR2
TSSOP−16*
2500 Tape & Reel
MC74LCX257M
SOEIAJ−16
48 Units / Rail
MC74LCX257MEL
SOEIAJ−16
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74LCX257
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
VIH
VIL
VOH
VOL
Characteristic
HIGH Level Input Voltage (Note 2)
LOW Level Input Voltage (Note 2)
HIGH Level Output Voltage
LOW Level Output Voltage
Condition
Min
2.3 V ≤ VCC ≤ 2.7 V
1.7
2.7 V ≤ VCC ≤ 3.6 V
2.0
Max
Unit
V
2.3 V ≤ VCC ≤ 2.7 V
0.7
2.7 V ≤ VCC ≤ 3.6 V
0.8
2.3 V ≤ VCC ≤ 3.6 V; IOH = −100 A
VCC − 0.2
VCC = 2.3 V; IOH = −8 mA
1.8
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
V
V
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 A
0.2
VCC = 2.3 V; IOL = 8 mA
0.6
VCC = 2.7 V; IOL = 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
V
II
Input Leakage Current
2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5
A
IOZ
3−State Output Current
2.3 ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 5.5 V;
VI = VIH or VIL
±5
A
IOFF
Power−Off Leakage Current
VCC = 0 V; VI or VO = 5.5 V
10
A
ICC
Quiescent Supply Current
2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC
10
A
2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±10
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
500
ICC
Increase in ICC per Input
A
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 Limits
TA = −40°C to +85°C
Symbol
Parameter
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 2.5 V ± 0.2 V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Waveform
Min
Max
Min
Max
Min
Max
Unit
1
1.5
6.0
1.5
6.5
1.5
7.2
ns
1.5
6.0
1.5
6.5
1.5
7.2
1.5
7.0
1.5
8.5
1.5
9.1
1.5
7.0
1.5
8.5
1.5
9.1
1.5
7.0
1.5
8.5
1.5
9.1
1.5
7.0
1.5
8.5
1.5
9.1
1.5
5.5
1.5
6.0
1.5
6.6
1.5
5.5
1.5
6.0
1.5
6.6
tPLH
Propagation Delay
tPHL
In to Zn
tPLH
Propagation Delay
tPHL
S to Zn
tPZH
Output Enable Time to
tPZL
High and Low Level
tPHZ
Output Disable Time From
tPLZ
High and Low Level
tOSHL
Output−to−Output Skew
1.0
tOSLH
(Note 3)
1.0
1, 2
3
3
ns
ns
ns
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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4
MC74LCX257
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
V
VOLV
Dynamic LOW Valley Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
CPD
Power Dissipation Capacitance
Condition
Typical
Unit
VCC = 3.3 V, VI = 0 V or VCC
7
pF
VCC = 3.3 V, VI = 0 V or VCC
8
pF
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
25
pF
VCC
VCC
In, S Vmi
Vmi
Vmi
S
Vmi
0V
tPLH
0V
tPHL
tPLH
tPHL
VOH
Zn
Vmo
VOH
Vmo
Vmo
Zn
VOL
VOL
WAVEFORM 1 − NON−INVERTING PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1.0 MHz; tW = 500 ns
WAVEFORM 2 − INVERTING PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1.0 MHz; tW = 500 ns
VCC
Vmi
Vmi
OE
0V
tPZH
tPHZ
VCC
VOH − 0.3
V
Vmo
Zn
≈0V
tPZL
tPLZ
≈ 3.0V
Vmo
Zn
VOL + 0.3 V
GND
WAVEFORM 3 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1.0 MHz; tW = 500 ns
Vcc
Symbol
Vmo
3.3 V + 0.3 V
2.7 V
2.5 V + 0.2 V
Vmi
1.5 V
1.5 V
Vcc/2
Vmo
1.5 V
1.5 V
Vcc/2
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 0.15 V
Figure 3. AC Waveforms
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5
MC74LCX257
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
S
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
S
K
ÉÉ
ÇÇ
ÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
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6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC74LCX257
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
16
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
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7
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.031
MC74LCX257
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
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8
For additional information, please contact your
local Sales Representative.
MC74LCX257/D