NCP5603 High Efficiency Charge Pump Converter The NCP5603 is an integrated circuit dedicated to the medium power White LED applications. The power conversion is achieved by means of a charge pump structure, using two external ceramic capacitors, making the system extremely tiny. The device supplies a constant voltage to the load from a low battery voltage source. It is particularly suited for the High Efficiency LED used in low cost, low power applications, with high extended battery life. http://onsemi.com MARKING DIAGRAM Features • • • • • • • • • • Wide Battery Supply Voltage Range: 2.7 < VCC < 5.5 V Automatic Operating Mode 1X, 1.5X and 2X Improves Efficiency Dimmable Output Current Up to 350 mA Output Pulsed Current Selectable Output Voltage High Efficiency Up To 90% Supports 2.5 kV ESD, Human Body Model Supports 200 V Machine Model ESD Low 40 mA Short Circuit Current Pb−Free Package is Available 5603 ALYW G DFN10 MN SUFFIX CASE 485C 5603 A L Y W G Applications = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS • High Power LED • Back Light Display • High Power Flash Vout 1 10 C2P C1P 2 9 C1N Vbat 3 8 GND Fsel 4 7 C2N Vsel 5 6 EN (Top View) ORDERING INFORMATION Device NCP5603MNR2 Package Shipping† QFN10, 3x3 3000/ Tape & Reel NCP5603MNR2G QFN10, 3x3 3000/ Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 November, 2005 − Rev. 1 1 Publication Order Number: NCP5603/D NCP5603 Vbat U1 Figure 1. Typical Application http://onsemi.com 2 LWT67C 10 W D4 LWT67C GND R4 NCP5603 10 W 6 EN/PWM 4 Fsel 5 Vsel 8 GND GND 1 mF/16 V 1 D3 Vout C1N GND R3 9 10 LWT67C C2P LWT67C PWM FSEL VSEL C1P R1 C1 1 mF/16 V C4 D2 2 7 10 W C2N C2 1 mF/16 V Vbat 4.7 mF/16 V D1 GND R2 3 10 W C3 NCP5603 Vbat Vbat 3 Fsel 4 LOGIC AND ANALOG CONTROL Vbat POWER SWITCHES Thermal Shutdown 10 C2P LEVEL SHIFTER AND MOSFET DRIVE Vbat 7 C2N 9 C1N 2 C1P Vout 1 Vout GND Vbat − Vsel 5 + GND EN 6 GND BANDGAP 8 GND Figure 2. Block Diagram http://onsemi.com 3 NCP5603 PIN FUNCTION DESCRIPTION Pin Symbol Type Description 1 Vout OUTPUT, PWR This pin supplies the regulated voltage to the external LED. Since high current transients are present in this pin, care must be observed to avoid voltage spikes in the system. Good high frequency layout technique must be observed. 2 C1N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P, pin 9. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 3 Vbat POWER This pin shall be connected to the power source, and must be decoupled to Ground by a low ESR capacitor (2.2 mF/6.3 V ceramic or better (see Note 1)). 4 Fsel INPUT, Digital This pin is used to program the operating frequency: Fsel = 0 → Fop = 262 kHz Fsel = 1 → Fop = 650 kHz 5 Vsel INPUT, Digital This pin setup the output voltage: Vsel = 0 → Vout = 4.5 V Vsel = 1 → Vout = 5.0 V 6 EN/PWM INPUT, Digital This pin controls the activity of the NCP5603 chip: EN/PWM = Low → the chip is deactivated, the load is disconnected EN/PWM = High → the chip is activated and the load is connected to the regulated output current. The NCP5603 can operate either in a continuous mode (EN/PWM = High), or can be controlled by a PWM pulse applied to EN/PWM to dim the output light. When EN/PWM is Low, the external load is disconnected from the converter, providing a very low standby current. The pull down built−in resistance makes sure the chip is deactivated even if the EN/PWM pin is disconnected (see Note 2). 7 C2N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P, pin 10. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 8 GND GROUND This pin combines the Signal ground and the Power ground and must be connected to the system ground. Using good quality ground plane is mandatory to avoid spikes on the logic signal lines. 9 C1P POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N, pin 2. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 10 C2P POWER One side of the external charge pump capacitor is connected to this pin, associated with C2N, pin 7. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 1. Using ceramic 16 V working voltage capacitors is recommended to compensate the DC bias effect encountered with such type of capacitors. 2. Any external impedance connected to pin 6 shall be 10 kW or higher. http://onsemi.com 4 NCP5603 MAXIMUM RATINGS Symbol Value Unit Power Supply Voltage Rating Vbat 7.0 V Power Supply Current Ibat 800 mA Digital Input Pins Vin −0.5 V < Vbat < Vbat +0.5 V < 6.0 V V Digital Input Pins Iin "5.0 mA Output Voltage Vout 5.5 V ESD Capability (Note 3) Human Body Model Machine Model VESD 2.5 200 kV V PDS RqJA 580 68.5 mW °C/W Operating Ambient Temperature Range TA −40 to +85 °C Operating Junction Temperature Range TJ −40 to +125 °C TJmax +150 °C Tstg −65 to +150 °C QFN10, 3x3 Package Power Dissipation @ Tamb = +85°C Thermal Resistance, Junction−to−Air (RqJA) Maximum Junction Temperature Storage Temperature Range Latchup Current Maximum Rating 100 mA per JEDEC standard, JESD78 Moisture Sensitivity Level (MSL) 1 per IPC/JEDEC standard, J−STD−020A Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.5 kV per JEDEC Standard: JESD22−A114 Machine Model (MM) "200 V per JEDEC Standard: JESD22−A115. 4. The maximum package power dissipation limit must not be exceeded. http://onsemi.com 5 NCP5603 ELECTRICAL CHARACTERISTICS @ 2.85 V < Vbat < 5.5 V (−40°C to +85°C ambient temperature, unless otherwise noted). Characteristic Pin Symbol Min Typ Max Unit Power Supply 3 Vbat 2.85 − 5.5 V Quiescent Current @ Vbat = 3.7 V, Iout = 0 mA @ Pulsed Clock Fop = 262 kHz @ Pulsed Clock Fop = 650 kHz @ Continuous Clock Fop = 262 kHz @ Continuous Clock Fop = 650 kHz 3 Iqsc − − − − − − 1.0 2.1 0.8 1.2 − − Shutdown Current @ Iout = 0 mA, EN/PWM = L @ 2.85 < Vbat < 4.2 V @ Vbat = 5.5 V 3 − − − − 2.5 4.0 Output Voltage Regulation @ Vsel = 1, 2.85 V < Vbat < 4.5 V @ Vsel = 0, 2.85 V < Vbat < 4.5 V 3 4.75 4.275 5.0 4.5 5.25 4.725 Continuous DC Load Current (Note 7) Cin = 1.0 mF, CFLY = 1.0 mF, Cout = 1.0 mF @ Vsel = 1, 3.2 V < Vbat < 4.5 V @ Vsel = 0, 3.2 V < Vbat < 5.5 V @ Vsel = 1, 2.85 V < Vbat < 4.5 V @ Vsel = 0, 2.85 V < Vbat < 5.5 V 3 Pulsed Output Current Cin = 10 mF, CFLY = 1.0 mF, Cout = 10 mF, Vbat = 3.6 V Pwidth = 500 ms, −40°C < TA < +65°C 3 IFLH Output Continuous Short Circuit Current, Vout = 0 V 3 Isch mA mA Istdb Vout V Iout mA − − − − Operating Frequency (Note 5) @ Fsel = 0, 2.85 V < Vbat < 4.5 V @ Fsel = 1, 2.85 V < Vbat < 4.5 V − − − − 160 200 80 120 mA − 350 − − 40 100 210 500 262 650 320 1000 Fop Output Voltage Ripple (Note 6) Fop = 262 kHz, Iout = 60 mA (Note 7) @ Cout = 1.0 mF @ Cout = 4.7 mF 3 mA kHz VPP mV − − 150 25 − 60 Digital Input High Level 4, 5, 6 VIH 1.3 − − V Digital Input Low level 4, 5, 6 VIL − − 0.4 V − − 75 84 − − − − 160 20 − − Output Power Efficiency @ Vbat = 3.3 V, Vout = 5.0 V, Iout = 60 mA, Fop = 262 kHz @ Vbat = 3.9 V, Vout = 5.0 V, Iout = 160 mA, Fop = 650 kHz % Ph Thermal Shut Down Protection Hysteresis THSD °C 5. Temperature range guaranteed by design, not production tested. 6. Smaller footprint associated to lower working voltages (10 V or 6.3 V, size 0805 or 0602) can be used, but care must be observed to prevent DC bias effect on the capacitance final value. See capacitor manufacturer data sheets. 7. Ceramic X7R, ESR < 100 mW, SMD type capacitors are mandatory to achieve the Iout specifications. Depending upon the PCB layout, it might be necessary to use two 2.2 mF/6.3 V/ceramic capacitors in parallel, yielding an improved Vout noise over the temperature range. On the other hand, care must be observed to take into account the DC bias impact on the capacitance value. See ceramic capacitor manufacturer data sheets. 8. Digital inputs undershoot < − 0.30 V to ground, Digital inputs overshoot < 0.30 V to Vbat. http://onsemi.com 6 NCP5603 TYPICAL CHARACTERISTICS 100 100 IOUT = 120 mA IOUT = 120 mA 90 EFFICIENCY (%) EFFICIENCY (%) 90 80 70 60 80 70 60 50 2.5 3.0 3.5 4.0 4.5 5.0 50 2.5 5.5 3.0 3.5 4.0 4.5 5.0 Vin (V) Vbat (V) Figure 3. Operating Modes Transitions and Output Power Efficiency @ Vout = 4.5 V/262 kHz Figure 4. Operating Modes Transitions and Output Power Efficiency @ Vout = 4.5 V/650 kHz 100 IOUT = 160 mA −40°C EFFICIENCY (%) 90 25°C 85°C 80 70 60 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vbat (V) Figure 5. Operating Modes Transitions and Output Power Efficiency @ Vout = 5.0 V/650 kHz Figure 6. Typical Output Voltage Ripple 4.8 IOUT = 200 mA 4.7 4.6 Vout (V) 5.5 25°C 4.5 4.4 −40°C 4.3 85°C 4.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vbat (V) Test conditions: Vbat = 3.6 V, Vout = 5 V, Load = 4*LW87S, ILED = 25mA Figure 7. Typical Output Voltage Line Regulation Figure 8. Output Voltage Startup from Scratch http://onsemi.com 7 NCP5603 TYPICAL CHARACTERISTICS Test conditions: Vbat = 3.6 V, Vout = 5 V, Load = 4*LW87S, ILED = 25mA Figure 9. Typical PWM Dimming VCC NCP5603 3 C1 10 mF/10 V GND 2 C2 1 mF/6.3 V EN 6 FSEL 4 VSEL 5 PWR−FLASH GND 9 8 Vbat C2N C1P C1P C1N Vout 7 C2 1 mF/16 V 10 1 C4 10 mF EN/PWM D1 OSRAM: LWW5SG GOLDEN DRAGON Fsel Vsel GND GND R1 1W GND GND Figure 10. Typical High Power Flash Circuit http://onsemi.com 8 NCP5603 500 R=0W 450 400 R=1W Iout (mA) 350 300 R = 2.2 W 250 200 150 Vout = 4.5 V FSEL = 0 Load = OSRAM / LWW5SG PWR SWITCH = MGSF1N03 100 50 0 2.5 3.0 3.5 4.0 4.5 Vbat (V) Figure 11. NCP5603 Output Current Table 1. Ceramic Preferred Capacitors Manufacturer Type/Series Format Value TDK C3216X5R1C475MT 1206 4.7 mF / 16 V TDK C2012X5R1C225MT 0805 2.2 mF / 16 V TDK C2012X5R1C105MT 0805 1.0 mF / 16 V http://onsemi.com 9 NCP5603 TP2 1 GND C3 1.0 mF/16 V ISENSE R9 D4 TP1 82 W LW67C 1 GND R8 D3 Vout 82 W LW67C R7 D2 82 W LW67C R6 D1 82 W LW67C 1 GND 8 Vsel Fsel 5 4 6 EN/PWM Vout C1N 9 C1P 2 Vbat 3 U1 NCP5603 C2N C1P 7 10 C2 1 mF/16 V C1 GND S3 Vsel R4 Vsel S2 Fsel 10 k GND VCC 1 mF/16 V VCC GND R5 Fsel C7 100 nF 3 4 S1 R2 3 100 k 6 NL27WZ14 U2A 1 GND R1 NL27WZ14 U2B 10 Q 15 C 12 A 11 B 13 CLR RC D5 PWM Z3 GND GROUND Figure 12. Evaluation Board Schematic Diagram http://onsemi.com GND R11 1.5 k GND 33 nF 4 9 10 GND VCC PK1 2 x 1.5 V 100 nF GND GND 4 mm J2 VCC 4 mm + + J1 2 − + GND 1 GND 100 nF C5 C8 VCC S4 POWER 14 5 3 C6 Q U3B MC14538B 7 Q Q C A B CLR R10 10 k CNT/PWM 10 k VCC Adjust PWM 4 R3 1 P1 200 kA RC GND 2 C4 4.7 mF/16 V U3A MC14538B 6 10 k GND NCP5603 Figure 13. Evaluation Board: Silk View (Top View) http://onsemi.com 11 NCP5603 PACKAGE DIMENSIONS DFN10 MN SUFFIX CASE 485C−01 ISSUE A D PIN 1 REFERENCE A B ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ EDGE OF PACKAGE L1 E DETAIL A Bottom View (Optional) 0.15 C 2X TOP VIEW 0.15 C 2X DIM A A1 A3 b D D2 E E2 e K L L1 (A3) DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. A 10X 0.08 C SIDE VIEW D2 10X SEATING PLANE A1 C DETAIL A MOLD CMPD e L 1 5 A1 A3 DETAIL B Side View (Optional) E2 10X ÉÉ ÉÉ EXPOSED Cu MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 K SOLDERING FOOTPRINT* 10 10X b 0.10 C A B 0.05 C 6 2.6016 BOTTOM VIEW NOTE 3 2.1746 1.8508 3.3048 10X 0.5651 10X 0.3008 0.5000 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 NCP5603 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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