NBSG11 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com Description The NBSG11 is a 1−to−2 differential fanout buffer, optimized for low skew and Ultra−Low JITTER. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. Features • • • • • • • • • • Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V RSECL Output Level (400 mV Peak−to−Peak Output), Differential Output Only 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices Pb−Free Packages are Available MARKING DIAGRAMS* SG 11 ALYW FCBGA−16 BA SUFFIX CASE 489 ÇÇ ÇÇ 16 1 QFN−16 MN SUFFIX CASE 485G A L Y W G SG11 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 8 1 Publication Order Number: NBSG11/D NBSG11 1 A VTCLK B 2 3 4 NC NC Q1 VEE CLK VCC VTCLK 1 CLK 2 VEE NC NC VCC 16 15 14 13 Exposed Pad (EP) 12 Q0 11 Q0 Q1 NBSG11 CLK VEE VCC Q0 VTCLK NC NC Q0 C D CLK 3 10 Q1 VTCLK 4 9 Q1 Figure 1. BGA−16 Pinout (Top View) 5 6 7 8 VEE NC NC VCC Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA QFN Name I/O D1 1 VTCLK − C1 2 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC. B1 3 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Internal 75 kW to VEE. Description Internal 50 W Termination Pin. See Table 2. A1 4 VTCLK − Internal 50 W Termination Pin. See Table 2. B2,C2 5,16 VEE − Negative Supply Voltage A2,A3,D2, D3 6,7,14,15 NC − No Connect B3,C3 8,13 VCC − Positive Supply Voltage A4 9 Q1 RSECL Output Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. B4 10 Q1 RSECL Output Noninverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. C4 11 Q0 RSECL Output Inverted Differential output 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V. D4 12 Q0 RSECL Output Noninverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC − 2 V. N/A − EP − Exposed Pad (Note 2) 1. The NC pins are electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. 3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. http://onsemi.com 2 NBSG11 VCC VTCLK Q1 36.5 KW 50 W Q1 CLK CLK 50 W 75 KW Q0 75 KW Q0 VTCLK VEE Figure 3. Logic Diagram Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK and VTCLK to VCC LVDS Connect VTCLK and VTCLK together AC−COUPLED Bias VTCLK and VTCLK Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An external voltage should be be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (CLK, CLK) 75 kW Internal Input Pullup Resistor (CLK) ESD Protection 36.5 kW Human Body Model Machine Model Moisture Sensitivity (Note 4) FCBGA−16 QFN−16 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 100 V Pb Pkg Pb−Free Pkg Level 3 Level 1 N/A Level 1 UL 94 V−0 @ 0.125 in 125 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NBSG11 Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol Positive Power Supply Parameter VEE = 0 V Condition 1 3.6 V VEE Negative Power Supply VCC = 0 V −3.6 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 −3.6 V V VINPP Differential Input Voltage 2.8 |VCC − VEE| V V Iout Output Current Continuous Surge 25 50 mA mA TA Operating Temperature Range 16 FCBGA 16 QFN −40 to +70 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 16 FCBGA 16 FCBGA 16 QFN 16 QFN 108 86 41.6 35.2 °C/W °C/W °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 5) 2S2P (Note 6) 16 FCBGA 16 QFN 5.0 4.0 °C/W °C/W Tsol Wave Solder 225 225 °C |D − D| VCC − VEE w VCC − VEE < Condition 2 VI ≤ VCC VI ≥ VEE 2.8 V 2.8 V Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power). 6. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG11 Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 7) −40°C 25°C 70°C(BGA)/85°C(QFN)** Min Typ Max Min Typ Max Min Typ Max Unit 45 60 75 45 60 75 45 60 75 mA Output HIGH Voltage (Note 8) 1450 1530 1575 1525 1565 1600 1550 1590 1625 mV VOUTPP Output Amplitude Voltage 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single−Ended) (Note 10) VCC− 1435 mV VCC− 1000 mV* VCC VCC− 1435 mV VCC− 1000 mV* VCC VCC− 1435 mV VCC− 1000 mV* VCC V VIL Input LOW Voltage (Single−Ended) (Note 11) VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 1.2 2.5 1.2 2.5 1.2 2.5 V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W IIH Input HIGH Current (@ VIH, VIHMAX) 80 150 80 150 80 150 mA IIL Input LOW Current (@ VIL, VILMIN) 25 100 25 100 25 100 mA Symbol Characteristic IEE Negative Power Supply Current VOH NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. **The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum temperature specification of 85°C. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. 8. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10. VIH cannot exceed VCC. 11. VIL always ≥ VEE. http://onsemi.com 5 NBSG11 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 12) −40°C Symbol Characteristic 25°C 70°C(BGA)/85°C(QFN)** Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 45 60 75 45 60 75 45 60 75 mA VOH Output HIGH Voltage (Note 13) 2250 2330 2375 2325 2365 2400 2350 2390 2425 mV VOUTPP Output Amplitude Voltage 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single−Ended) (Note 15) VCC− 1435 mV VCC− 1000 mV* VCC VCC− 1435 mV VCC− 1000 mV* VCC VCC− 1435 mV VCC− 1000 mV* VCC V VIL Input LOW Voltage (Single−Ended) (Note 16) VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV V VIHCMR Input HIGH Voltage Common Mode Range (Note 14) (Differential Configuration) 1.2 3.3 1.2 3.3 1.2 3.3 V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W IIH Input HIGH Current (@ VIH, VIHMAX) 80 150 80 150 80 150 mA IIL Input LOW Current (@ VIL, VILMIN) 25 100 25 100 25 100 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. 13. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 15. VIH cannot exceed VCC. 16. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum temperature specification of 85°C. http://onsemi.com 6 NBSG11 Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 17) −40°C 25°C 70°C(BGA)/85°C(QFN)** Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 45 60 75 45 60 75 45 60 75 mA VOH Output HIGH Voltage (Note 18) −1050 −970 −925 −975 −935 −900 −950 −910 −875 mV VOUTPP Output Amplitude Voltage 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single−Ended) (Note 20) VCC− 1435 mV VCC− 1000 mV* VCC VCC− 1435 mV VCC− 1000 mV* VCC VCC− 1435 mV VCC− 1000 mV* VCC V VIL Input LOW Voltage (Single−Ended) (Note 21) VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV VIH− 2.5 V VCC− 1400 mV* VIH− 150 mV V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) 0.0 V RTIN Internal Input Termination Resistor 50 55 W IIH IIL Symbol Characteristic VEE+1.2 45 0.0 50 55 Input HIGH Current (@ VIH, VIHMAX) 80 Input LOW Current (@ VIL, VILMIN) 25 VEE+1.2 45 0.0 VEE+1.2 50 55 45 150 80 150 80 150 mA 100 25 100 25 100 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 20. VIH cannot exceed VCC. 21. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum temperature specification of 85°C. http://onsemi.com 7 NBSG11 Table 8. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 22) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 23) Within−Device Skew (Note 24) Device−to−Device Skew (Note 25) tJITTER RMS Random Clock Jitter Min Typ 10.709 12 90 125 160 3 6 25 0.2 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 26) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz Max 70°C Min Typ Max Min Typ 10.709 12 90 125 160 15 15 50 3 6 25 1 0.2 Max 10.709 12 90 125 160 ps 15 15 50 3 6 25 15 15 50 ps 1 0.2 1 Unit GHz ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C TBD 75 Q, Q 20 30 TBD 2600 75 55 20 30 TBD 2600 75 55 20 30 2600 mV 55 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 22. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. For minimum fmax value of 10.709 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P−P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% − 80%). 23. See Figure 5. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform. 24. Within−Device skew is defined as identical transitions on similar paths through a device. 25. Device−to−device skew for identical transitions at identical VCC levels. 26. VINPP (MAX) cannot exceed VCC − VEE. http://onsemi.com 8 NBSG11 Table 9. AC CHARACTERISTICS for QFN−16 VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 27) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 28) Within−Device Skew (Note 29) Device−to−Device Skew (Note 30) tJITTER RMS Random Clock Jitter 25°C Min Typ Max 10.5 12 90 125 160 3 6 25 0.2 85°C Min Typ Max Min Typ 10.5 12 90 125 160 15 15 50 3 6 25 1 0.2 Max 10.5 12 90 125 160 ps 15 15 50 3 6 25 15 15 50 ps 1 0.2 1 Unit GHz ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 31) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz TBD 75 Q, Q 15 30 TBD 2600 75 55 20 30 TBD 2600 75 55 20 30 2600 mV 55 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 27. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. For minimum fmax value of 10.5 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P−P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% − 80%). 28. See Figure 5. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform. 29. Within−Device skew is defined as identical transitions on similar paths through a device. 30. Device−to−device skew for identical transitions at identical VCC levels. 31. VINPP (MAX) cannot exceed VCC − VEE. 600 8.5 500 7.5 OUTPUT AMP. ÑÑ ÓÓÓ ÑÑÑÑÑÑ ÔÔ ÖÖÖ ÑÑ ÑÑÑÑÑÑÑÑ ÓÓÓÔÔÖÖÖÑÑÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÓÓ ÔÔÔ ÑÑÓÓÓÔÔÖÖÖÑÑÓÓÔÔÔÒÒ ÑÑÓÓÓÔÔÖÖÖÑÑÓÓÔÔÔÒÒÕÕŠŠŠ ÑÑÓÓÓÔÔÖÖÖÑÑÑÑÑ ÑÑÓÓÔÔÔÒÒÕÕŠŠŠÚÚ ÑÑÓÓÓÔÔÖÖÖÑÑÓÓÔÔÔÒÒÕÕŠŠŠÚÚÒÒÒ ÑÑÓÓÓÔÔÖÖÖÑÑÓÓÔÔÔÒÒÕÕŠŠŠÚÚÒÒÒ 6.5 400 5.5 OUTPUT P−P SPEC 300 4.5 3.5 200 2.5 100 1.5 RMS JITTER 0.5 0 1 2 3 4 5 6 7 8 9 INPUT FREQUENCY (GHz) 10 11 12 Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 9 −0.5 JITTERout ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 9.5 NBSG11 CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPLH tPHL Figure 5. AC Reference Measurement Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NBSG11BA FCBGA−16 100 Units / Tray (Contact Sales Representative) NBSG11BAR2 FCBGA−16 100 / Tape & Reel QFN−16 123 Units / Rail NBSG11MNG QFN−16 (Pb−Free) 123 Units / Rail NBSG11MNR2 QFN−16 3000 / Tape & Reel QFN−16 (Pb−Free) 3000 / Tape & Reel Device NBSG11MN NBSG11MNR2G Board Description NBSG11BAEVB NBSG11BA Evaluation Board †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NBSG11 PACKAGE DIMENSIONS FCBGA−16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489−01 ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA −X− D M −Y− K E M 0.20 3X e 4 3 2 FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA 1 A 3 B b 16 X C D S VIEW M−M 0.15 M Z X Y 0.08 M Z 5 0.15 Z A A2 A1 16 X 4 −Z− 0.10 Z DETAIL K ROTATED 90 _ CLOCKWISE http://onsemi.com 11 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG11 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D PIN 1 LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B ÇÇ ÇÇ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 C SOLDERING FOOTPRINT* D2 16X 0.575 0.022 e L 5 NOTE 5 EXPOSED PAD 8 4 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 3.25 0.128 0.30 0.012 EXPOSED PAD 9 E2 16X K 12 1 16 16X 1.50 0.059 3.25 0.128 13 b 0.10 C A B 0.05 C e BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and solder details, please download the ON Semiconductor Soldering a Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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