MC100LVEL56 3.3VECL Dual Differential 2:1 Multiplexer Description The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 forcing the Q output LOW. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • • • • • • • • http://onsemi.com SO−20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 580 ps Typical Propagation Delays Separate and Common Select The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL Q Output will Default LOW with Inputs Open or at VEE Pb−Free Packages are Available* 100LVEL56 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 11 1 Publication Order Number: MC100LVEL56/D MC100LVEL56 Q0 Q0 SEL0 20 19 18 17 1 1 D0a 2 D0a COM_SEL VCC Table 1. PIN DESCRIPTION D0a* − D1a* ECL Input Data a SEL1 VCC Q1 Q1 VEE D0a* − D1a* ECL Input Data a Invert 16 15 14 13 12 11 D0b* − D1b* ECL Input Data b D0b* − D1b* ECL Input Data b Invert SEL0* − SEL1* ECL Indiv. Select Input COM_SEL* ECL Common Select Input VBB0, VBB1 Output Reference Voltage Q0 − Q1 ECL True Outputs Q0 − Q1 ECL Inverted Outputs VCC Positive Supply VEE Negative Supply PIN 0 3 1 4 VBBO D0b 5 D0b 6 7 D1a D1a 0 8 VBB1 9 D1b FUNCTION * Pins will default LOW when left open. 10 D1b Table 2. TRUTH TABLE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. SEL0 SEL1 COM_SEL Q0, Q0 Q1, Q1 X L L H H X L H H L H L L L L a b b a a a b a a b Figure 1. 20−Lead Package (Top View) and Logic Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 KW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index > 2 kV > 200 V > 4 kV Level 1 UL 94 V−0 @ 0.125 in 28 to 34 Transistor Count 147 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100LVEL56 Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SO−20 WB SO−20 WB 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SO−20 WB 30 to 35 °C/W Tsol Wave Solder t2 to 3 sec @ 248°C t2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 VI VCC VI VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 20 24 20 24 20 24 mA VOH Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 4) Vpp < 500 mV Vpp y 500 mV 1.3 1.5 2.9 2.9 1.2 1.4 2.9 2.9 1.2 1.4 2.9 2.9 V V 150 mA IIH Input HIGH Current IIL Input LOW Current 150 Dn Dn 0.5 −600 150 0.5 −600 0.5 −600 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP(min) and 1 V. http://onsemi.com 3 MC100LVEL56 Table 6. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 5) −40°C Symbol Min Characteristic 25°C Typ Max 20 24 Min 85°C Typ Max 20 24 Min Typ Max Unit 20 24 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 6) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 7) Vpp < 500 mV Vpp y 500 mV −2.0 −0.4 −2.1 −0.4 −2.1 −0.4 −1.8 −0.4 −1.9 −0.4 −1.9 −0.4 V V IIH Input HIGH Current IIL Input LOW Current 150 Dn Dn 0.5 −600 150 0.5 −600 150 0.5 −600 mA mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 7. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 8) −40°C Symbol Min Characteristic Typ 25°C Max Min Typ 85°C Max Min Typ Max 1 Unit fmax Maximum Toggle Frequency (See Figure 2, Fmax/JITTER) tPLH tPHL Propagation Delay to Output tSKEW Within−Device Skew (Note 9) tSKEW Duty Cycle Skew (Note 10) tJITTER Random Clock Jitter (RMS) VPP Input Swing (Note 11) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% − 80%) 200 540 200 540 200 540 ps D SEL COMSEL 400 430 430 600 730 730 40 420 440 440 80 GHz 440 620 740 740 40 80 100 440 450 450 640 750 750 40 100 ps 80 ps 100 ps 1.5 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. VEE can vary ±0.3 V. 9. Within-device skew is defined as identical transitions on similar paths through a device. 10. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 11. VPP(min) is minimum input swing for which AC parameters are guaranteed. http://onsemi.com 4 1000 10 900 9 800 8 700 7 600 6 500 5 400 4 300 3 200 0 2 (JITTER) 100 0 250 JITTER (ps RMS) OUTPUT VOLTAGE (mV amplitude) MC100LVEL56 1 500 750 1000 1250 1500 1750 2000 FREQUENCY (MHz) Figure 2. Fmax/Jitter Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 5 MC100LVEL56 ORDERING INFORMATION Package Shipping † MC100LVEL56DW SO−20 WB 38 Units / Rail MC100LVEL56DWG SO−20 WB (Pb−Free) 38 Units / Rail MC100LVEL56DWR2 SO−20 WB 1000 / Tape & Reel MC100LVEL56DWR2G SO−20 WB (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 6 MC100LVEL56 PACKAGE DIMENSIONS SO−20 WB DW SUFFIX CASE 751D−05 ISSUE G A 20 q X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100LVEL56/D