ONSEMI MC14016BCPG

MC14016B
Quad Analog Switch/
Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linearized Transfer Characteristics
Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical
Pin−for−Pin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
For Lower RON, Use The HC4016 High−Speed CMOS Device or
The MC14066B
This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.
Pb−Free Packages are Available
14
PDIP−14
P SUFFIX
CASE 646
1
14
SOIC−14
D SUFFIX
CASE 751A
VDD
Parameter
DC Supply Voltage Range
Value
Unit
−0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5
V
Iin
Input Current (DC or Transient)
per Control Pin
± 10
mA
ISW
Switch Through Current
± 25
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
14016BG
AWLYWW
1
14
SOEIAJ−14
F SUFFIX
CASE 965
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
MC14016BCP
AWLYYWWG
MC14016B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1
Publication Order Number:
MC14016B/D
MC14016B
PIN ASSIGNMENT
BLOCK DIAGRAM
IN 1
1
14
VDD
OUT 1
2
13
CONTROL 1
OUT 2
3
12
CONTROL 4
IN 2
4
11
IN 4
CONTROL 2
5
10
OUT 4
CONTROL 3
6
9
OUT 3
VSS
7
8
IN 3
CONTROL 1
IN 1
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
13
2
OUT 1
1
5
3
OUT 2
4
6
9
OUT 3
8
12
10
11
OUT 4
VDD = PIN 14
VSS = PIN 7
OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS
VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD
IN
Control
Switch
0 = VSS
Off
1 = VDD
On
ORDERING INFORMATION
Device
Package
MC14016BCP
PDIP−14
MC14016BCPG
PDIP−14
(Pb−Free)
MC14016BD
SOIC−14
MC14016BDG
SOIC−14
(Pb−Free)
MC14016BDR2
SOIC−14
MC14016BDR2G
SOIC−14
(Pb−Free)
MC14016BFEL
SOEIAJ−14
MC14016BFELG
SOEIAJ−14
(Pb−Free)
Shipping †
25 / Tape & Ammo Box
55 Units / Rail
2500 / Tape & Reel
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14016B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Input Voltage
Control Input
125_C
Max
Min
Typ (2)
Max
Min
Max
Unit
Symbol
1
VIL
5.0
10
15
−
−
−
−
−
−
−
−
−
1.5
1.5
1.5
0.9
0.9
0.9
−
−
−
−
−
−
Vdc
VIH
5.0
10
15
−
−
−
−
−
−
3.0
8.0
13
2.0
6.0
11
−
−
−
−
−
−
−
−
−
Vdc
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5.0
5.0
5.0
0.2
−
−
−
−
−
−
−
−
−
−
−
−
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
−
−
−
600
600
600
−
−
−
−
−
300
300
280
660
660
660
−
−
−
−
−
840
840
840
7.5
−
−
−
360
360
360
−
−
−
240
240
180
400
400
400
−
−
−
520
520
520
10
−
−
−
600
600
600
−
−
−
260
310
310
660
660
660
−
−
−
840
840
840
15
−
−
−
360
360
360
−
−
−
260
260
300
400
400
400
−
−
−
520
520
520
−
Iin
Input Capacitance
Control
Switch Input
Switch Output
Feed Through
−
Cin
“ON” Resistance
(VC = VDD, RL = 10 kW)
(Vin = + 5.0 Vdc)
(Vin = − 5.0 Vdc) VSS = − 5.0 Vdc
(Vin = ± 0.25 Vdc)
25_C
Min
Figure
Input Current Control
Quiescent Current
(Per Package) (3)
− 55_C
VDD
Vdc
2,3
IDD
4,5,6
RON
5.0
(Vin = + 7.5 Vdc)
(Vin = − 7.5 Vdc) VSS = − 7.5 Vdc
(Vin = ± 0.25 Vdc)
(Vin = + 10 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 5.6 Vdc)
(Vin = + 15 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 9.3 Vdc)
D “ON” Resistance
Between any 2 circuits in a common
package
(VC = VDD)
(Vin = ± 5.0 Vdc, VSS = − 5.0 Vdc)
(Vin = ± 7.5 Vdc, VSS = − 7.5 Vdc)
−
Input/Output Leakage Current
(VC = VSS)
(Vin = + 7.5, Vout = − 7.5 Vdc)
(Vin = − 7.5, Vout = + 7.5 Vdc)
−
pF
mAdc
Ohms
Ohms
DRON
−
−
5.0
7.5
−
−
−
−
15
10
−
−
−
−
−
−
−
mAdc
7.5
7.5
−
−
± 0.1
± 0.1
−
−
± 0.0015
± 0.0015
± 0.1
± 0.1
−
−
± 1.0
± 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV switch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
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3
MC14016B
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ELECTRICAL CHARACTERISTICS (4) (CL = 50 pF, TA = 25_C)
Characteristic
VDD
Vdc
Min
Typ (5)
Max
Unit
5.0
10
15
−
−
−
15
7.0
6.0
45
15
12
ns
5.0
10
15
−
−
−
34
20
15
90
45
35
−
5.0
10
15
−
−
−
30
50
100
−
−
−
mV
−
−
5.0
−
– 80
−
dB
10,11
−
5.0
10
15
−
−
−
24
25
30
−
−
−
nV/√Cycle
5.0
10
15
−
−
−
12
12
15
−
−
−
−
0.16
−
Figure
Symbol
Propagation Delay Time (VSS = 0 Vdc)
Vin to Vout
(VC = VDD, RL = 10 kW)
7
tPLH,
tPHL
Control to Output
(Vin v 10 Vdc, RL = 10 kW)
8
tPHZ,
tPLZ,
tPZH,
tPZL
Crosstalk, Control to Output (VSS = 0 Vdc)
(VC = VDD, Rin = 10 kW, Rout = 10 kW,
f = 1.0 kHz)
9
Crosstalk between any two switches (VSS = 0 Vdc)
(RL = 1.0 kW, f = 1.0 MHz,
V
crosstalk + 20 log10 out1)
Vout2
Noise Voltage (VSS = 0 Vdc)
(VC = VDD, f = 100 Hz)
(VC = VDD, f = 100 kHz)
ns
Second Harmonic Distortion (VSS = – 5.0 Vdc)
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 kW, f = 1.0 kHz)
−
−
5.0
Insertion Loss (VC = VDD, Vin = 1.77 Vdc,
VSS = − 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
V
Iloss + 20 log10 out)
Vin
(RL = 1.0 kW)
(RL = 10 kW)
(RL = 100 kW)
(RL = 1.0 MW)
12
−
5.0
Bandwidth (− 3.0 dB)
(VC = VDD, Vin = 1.77 Vdc, VSS = − 5.0 Vdc,
RMS centered @ 0.0 Vdc)
(RL = 1.0 kW)
(RL = 10 kW)
(RL = 100 kW)
(RL = 1.0 MW)
OFF Channel Feedthrough Attenuation
(VSS = − 5.0 Vdc)
Vout
+ –50 dB)
(VC = VSS, 20 log10
Vin
(RL = 1.0 kW)
(RL = 10 kW)
(RL = 100 kW)
(RL = 1.0 MW)
dB
−
−
−
−
12,13
BW
−
2.3
0.2
0.1
0.05
−
−
−
−
5.0
MHz
−
−
−
−
−
54
40
38
37
−
−
−
−
5.0
kHz
−
−
−
−
1250
140
18
2.0
−
−
−
−
4. The formulas given are for typical characteristics only at 25_C.
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
%
MC14016B
VC
IS
Vin
Vout
VIL: VC is raised from VSS until VC = VIL.
VIL: at VC = VIL: IS = ±10 mA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000
PD , POWER DISSIPATION (μW)
VDD = 15 Vdc
VDD
ID
PULSE
GENERATOR
TO ALL
4 CIRCUITS
VDD
Vout
10 k
CONTROL
INPUT
fc
VSS
Vin
TA = 25°C
1000
5.0 Vdc
100
10
1.0
5.0k 10k
PD = VDD x ID
10 Vdc
Figure 2. Quiescent Power Dissipation
Test Circuit
100k
1.0M
fc, FREQUENCY (Hz)
10M
50M
Figure 3. Typical Power Dissipation per Circuit
(1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE
700
RL = 10 kW
TA = 25°C
600
R ON, ON" RESISTANCE (OHMS)
R ON, ON" RESISTANCE (OHMS)
700
500
400
VC = VDD = 5.0 Vdc
VSS = − 5.0 Vdc
300
200
100
0
− 10 − 8.0
VC = VDD = 7.5 Vdc
VSS = − 7.5 Vdc
− 4.0
0
4.0
Vin, INPUT VOLTAGE (Vdc)
8.0
500
400
VC = VDD = 10 Vdc
300
200
VC = VDD = 15 Vdc
100
0
10
VSS = 0 Vdc
RL = 10 kW
TA = 25°C
600
0
Figure 4. VSS = − 5.0 V and − 7.5 V
2.0
6.0
10
14
Vin, INPUT VOLTAGE (Vdc)
Figure 5. VSS = 0 V
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5
18
20
MC14016B
Vout
RL
CL
Vin
Vout
20 ns
RL
VC
20 ns
90%
50%
Vin
tPLH
Figure 6. RON Characteristics
Test Circuit
10%
tPHL
VSS
50%
Vout
Vin
VDD
Figure 7. Propagation Delay Test Circuit
and Waveforms
Vout
VC
RL
VX
Vin
20 ns
50%
VC
Vout
Vout
VDD
90%
10%
tPZH
tPHZ
90%
10%
tPZL
CL
Vout
10 k
VC
VSS
Vin = VDD
Vx = VSS
Vin
tPLZ
90%
10%
15 pF
1k
Vin = VSS
Vx = VDD
Figure 8. Turn−On Delay Time Test Circuit
and Waveforms
Figure 9. Crosstalk Test Circuit
OUT
VC = VDD
IN
NOISE VOLTAGE (nV/ CYCLE)
35
QUAN−TECH
MODEL
2283
OR EQUIV
30
VDD = 15 Vdc
25
10 Vdc
20
5.0 Vdc
15
10
5.0
0
10
Figure 10. Noise Voltage Test Circuit
100
1.0k
f, FREQUENCY (Hz)
10 k
Figure 11. Typical Noise Characteristics
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6
100 k
MC14016B
TYPICAL INSERTION LOSS (dB)
2.0
0
RL = 1 MW AND 100 kW
10 kW
− 2.0
− 4.0
1.0
kW− 3.0 dB (R = 1.0 MW )
L
− 6.0
− 3.0 dB (RL = 10 kW )
− 8.0
Vout
− 3.0 dB (RL = 1.0 kW )
+ 2.5 Vdc
0.0 Vdc
− 2.5 Vdc
− 10
− 12
10 k
Vin
100 k
1.0M
10 M
fin, INPUT FREQUENCY (Hz)
RL
VC
100 M
Figure 12. Typical Insertion Loss/Bandwidth
Characteristics
Figure 13. Frequency Response Test Circuit
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. DV Across Switch
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7
MC14016B
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0−to−5 V
Digital Control signal is used to directly control a 5 Vp−p
analog signal.
The digital control logic levels are determined by V DD
and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, VDD = +5 V logic high
at the control inputs; V SS = GND = 0 V logic low.
The maximum analog signal level is determined by VDD
and V SS. The analog voltage must not swing higher than
V DD or lower than V SS.
The example shows a 5 V p−p signal which allows no
margin at either peak. If voltage transients above V DD
and/or below V SS are anticipated on the analog channels,
external diodes (Dx) are recommended as shown in Figure
B. These diodes should be small signal types able to absorb
the maximum anticipated current surges during clipping.
The absolute maximum potential difference between
V DD and VSS is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between V DD and V SS.
+5 V
VSS
VDD
+5 V
5 Vp−p
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
SWITCH
IN
+ 5.0 V
SWITCH
OUT
5 Vp−p
+ 2.5 V
ANALOG SIGNAL
0−TO−5 V DIGITAL
CONTROL SIGNALS
GND
MC14016B
Figure A. Application Example
VDD
VDD
Dx
Dx
SWITCH
IN
SWITCH
OUT
Dx
Dx
VSS
VSS
Figure B. External Germanium or Schottky Clipping Diodes
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8
MC14016B
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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9
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC14016B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC14016B
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
M_
L
7
1
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.056
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC14016B/D