IRFL210, SiHFL210 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Surface Mount 200 RDS(on) (Ω) VGS = 10 V 1.5 Qg (Max.) (nC) 8.2 • Dynamic dV/dt Rating Qgs (nC) 1.8 • Repetitive Avalanche Rated 4.5 • Fast Switching Qgd (nC) Configuration Single Available • Available in Tape and Reel RoHS* COMPLIANT • Ease of Paralleling D • Simple Drive Requirements • Lead (Pb)-free Available SOT-223 DESCRIPTION G S N-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOT-223 package is designed for surface-mounting using vapor phase, infrared, or wave soldering techniques. Its unique package design allows for easy automatic pick-and-place as with other SOT or SOIC packages but has the added advantage of improved thermal performace due to an enlarged tab for heatsinking. Power dissipation of greater than 1.25 W is possible in a typical surface mount application. ORDERING INFORMATION Package Lead (Pb)-free SnPb SOT-223 SOT-223 IRFL210PbF IRFL210TRPbFa SiHFL210-E3 SiHFL210T-E3a IRFL210 IRFL210TRa SiHFL210 SiHFL210Ta Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 200 Gate-Source Voltage VGS ± 20 Continuous Drain Current Pulsed Drain VGS at 10 V TC = 25 °C TC = 100 °C Currenta ID IDM V 0.96 0.6 A 7.7 Linear Derating Factor 0.025 Linear Derating Factor (PCB Mount)e 0.017 Single Pulse Avalanche Energyb UNIT W/°C EAS 50 mJ Repetitive Avalanche Currenta IAR 0.96 A Repetitive Avalanche Energya EAR 0.31 mJ * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91193 S-81377-Rev. A, 30-Jun-08 www.vishay.com 1 IRFL210, SiHFL210 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB Mount)e TA = 25 °C Operating Junction and Storage Temperature Range UNIT 3.1 PD Peak Diode Recovery dV/dtc Soldering Recommendations (Peak Temperature) LIMIT W 2.0 dV/dt 5.0 TJ, Tstg - 55 to + 150 V/ns °C 300d for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 81 mH, RG = 25 Ω, IAS = 0.96 A (see fig. 12). c. ISD ≤ 3.3 A, dI/dt ≤ 70 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient (PCB Mount)a PARAMETER RthJA - - 40 Maximum Junction-to-Case (Drain) RthJC - - 60 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 µA 200 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.30 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 200 V, VGS = 0 V - - 25 VDS = 160 V, VGS = 0 V, TJ = 125 °C - - 250 - - 1.5 Ω VDS = 50 V, ID = 0.58 A 0.51 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 140 - - 53 - - 15 - - - 8.2 Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 0.58 Ab VGS = 10 V µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 1.8 Gate-Drain Charge Qgd - - 4.5 Turn-On Delay Time td(on) - 8.2 - tr - 17 - - 14 - - 8.9 - - 4.0 - - 6.0 - Rise Time Turn-Off Delay Time Fall Time td(off) VGS = 10 V ID = 3.3 A, VDS = 160 V, see fig. 6 and 13b VDD = 100 V, ID = 3.3 A, RG = 24 Ω, RD = 30 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S www.vishay.com 2 Document Number: 91193 S-81377-Rev. A, 30-Jun-08 IRFL210, SiHFL210 Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT - - 0.96 S - - 7.7 TJ = 25 °C, IS = 0.96 A, VGS = 0 Vb - - 2.0 - 150 310 ns - 0.60 1.4 µC Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current MOSFET symbol showing the integral reverse p - n junction diode IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton D A G TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/µsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 101 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 100 10-1 4.5 V ID, Drain Current (A) ID, Drain Current (A) Top 25 °C 10-1 10-2 20 µs Pulse Width TC = 25 °C 100 10-1 100 4.5 V 10-1 20 µs Pulse Width TC = 150 °C 100 10-1 91193_02 101 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 150 °C Document Number: 91193 S-81377-Rev. A, 30-Jun-08 6 7 8 9 10 Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain Current (A) Top 5 VGS, Gate-to-Source Voltage (V) 91193_03 Fig. 1 - Typical Output Characteristics, TC = 25 °C VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 20 µs Pulse Width VDS = 50 V 4 101 VDS, Drain-to-Source Voltage (V) 91193_01 150 °C 100 91193_04 3.5 ID = 3.3 A 3.0 VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRFL210, SiHFL210 Vishay Siliconix 300 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 101 ISD, Reverse Drain Current (A) Capacitance (pF) 250 200 Ciss 150 Coss 100 Crss 50 0 100 0.8 102 ID = 3.3 A VDS = 160 V VDS = 100 V VDS = 40 V 12 8 4 0 91193_06 2 4 6 8 Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 2 5 100 µs 2 1 1 ms 5 0.1 TC = 25 °C TJ = 150 °C Single Pulse 1 10 QG, Total Gate Charge (nC) 2.0 10 2 For test circuit see figure 13 0 1.6 Operation in this area limited by RDS(on) 5 16 1.2 VSD, Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) VGS = 0 V 91193_07 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 20 25 °C 10-1 0.4 101 VDS, Drain-to-Source Voltage (V) 91193_05 150 °C 100 91193_08 2 5 10 ms 10 2 5 102 2 5 103 VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 91193 S-81377-Rev. A, 30-Jun-08 IRFL210, SiHFL210 Vishay Siliconix RD VDS VGS 1.0 ID, Drain Current (A) D.U.T. RG + - VDD 10 V 0.8 Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 0.6 Fig. 10a - Switching Time Test Circuit 0.4 VDS 0.2 90 % 0.0 25 50 75 100 125 150 10 % VGS TC, Case Temperature (°C) 91193_09 td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 102 0 - 0.5 10 1 0.2 0.1 0.05 0.02 PDM 0.01 Single Pulse (Thermal Response) t1 0.1 10-2 10-5 91193_11 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-4 10-3 10-2 0.1 1 10 102 103 t1, Rectangular Pulse Duration (S) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91193 S-81377-Rev. A, 30-Jun-08 www.vishay.com 5 IRFL210, SiHFL210 Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - I AS V DD VDS 10 V 0.01 Ω tp IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12a - Unclamped Inductive Test Circuit EAS, Single Pulse Energy (mJ) 120 ID 0.43 A 0.61 A Bottom 0.90 A Top 100 80 60 40 20 0 VDD = 50 V 25 91193_12C 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91193 S-81377-Rev. A, 30-Jun-08 IRFL210, SiHFL210 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91193. Document Number: 91193 S-81377-Rev. A, 30-Jun-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1