ONSEMI LMV821SQ3T2G

LMV821, LMV822, LMV824
Single, Dual, Quad Low
Voltage, Rail-to-Rail
Operational Amplifiers
The LMV821, LMV822, and LMV824 are operational amplifiers
with low input voltage offset and drift vs. temperature. In spite of low
quiescent current requirements these devices have 5 MHz bandwidth
and 1.4 V/ms slew rate. In addition they provide rail−to−rail output
swing into 600 W loads. The input common−mode voltage range
includes ground, and the maximum input offset voltage is only
3.5 mV. Substantially large capacitive loads can be driven by simply
adding a pullup resistor or isolation resistor.
The LMV821 (single) is available in a space−saving SC70−5 while
the dual and quad also come in ultra small SOIC and TSSOP packages.
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1
1
Low Offset Voltage: 3.5 mV
Very low Offset Drift: 1.0 mV/°C
High Bandwidth: 5 MHz
Rail−to−Rail Output Swing into a 600 W load
Capable of driving highly capacitive loads
These Devices are Pb−Free and are RoHS Compliant
SOIC−8
CASE 751
Typical Applications
• Notebook Computers
• PDAs
• Modem Transmitter/ Receivers
80
1
1
SOIC−14
CASE 751A
TSSOP−14
CASE 948G
ORDERING AND MARKING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
80
VS = 5 V, RL = 100 kW
70
Micro8]
CASE 846A
8
Features
•
•
•
•
•
•
1
SC−70
CASE 419A
70
60
CMRR (dB)
GAIN (dB)
50
40
30
20
60
VS = 5 V
50
10
40
0
−10
−20
1k
10k
100k
FREQUENCY (Hz)
1M
30
−1
10M
Figure 1. Gain vs. Frequency
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 1
0
1
2
3
4
INPUT COMMON MODE VOLTAGE (V)
5
Figure 2. CMRR vs. Input Common Mode
Voltage
1
Publication Order Number:
LMV821/D
LMV821, LMV822, LMV824
MARKING DIAGRAMS
SC−70
Micro8
SOIC−8
8
8
V822
ALYWG
G
V822
AYWG
G
AAEMG
G
1
AAE
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
V822
A
Y
W
G
(Note: Microdot may be in either location)
V822
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
1
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
(Note: Microdot may be in either location)
TSSOP−14
SOIC−14
14
14
LMV
824
ALYWG
G
LMV824G
AWLYWW
1
1
LMV824 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
LMV824 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
2
V−
3
+
−
−IN
4
IN A−
2
IN A+
3
7 OUT B
6 IN B−
B
+ −
OUTPUT
V−
A
− +
4
(Top View)
5 IN B+
OUT A
1
IN A−
2
A
− +
D
+ −
TSSOP−14
14 OUT D
OUT A
1
13 IN D−
IN A−
2
IN A+
3
12 IN D+
IN A+
3
12 IN D+
14 OUT D
A
− +
D
+ −
13 IN D−
V+
4
11 V−
V+
4
11 V−
IN B+
5
10 IN C+
IN B+
5
10 IN C+
IN B−
6
9
IN C−
IN B−
6
OUT B
7
8
OUT C
OUT B
7
(Top View)
+ −
V+
+IN
8 V+
1
B
− +
OUT A
5
SOIC−14
C
(Top View)
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2
+ −
1
Micro8/SOIC−8
B
− +
SC70−5
C
(Top View)
9
IN C−
8
OUT C
LMV821, LMV822, LMV824
MAXIMUM RATINGS
Symbol
VS
Rating
Supply Voltage (Operating Range VS = 2.7 V to 5.5 V)
Value
Unit
5.5
V
VIDR
Input Differential Voltage
$Supply Voltage
V
VICR
Input Common Mode Voltage Range
−0.5 to (V+) +0.5
V
10
mA
Maximum Input Current
tSO
Output Short Circuit (Note 1)
Continuous
TJ
Maximum Junction Temperature (Operating Range −40°C to 85°C)
qJA
Thermal Resistance
VESD
°C
°C/W
SC−70
280
Micro8
238
SOIC−8
212
SOIC−14
156
TSSOP−14
TSTG
150
190
Storage Temperature
−65 to 150
°C
Mounting Temperature (Infrared or Convection − 20 sec)
235
°C
ESD Tolerance
200
2000
V
Machine Model
Human Body Model
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
1. Continuous short−circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability. Shorting output to either V+ or V−
will adversely affect reliability.
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LMV821, LMV822, LMV824
2.7V DC ELECTRICAL CHARACTERISTICS Unless otherwise noted, all min/max limits are guaranteed for TA = 25°C, V+ = 2.7 V,
V− = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MW. Typical specifications represent the most likely parametric norm. Min/Max
specifications are guaranteed by testing, characterization, or statistical analysis.
Parameter
Input Offset Voltage
Symbol
Conditions
Min
VIO
Typ
Max
Unit
1
3.5
mV
TA = −40°C to +85°C
Input Offset Voltage Average
Drift
Input Bias Current
4
TCVOS
1
IB
105
TA = −40°C to +85°C
Input Offset Current
IIO
0.5
CMRR
0 V v VCM v 1.7 V
70
TA = −40°C to +85°C
68
Power Supply Rejection Ratio
PSRR
1.5 V v V+ v 4 V, V − = −1 V, VO = 0 V,
VCM = 0.0 V
75
TA = −40°C to +85°C
70
Input Common−Mode Voltage
Range
VCM
For CMRR w 53 dB
and TA = −40°C to +85°C
−0.2
−0.3 to
2.0
AV
RL = 600 W, VO = 0.5 V to 2.5 V
80
95
VOH
VOL
VOL
IO
Supply Current
ICC
TA = −40°C to +85°C
70
RL = 2 kW, VO = 0.5 V to 2.5 V
83
TA = −40°C to +85°C
80
RL = 600 W to 1.35 V
2.5
TA = −40°C to +85°C
2.4
85
dB
2.6
TA = −40°C to +85°C
2.5
12
Sinking, VO = 2.7 V
12
0.12
mA
26
0.242
0.3
0.5
0.5
TA = −40°C to +85°C
4
0.21
2.66
TA = −40°C to +85°C
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V
0.2
Sourcing, VO = 0 V
TA = −40°C to +85°C
dB
2.58
0.08
RL = 2 kW to 1.35 V
LMV824 (All Four Applications)
V
0.3
RL = 2 kW to 1.35 V
LMV822 (Both Applications)
1.9
89
0.13
RL = 600 W to 1.35 V
LMV821 (Single)
nA
dB
TA = −40°C to +85°C
Output Current
30
85
TA = −40°C to +85°C
VOH
nA
50
Common−Mode Rejection
Ratio
Output Swing
210
315
TA = −40°C to +85°C
Large Signal Voltage Gain
mV/°C
0.7
0.9
1
1.3
1.5
mA
LMV821, LMV822, LMV824
2.5V DC ELECTRICAL CHARACTERISTICS Unless otherwise noted, all min/max limits are guaranteed for TA = 25°C, V+ = 2.5 V,
V− = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MW. Typical specifications represent the most likely parametric norm. Min/Max
specifications are guaranteed by testing, characterization, or statistical analysis.
Parameter
Input Offset Voltage
Symbol
Conditions
VIO
TA = −40°C to +85°C
Min
Typ
Max
Unit
1
3.5
mV
4
Output Swing
VOH
VOL
RL = 600 W to 1.25 V
2.3
TA = −40°C to +85°C
2.2
0.13
RL = 600 W to 1.25 V
TA = −40°C to +85°C
VOH
VOL
V
2.37
0.20
0.3
RL = 2 kW to 1.25 V
2.4
TA = −40°C to +85°C
2.3
2.46
0.08
RL = 2 kW to 1.25 V
TA = −40°C to +85°C
0.12
0.20
2.7V AC ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.7 V, V− =
0 V, VCM = 1.0 V, VO = V+/2 and RL > 1 MW. Typical specifications represent the most likely parametric norm. Min/Max specifications are
guaranteed by testing, characterization, or statistical analysis.
Parameter
Slew Rate
Gain Bandwidth Product
Symbol
Conditions
SR
(Note 2)
GBWP
Min
Typ
Max
Unit
1.5
V/uS
5
MHz
Phase Margin
qm
55
°
Gain Margin
Gm
12.9
dB
Input−Referred Voltage Noise
en
f = 1 kHz, VCM = 1 V
12
nV/√Hz
Input−Referred Current Noise
in
f = 1kHz
0.2
pA/√Hz
THD
f = 1 kHz, AV = −2, RL = 10 kW , VO = 1.8 VPP
0.023
%
(Note 3)
135
dB
Total Harmonic Distortion
Amplifier−to−Amplifier Isolation
2. Connected as voltage follower with input step from 0.5 V to 1.5 V. Number specified is the average of the positive and negative slew rates.
3. Input referred, RL = 100 kW connected to V+/2. Each amp excited in turn with 1kHz to produce VO = 3 VPP. For Supply Voltages < 3 V,
VO = V+.
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5
LMV821, LMV822, LMV824
5V DC ELECTRICAL CHARACTERISTICS Unless otherwise noted, all min/max limits are guaranteed for TA = 25°C, V+ = 5 V,V−
= 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MW. Typical specifications represent the most likely parametric norm. Min/Max specifications
are guaranteed by testing, characterization, or statistical analysis.
Parameter
Input Offset Voltage
Symbol
Conditions
Min
VIO
Typ
Max
Unit
1
3.5
mV
TA = −40°C to +85°C
Input Offset Voltage Average
Drift
Input Bias Current
4
TCVOS
1
IB
119
TA = −40°C to +85°C
Input Offset Current
IIO
0.5
CMRR
0 V v VCM v 4.0 V
72
TA = −40°C to +85°C
70
Power Supply Rejection Ratio
PSRR
1.7 V v V+ v 4 V, V − = 1 V, VO = 0 V,
VCM = 0.0 V
75
TA = −40°C to +85°C
70
Input Common−Mode Voltage
Range
VCM
For CMRR w 58 dB
and TA = − 40°C to +85°C
−0.2
−0.2 to
4.3
AV
RL = 600 W, VO = 1.0 V to 4.0 V
87
100
VOH
VOL
VOL
Supply Current
IO
TA = −40°C to +85°C
73
RL = 2 kW, VO = 1.0 V to 4.0 V
84
TA = −40°C to +85°C
82
RL = 600 W to 2.5 V
4.75
TA = −40°C to +85°C
4.7
85
dB
4.85
TA = −40°C to +85°C
4.8
20
TA = −40°C to +85°C
10
Sinking, Vo = 5 V
20
TA = −40°C to +85°C
15
0.15
mA
45
40
TA = −40°C to +85°C
0.4
0.6
0.5
TA = −40°C to +85°C
6
0.33
4.9
0.3
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V
0.2
Sourcing, Vo = 0 V
TA = −40°C to +85°C
dB
4.84
0.1
RL = 2 kW to 2.5 V
LMV824 (All Four Applications)
V
0.4
RL = 2 kW to 2.5 V
LMV822 (Both Applications)
4.2
99
0.17
RL = 600 W to 2.5 V
ICC
nA
dB
TA = −40°C to +85°C
Output Current
30
90
TA = −40°C to +85°C
VOH
nA
50
Common−Mode Rejection
Ratio
Output Swing
245
380
TA = −40°C to +85°C
Large Signal Voltage Gain
mV/°C
0.7
0.9
1
1.3
1.5
mA
LMV821, LMV822, LMV824
5V AC ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5 V, V− = 0 V,
VCM = 2.0 V, VO = V+/2 and RL > 1 MW. Typical specifications represent the most likely parametric norm. Min/Max specifications are
guaranteed by testing, characterization, or statistical analysis.
Parameter
Slew Rate
Symbol
Conditions
SR
(Note 4)
Min
Typ
Max
Unit
2
V/mS
GBWP
5.6
MHz
Phase Margin
qm
63
°
Gain Margin
Gm
11.7
dB
Input−Referred Voltage Noise
en
11
nV/√Hz
Gain Bandwidth Product
Input−Referred Current Noise
Total Harmonic Distortion
Amplifier−to−Amplifier Isolation
f = 1 kHz, VCM = 1 V
in
f = 1 kHz
0.21
pA/√Hz
THD
f = 1 kHz, AV = −2, RL = 10 kW , VO = 4.11 VPP
0.012
%
(Note 5)
135
dB
4. Connected as voltage follower with input step from 0.5 V to 3.5 V. Number specified is the average of the positive and negative slew rates.
5. Input referred, RL = 100 kW connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP. (For Supply Voltages < 3 V,
VO = V+).
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7
LMV821, LMV822, LMV824
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
100
70
+PSRR (dB)
80
60
40
VS = 2.7 V
60
50
40
30
20
20
10
0
100
1k
10k
0
100
100k
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3. Crosstalk Rejection vs. Frequency
Figure 4. +PSRR vs. Frequency
100
80
90
70
80
60
70
−PSRR (dB)
VS = 5 V
80
VS = 2.7 V
50
40
30
VS = 5 V, CL = 0 pF, RL = 100 kW
40
30
20
10
20
0
10
−10
0
100
1k
10k
100k
−20
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. −PSRR vs. Frequency
Figure 6. Gain vs. Frequency
80
VS = 2.7 V, CL = 0 pF, RL = 100 kW
70
60
GAIN (dB)
50
40
30
20
10
0
−10
−20
1M
50
VS = 5 V
60
GAIN (dB)
CROSSTALK REJECTION (dB)
120
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 7. Gain vs. Frequency
Figure 8. Non−Inverting Stability vs.
Capacitive Load
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8
10M
LMV821, LMV822, LMV824
TYPICAL PERFORMANCE CHARACTERISTICS
3
AV = 1, RL = 100 kW, TA = 25°C
2.5
GAIN (dB)
SR+
2
1.5
SR−
1
0.5
2.5
3
3.5
4
4.5
5
FREQUENCY (Hz)
Figure 9. Gain vs. Frequency
Figure 10. Non−Inverting Large Signal Step
Response
Figure 11. Non−Inverting Small Signal Step
Response
Figure 12. Inverting Large Signal Step
Response
Figure 13. Inverting Small Signal Step
Response
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9
LMV821, LMV822, LMV824
APPLICATIONS INFORMATION
50 k
R1
5.0 k
VCC
VCC
R2
10 k
MC1403
2.5 V
VO
LMV821
VO
LMV821
VCC
−
Vref
−
+
+
1
V ref + V CC
2
R1
V O + 2.5 V(1 )
)
R2
R
R
Figure 14. Voltage Reference
fO +
C
C
1
2pRC
For: fo = 1.0 kHz
R = 16 kW
C = 0.01 mF
Figure 15. Wien Bridge Oscillator
VCC
C
R1
Vin
R2
C
R3
−
Hysteresis
Vin
R1
+
R2
VOH
Vref
LMV821
−
VO
VOL
VO
CO = 10 C
Vref
VO
+
CO
LMV821
VinL
Given: fo = center frequency
A(fo) = gain at center frequency
VinH
Choose value fo, C
Q
Then : R3 +
pf O C
Vref
R1
(V OL * V ref) ) V ref
R1 ) R2
R1
V inH +
(V OH * V ref) ) V ref
R1 ) R2
R1
H+
(V OH * V OL)
R1 ) R2
V inL +
R1 +
R2 +
R3
2 A(f O)
R1 R3
4Q 2 R1 * R3
Figure 16. Comparator with Hysteresis
For less than 10% error from operational amplifier,
((QO fO)/BW) < 0.1 where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Figure 17. Multiple Feedback Bandpass Filter
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10
LMV821, LMV822, LMV824
ORDERING INFORMATION
Number
of
Channels
Specific Device Marking
Package Type
Shipping†
LMV821SQ3T2G*
Single
AAE
SC−70
(Pb−Free)
3000 / Tape & Reel
LMV822DMR2G*
Dual
V822
Micro8
(Pb−Free)
4000 / Tape & Reel
LMV822DR2G*
Dual
V822
SOIC−8
(Pb−Free)
2500 / Tape & Reel
LMV824DR2G
Quad
LMV824
SOIC−14
(Pb−Free)
2500 / Tape & Reel
LMV824DTBR2G
Quad
LMV
824
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Contact factory.
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11
LMV821, LMV822, LMV824
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
H
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
K
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12
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
LMV821, LMV822, LMV824
PACKAGE DIMENSIONS
Micro8™
CASE 846A−02
ISSUE H
D
HE
PIN 1 ID
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
T B
M
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
−T− PLANE
0.038 (0.0015)
A
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
LMV821, LMV822, LMV824
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
S
M
J
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
LMV821, LMV822, LMV824
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
LMV821, LMV822, LMV824
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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16
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For additional information, please contact your local
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LMV821/D