HEX D FLIP-FLOP WITH MASTER RESET The MC74AC174/74ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. • Outputs Source/Sink 24 mA • ′ACT174 Has TTL Compatible Inputs VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 N SUFFIX CASE 648-08 PLASTIC CP 9 PIN NAMES 1 2 3 4 5 6 7 8 MR Q0 D0 D1 Q1 D2 Q2 GND D0–D5 CP MR Q0–Q5 Data Inputs Clock Pulse Input Master Reset Input Outputs LOGIC SYMBOL TRUTH TABLE Inputs Output MR CP D Q L H H H X X H L X L H L Q L D SUFFIX CASE 751B-05 PLASTIC D0 D1 D2 D3 D4 D5 CP MR Q0 Q1 Q2 Q3 Q4 Q5 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition of Clock FACT DATA 5-1 MC74AC174 MC74ACT174 FUNCTIONAL DESCRIPTION The MC74AC174/74ACT174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The MC74AC174/ 74ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. LOGIC DIAGRAM MR CP D5 D4 D Q D3 D CP CD Q D CP CD Q5 D2 Q D CP CD Q4 D1 Q Q D CP CD Q3 D0 D CP CD Q2 Q CP CD Q1 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. MAXIMUM RATINGS* Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C VCC DC Supply Voltage (Referenced to GND) Vin * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. FACT DATA 5-2 MC74AC174 MC74ACT174 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH IOL Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs tr, tf Min Unit V VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 V ns/V ns/V 140 °C 85 °C Output Current — High –24 mA Output Current — Low 24 mA –40 25 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = –40°C to +85°C Typ VIH VIL VOH 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC – 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC – 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 5.5 ±0.1 Maximum Low Level Output Voltage Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current ICC Guaranteed Limits 3.0 4.5 5.5 IIN IOHD Conditions Minimum High Level Input Voltage 3.0 4.5 5.5 VOL Unit Maximum Quiescent Supply Current 3.0 4.5 5.5 0.002 0.001 0.001 IOUT = –50 µA V *VIN = VIL or VIH –12 mA IOH –24 mA –24 mA IOUT = 50 µA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 µA VI = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. FACT DATA 5-3 MC74AC174 MC74ACT174 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Unit Fig. No. MHz 3-3 Max fmax Maximum Clock Frequency 3.3 5.0 90 100 100 125 70 100 tPLH Propagation Delay CP to Qn 3.3 5.0 2.0 1.5 9.0 6.0 11.5 8.5 1.5 1.0 12.5 9.5 ns 3-6 tPHL Propagation Delay CP to Qn 3.3 5.0 2.0 1.5 8.5 6.0 11.0 8.0 1.5 1.0 12.0 9.0 ns 3-6 tPHL Propagation Delay MR to Qn 3.3 5.0 2.5 1.5 9.0 7.0 11.5 9.0 2.0 1.5 12.5 10.5 ns 3-6 Unit Fig. No. * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to CP 3.3 5.0 2.5 2.0 6.5 5.0 7.0 5.5 ns 3-9 th Hold Time, HIGH or LOW Dn to CP 3.3 5.0 1.0 0.5 3.0 3.0 3.0 3.0 ns 3-9 tw MR Pulse Width, LOW 3.3 5.0 1.0 1.0 5.5 5.0 7.0 5.0 ns 3-6 tw CP Pulse Width 3.3 5.0 1.0 1.0 5.5 5.0 7.0 5.0 ns 3-6 trec Recovery TIme MR to CP 3.3 5.0 0 0 2.5 2.0 2.5 2.0 ns 3-6 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-4 MC74AC174 MC74ACT174 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = –40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC – 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC – 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC – 2.1 V 4.5 5.5 VOL 4.5 5.5 Maximum Low Level Output Voltage 0.001 0.001 IOUT = –50 µA *VIN = VIL or VIH –24 mA IOH –24 mA V IOUT = 50 µA V IIN Maximum Input Leakage Current 5.5 ∆ICCT Additional Max. ICC/Input 5.5 IOLD †Minimum Dynamic Output Current 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 0.6 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) Min 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Max Min Unit Fig. No. MHz 3-3 Max fmax Maximum Clock Frequency 5.0 165 tPLH Propagation Delay CP to Qn 5.0 1.5 10.5 1.5 11.5 ns 3-6 tPHL Propagation Delay CP to Qn 5.0 1.5 10.5 1.5 11.5 ns 3-6 tPHL Propagation Delay MR to Qn 5.0 1.5 9.5 1.5 11.0 ns 3-6 * Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-5 140 MC74AC174 MC74ACT174 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to CP 5.0 1.5 1.5 ns 3-9 th Hold Time, HIGH or LOW Dn to CP 5.0 2.0 2.0 ns 3-9 tw MR Pulse Width, LOW 5.0 3.0 3.5 ns 3-6 tw CP Pulse Width HIGH or LOW 5.0 3.0 3.5 ns 3-6 trec Recovery Time MR to CP 5.0 0.5 0.5 ns 3-6 * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 85 pF VCC = 5.0 V FACT DATA 5-6 MC74AC174 MC74ACT174 OUTLINE DIMENSIONS N SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ FACT DATA 5-7 *MC74AC174/D* MC74AC174/D