Product Preview " " "! The MC74AC/ACT823 consists of nine D-type edge-triggered flip-flops. This device has 3-state outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enabled pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flips. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The MC74AC/ACT823 has Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW, and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. • 3-State Outputs for Bus Interfacing • Broad Side Pin Configuration • ACT has TTL – Compatible Inputs • High Speed Parallel Positive Edge-Triggered D-Type Flip-Flops • High Performance Bus Interface Buffering for Busses Carrying Parity • Outputs Source/Sink 24 mA 9-BIT REGISTER WITH 3-STATE OUTPUTS 24 1 N SUFFIX CASE 724-03 PLASTIC PACKAGE Pinout: 24-Lead Packages (Top View) VCC 24 O0 23 O1 22 O2 21 O3 20 O4 19 O5 18 O6 O7 O8 EN CP 17 16 15 14 13 DW SUFFIX CASE 751E-04 SOIC PACKAGE PIN NAMES 1 2 3 4 5 6 7 8 9 10 11 12 OE1 D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND D0 – D8 O0 – O8 OE EN CLR CP FUNCTION TABLE Inputs Internal Outputs Data Inputs Data Outputs Output Enable Clock Enable Clear Clock Input Operating Mode OE CLR EN CP Dn Q O H H H L X X L L L L X X ↑ ↑ X X L H X X L H L L Z Z Z L H L H H H H X X X X NC NC Z NC Hold Hold H H H H L L ↑ ↑ L H L H Z Z Load Load L L H H L L ↑ ↑ L H L H L H Load Load High Z High Z Clear Clear H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; Z = High Impedance State; ↑ = LOW-to-High Transition; NC = No Change This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. FACT DATA 5-1 MC74AC823 MC74ACT823 LOGIC SYMBOL O0 O1 O2 O3 O4 O5 O8 O7 O6 CLR OE CP EN D0 D1 D2 D3 D4 D5 D8 D7 D6 LOGIC DIAGRAM EN CP D0 D1 D2 CP D3 CP D CP D Q CP D Q CLR D8 CP D Q CLR D7 CP D Q CLR D6 CP D Q CLR D5 CP D Q CLR D4 Q CLR CP D D Q CLR Q CLR CLR CLR OE Q0 Q1 Q2 Q3 FACT DATA 5-2 Q4 Q5 Q6 Q7 Q8 MC74AC823 MC74ACT823 MAXIMUM RATINGS* Symbol Parameter Value Units –0.5 to +7.0 V V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 VO DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Sink/Source Current, per Pin ± 50 mA ICC DC VCC or GND Current per Output Pin ± 50 mA Tstg Storage Temperature Range –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin DC Input Voltage, Output Voltage (Ref. to GND) ∆t/∆ v Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH IOL Min Typ Min ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 Unit V V ns/V ns/V 140 °C 85 °C Output Current — HIGH –24 mA Output Current — LOW 24 mA –40 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. FACT DATA 5-3 25 MC74AC823 MC74ACT823 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = –40°C to +85°C Typ VIH VIL VOH 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC – 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC – 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 5.5 ±0.1 5.5 ±0.5 Maximum Low Level Output Voltage Maximum Input Leakage Current IOZ Maximum 3-State Current IOHD ICC Guaranteed Limits 3.0 4.5 5.5 IIN IOLD Conditions Minimum High Level Input Voltage 3.0 4.5 5.5 VOL Unit †Minimum Dynamic Output Current Maximum Quiescent Supply Current 3.0 4.5 5.5 0.002 0.001 0.001 IOUT = – 50 µA V *VIN = VIL or VIH – 12 mA IOH – 24 mA – 24 mA IOUT = 50 µA V V *VIN = VIL or VIH 12 mA IOH 24 mA 24 mA ±1.0 µA VI = VCC, GND ±5.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one input loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. FACT DATA 5-4 MC74AC823 MC74ACT823 AC CHARACTERISTICS Symbol Parameter VCC* (V) Min 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Max Min Unit Fig. No. Max fmax Maximum Clock Frequency 3.3 5.0 MHz tPLH Propagation Delay CP to Qn 3.3 5.0 ns tPHL Propagation Delay CP to Qn 3.3 5.0 ns tPHL Propagation Delay CLR to On 3.3 5.0 ns tPZH Output Enable Time OE to On 3.3 5.0 ns tPZL Output Enable Time OE to On 3.3 5.0 ns tPHZ Output Disable Time OE to On 3.3 5.0 ns tPLZ Output Disable Time OE to On 3.3 5.0 ns * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Unit Guaranteed Minimum ts Set-up Time, HIGH or LOW Dn to CP 3.3 5.0 ns th Hold Time, HIGH or LOW Dn to CP 3.3 5.0 ns ts Set-up Time, HIGH or LOW EN to CP 3.3 5.0 ns th Hold Time, HIGH or LOW EN to CP 3.3 5.0 ns tw CP Pulse Width HIGH or LOW 3.3 5.0 ns CLR Pulse Width, LOW 3.3 5.0 ns CLR to CP Recovery Time 3.3 5.0 ns tw trec * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-5 Fig. No. MC74AC823 MC74ACT823 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = –40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC – 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC – 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOH 24 mA 5.5 ±0.1 ±1.0 µA VI = VCC, GND ±0.5 ±5.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 V V IOUT = – 50 µA *VIN = VIL or VIH – 24 mA IOH – 24 mA IOUT = 50 µA IIN Maximum Input Leakage Current IOZ Maximum 3-State Current 5.5 ∆ICCT Additional Max. ICC/Input 5.5 IOLD †Minimum Dynamic Output Current 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 0.6 5.5 1.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one input loaded at a time. FACT DATA 5-6 MC74AC823 MC74ACT823 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Unit Fig. No. Max fmax Maximum Clock Frequency 5.0 120 158 tPLH Propagation Delay CP to Qn 5.0 1.5 5.5 9.5 1.5 10.5 ns tPHL Propagation Delay CP to Qn 5.0 2.0 5.5 9.5 1.5 10.5 ns tPHL Propagation Delay CLR to On 5.0 2.5 8.0 13.5 2.0 15.5 ns tPZH Output Enable Time OE to On 5.0 1.5 6.0 10.5 1.5 11.5 ns tPZL Output Enable Time OE to On 5.0 2.0 6.5 11.0 1.5 12.0 ns tPHZ Output Disable Time OE to On 5.0 1.5 6.5 11.0 1.5 12.0 ns tPLZ Output Disable Time OE to On 5.0 1.5 6.0 10.5 1.5 11.5 ns 109 MHz * Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Unit Guaranteed Minimum ts Set-up Time, HIGH or LOW Dn to CP 5.0 0.5 2.5 2.5 ns th Hold Time, HIGH or LOW Dn to CP 5.0 0 2.5 2.5 ns ts Set-up Time, HIGH or LOW EN to CP 5.0 0 2.0 2.5 ns th Hold Time, HIGH or LOW EN to CP 5.0 0 1.0 1.0 ns tw CP Pulse Width, HIGH or LOW 5.0 2.5 4.5 5.5 ns tw CLR Pulse Width, LOW 5.0 3.0 5.5 5.5 ns trec CLR to CP Recovery TIme 5.0 1.5 3.5 4.0 ns * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 44.0 pF VCC = 5.0 V FACT DATA 5-7 Fig. No. MC74AC823 MC74ACT823 OUTLINE DIMENSIONS N SUFFIX PLASTIC DIP PACKAGE CASE 724–03 ISSUE D –A– 24 13 1 12 NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. –B– L C –T– NOTE 1 K SEATING PLANE N E G M J F D 24 PL 0.25 (0.010) 24 PL 0.25 (0.010) T A M M T B M 24 12X P 0.010 (0.25) 1 M B M 12 D J 0.010 (0.25) M T A S B S F R C –T– M 22X MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– SEATING PLANE INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E –A– 24X M DIM A B C D E F G J K L M N K G X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ FACT DATA 5-8 *MC74AC823/D* MC74AC823/D