CS4192 Single Air−Core Gauge Driver The CS4192 is a monolithic BiCMOS integrated circuit used to translate a digital 10−bit word from a microprocessor/microcontroller to complementary DC outputs. The DC outputs drive an air−core meter commonly used in vehicle instrument panels. The 10 bits of data are used to linearly control the quadrature coils of the meter directly with a 0.35° resolution and ±1.2° accuracy over the full 360° range of the gauge. The interface from the microcontroller is by a Serial Peripheral Interface (SPI) compatible serial connection using up to a 2.0 MHz shift clock rate. The digital code, which is directly proportional to the desired gauge pointer deflection, is shifted into a DAC and multiplexer. These two blocks provide a tangential conversion function to change the digital data into the appropriate DC coil voltage for the angle demanded. The tangential algorithm creates approximately 40% more torque in the meter movement than does a sin−cos algorithm at 45°, 135°, 225°, and 315° angles. This increased torque reduces the error due to pointer droop at these critical angles. Each output buffer is capable of supplying up to 70 mA per coil and the buffers are controlled by a common OE enable pin. The output buffers are turned off when OE is brought low, while the logic portion of the chip remains powered and continues to operate normally. OE must be high before the falling edge of CS to enable the output buffers. The status pin (ST) reflects the state of the outputs and is low whenever the outputs are disabled. The Serial Gauge Driver is self−protected against fault conditions. Each driver is protected for 125 mA (typ) overcurrent while a global thermal protection circuit limits junction temperature to 170°C (typ). The output drivers are disabled anytime the IC protection circuitry detects an overcurrent or overtemperature fault. The drivers remain disabled until a falling edge is presented on CS. If the fault is still present, the output drivers automatically disable themselves again. Features • • • • • • • • • Serial Input Bus 2.0 MHz Operating Frequency Tangential Drive Algorithm 70 mA Drive Circuits 0.5° Accuracy (Typ) Power−On−Reset Protection Features ♦ Output Short Circuit ♦ Overtemperature Internally Fused Leads in SOIC−16 WB Package Pb−Free Packages are Available* September, 2005 − Rev. 7 16 1 SOIC−16 WB DWF SUFFIX CASE 751G MARKING DIAGRAM 16 CS4192 AWLYYWWG 1 CS4192 A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS 1 SIN− SIN+ VBB GND GND SI VCC OE *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 http://onsemi.com 1 16 COS+ COS− SO GND GND ST CS SCLK ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Publication Order Number: CS4192/D CS4192 VCC VBB POR SI SCLK CS Serial to Parallel Shift Register LOGIC VTOP D0−D6 7 Bit DAC VVAR MUX VBAT SO D7−D9 POR ST Overcurrent R FAULT Latch S Q ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ SIN+ SIN− COS+ COS− Output Amplifiers ENA Overtemp OE GND Figure 1. Block Diagram MAXIMUM RATINGS Rating Value Unit −1.0 to 16.5 −1.0 to 6.0 V −1.0 to 6.0 V Steady State Output Current ±100 mA Forced Injection Current (Inputs and Supply) ±10 mA Operating Junction Temperature, (TJ) 150 °C −65 to 150 °C 230 peak °C ESD Susceptibility (Human Body Model) 2.0 kV Package Thermal Resistance, SOIC−16 WB Junction−to−Case, RqJC Junction−to−Ambient, RqJA 18 75 °C/W °C/W Supply Voltage VBB VCC Digital Inputs Storage Temperature Range Lead Temperature Soldering Reflow (SMD styles only) (Note 1) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 60 seconds max above 183°. http://onsemi.com 2 CS4192 ELECTRICAL CHARACTERISTICS (−40°C ≤ TJ ≤ 105°C; 7.5 V ≤ VBB ≤ 14 V, 4.5 V ≤ VCC ≤ 5.5 V; unless otherwise specified. Note 2) Characteristic Test Conditions Min Typ Max Unit Supply Voltages and Currents VBB Quiescent Current Output disabled (OE = 0 V) [RCOS, RSIN = RL(MIN)] @ 45° (code = X’080) VBB = 14 V − − 1.0 − 5.0 175 mA mA VCC Quiescent Current OE, CS, DI = high, VBB = 0 V, SCLK = 2.0 MHz − − 1.15 mA Digital Inputs and Outputs Output High Voltage SO, IOH = 0.8 mA VCC − 0.8 − − V Output Low Voltage SO, IOL = 0.8 mA ST, IOL = 2.5 mA − − − − 0.4 0.8 V V Output Off Leakage ST, VCC = 5.0 V − − 25 mA Input High Voltage CS, SCLK, SI, OE 0.7 × VCC − − V Input Low Voltage CS, SCLK, SI, OE − − 0.3 × VCC V Input High Current CS, SCLK, SI, OE; VIN = 0.7 × VCC − − 1.0 mA Input Low Current CS, SCLK, SI, OE; VIN = 0.3 × VCC − − 1.0 mA −1.2 ±0.5 +1.2 deg Analog Outputs Output Function Accuracy − Output Shutdown Current, Source VBB = 14 V 70 125 250 mA Output Shutdown Current, Sink VBB = 14 V 70 125 250 mΑ Output Shutdown Current, Source VBB = 7.5 V 43 125 250 mΑ Output Shutdown Current, Sink VBB = 7.5 V 43 125 250 mΑ Thermal Shutdown − − 170 − °C Thermal Shutdown Hysteresis − − 20 − °C Coil Drive Output Voltage − − 0.748 × VBB − V − − − 229 171 150 − − − W W W Minimum Load Resistance TA = 105°C TA = 25°C TA = −40°C Shift Clock Frequency − − − 2.0 MHz SCLK High Time − 175 − − ns SCLK Low Time − 175 − − ns SO Rise Time 0.75 V to VCC − 1.2 V; CL = 90 pF − − 150 ns SO Fall Time 0.75 V to VCC − 1.2 V; CL = 90 pF − − 150 ns SO Delay Time CL = 90 pF − − 150 ns SI Setup Time − 75 − − ns SI Hold Time − 75 − − ns 0 − − ns 75 − − ns CS Setup Time CS Hold Time Note 3. − 2. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. 3. OE must be high at falling edge of CS. This condition ensures valid output for any given input. http://onsemi.com 3 CS4192 PIN FUNCTION DESCRIPTION PACKAGE PIN # 16 Lead SOIC Wide PIN SYMBOL 1 SIN− Negative output for SINE coil. 2 SIN+ Positive output SINE coil. 3 VBB Analog supply. Nominally 13.5 V. 4, 5, 12, 13 GND Ground. 6 SI Serial data input. Data present at the rising edge of the clock signal is shifted into the internal shift register. 7 VCC 5.0 V logic supply. The internal registers and latches are reset by a POR generated by the rising edge of the voltage on this pin. 8 OE Controls the state of the output buffers. A logic low on this pin turns them off. 9 SCLK 10 CS When high allows data at SI to be shifted into part with the rising edges of SCLK. The falling edge transfers the shift register contents into the DAC and multiplexer to update the output buffers. The falling edge also reenables the output drivers if they have been disabled by a fault. 11 ST STATUS reflects the state of the outputs and is low anytime the outputs are disabled, either by OE or the internal protection circuitry. Requires external pullup resistor. 14 SO Serial data output. Existing 10−bit data is shifted out when new data is shifted in. Allows cascading of multiple devices on common serial port. 15 COS− Negative output for COSINE coil. 16 COS+ Positive output for COSINE coil. FUNCTION Serial clock for shifting in/out of data. Rising edge shifts data on SI into the shift register and the falling edge changes the data on SO. ORDERING INFORMATION Package Shipping † CS4192XDWF16 SOIC−16 WB 47 Units / Rail CS4192XDWF16G SOIC−16 WB (Pb−Free) 47 Units / Rail CS4192XDWFR16 SOIC−16 WB 1000 Units / Reel CS4192XDWFR16G SOIC−16 WB (Pb−Free) 1000 Units / Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 CS4192 APPLICATIONS INFORMATION THEORY OF OPERATION Quadrant II The SACD is for interfacing between a microcontroller or microprocessor and air−core meter movements commonly used in automotive vehicles for speedometers and tachometers. These movements are built using two coils placed at a 90° orientation to each other. A magnetized disc floats in the middle of the coils and responds to the magnetic field generated by each coil. The disc has a shaft attached to it that protrudes out of the assembly. A pointer indicator is attached to this shaft and in conjunction with a separate printed scale displays the vehicle’s speed or the engine’s speed. The disc (and pointer) respond to the vector sum of the voltages applied to the coils. Ideally, this relationship follows a sine/cosine equation. Since this is a transcendental and non−linear function, devices of this type use an approximation for this relationship. The SACD uses a tangential algorithm as shown in Figure 2. Only one output varies in any 45 degree range. q + 180°−Tan−1 For q + 90.176°to 134.824° : VSIN + 0.748 VBB VCOS + *Tan (q * 90°) 45° 90° 135° 180° 0.748 VSIN + Tan(180° * q) VCOS + *0.748 0.748 270° 315° VBB VBB Quadrant III q + 180° ) Tan−1 SIN) * VSIN* ƫ ƪVVCOS) * VCOS* For q + 180.176°to 224.824° : VSIN + *Tan (q * 180°) 225° VBB For q + 135.176°to 179.824° : Degrees of Rotation 0° SIN) * VSIN* ƫ ƪVVCOS) * VCOS* VCOS + *0.748 360° 0.748 VBB VBB Max(128) For q + 225.176°to 269.824° : SIN+ Output Min(0) VSIN + *0.748 VBB VCOS + *Tan (270° * q) Max(128) SIN− Output Min(0) 0.748 VBB Quadrant IV Max(128) q + 360° * Tan−1 COS+ Output SIN) * VSIN* ƫ ƪVVCOS) * VCOS* Min(0) For q + 270.176°to 314.824° : Max(128) VSIN + *0.748 VBB VCOS + Tan(q * 270°) COS− Output Min(0) 000 001 010 011 100 101 110 111 VSIN + *Tan (360° * q) Figure 2. SIN, COS Outputs VCOS + 0.748 Quadrant I SIN) * VSIN* ƫ ƪVVCOS) * VCOS* For q + 0.176°to 44.824° : VSIN + Tanq 0.748 VCOS + 0.748 VBB VBB For q + 45.176°to 89.824° : VSIN + 0.748 VBB VCOS + Tan(90° * q) VBB For q + 315.176° * 359.824° : MUX bits (D9−D7) q + Tan−1 0.748 000 0.748 VBB http://onsemi.com 5 VBB 0.748 VBB CS4192 VCOS+ 360/0° 0.748 VBB The 10 bits are shifted into the device’s shift register MSB first using an SPI compatible scheme. This method is shown in Figure 5. The CS must be high and remain high for SCLK to be enabled. Data on SI is shifted in on the rising edge of the synchronous clock signal. Data in the shift register changes at SO on the falling edge of SCLK. This arrangement allows the cascading of devices. SO is always enabled. Data shifts through without affecting the outputs until CS is brought low. At this time the internal DAC is updated and the outputs change accordingly. q IV I 270° VSIN− 0.748 VBB 90° VSIN+ 0.748 VBB II III CS 0.748 VBB CSSetup 180° VCOS− CSHold SCLK SI(Setup) Figure 3. Gauge Response SI(Hold) SI To drive the gauge’s pointer to a particular angle, the microcontroller sends a 10−bit digital word into the serial port. These 10 bits are divided as shown in Figure 4. MSB Gauge (360°) D9 SI(tpd) LSB D8 D7 D9−D7 select which octant D6 D5 D4 D3 D2 D1 SO(Rise, Fall) 10% − 90% SO Figure 5. Serial Data Timing Diagram D0 Divides a 45° octant into 128 equal parts to achieve a 0.35° resolution Code 0−12710 Figure 6 shows the power−up sequence for the CS4192. Note the IC requires a pulse on the Chip Select (CS) pin to clear the Status Fault (ST) after power up. OE must be high before the falling edge of CS to enable the output buffers. Figure 4. Definition of Serial Word However, from a software programmers viewpoint, a 360° circle is divided into 1024 equal parts of 0.35° each. Table 1 shows the data associated with the 45° divisions of the 360° driver. VCC CS Ideal Degrees Nominal Degrees 10 Bits SI VSIN (V) VCOS (V) 0 0 0.176 0.032 10.476 128 45 45.176 10.476 10.412 256 90 90.176 10.476 −0.032 384 135 135.176 10.412 −10.476 512 180 180.176 −0.032 −10.476 640 225 225.176 −10.476 −10.412 768 270 270.176 −10.476 0.032 896 315 315.176 −10.476 10.476 1023 359.65 359.826 −0.032 10.476 OE 10 Bits Registers set to zero Input Code (Decimal) Registers set to zero Table1. Nominal Output (VBB = 14 V) ST OUTPUTS ENABLED Figure 6. Power Up Sequence http://onsemi.com 6 OUTPUTS ENABLED CS4192 VBATT VREG CS8156 5.0 V 12 V ENABLE 360° Gauge CS4192 10 k Microcontroller COS+ COS− VBB VCC SIN− SIN+ ST CS SI SCLK SO OE Figure 7. Application Diagram http://onsemi.com 7 Next Driver CS4192 PACKAGE DIMENSIONS SOIC−16 WB DWF SUFFIX CASE 751G−03 ISSUE C A D 9 1 8 h X 45 _ H E 0.25 8X M B M 16 q 16X M T A S B S 14X e A1 L A 0.25 MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ B B NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. SEATING PLANE T C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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