12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface AD5444/AD5446 Data Sheet FEATURES GENERAL DESCRIPTION 12 MHz multiplying bandwidth INL of ± 0.5 LSB at 12 bits Pin-compatible 12-/14-bit current output DAC 2.5 V to 5.5 V supply operation 10-lead MSOP package ±10 V reference input 50 MHz serial interface 2.7 MSPS update rate Extended temperature range: −40°C to +125°C 4-quadrant multiplication Power-on reset with brownout detection 0.4 µA typical current consumption Guaranteed monotonic The AD5444/AD5446 1 are CMOS 12-bit and 14-bit, current output, digital-to-analog converters (DACs). Operating from a single 2.5 V to 5.5 V power supply, these devices are suited for battery-powered and other applications. As a result of the CMOS submicron manufacturing process, these parts offer excellent 4-quadrant multiplication characteristics of up to 12 MHz. These DACs use a double-buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. On power-up, the internal shift register and latches are filled with 0s, and the DAC output is at zero scale. The applied external reference input voltage (VREF) determines the full-scale output current. These parts can handle ±10 V inputs on the reference, despite operating from a single-supply power supply of 2.5 V to 5.5 V. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. The AD5444/AD5446 DACs are available in small 10-lead MSOP packages, which are pin-compatible with the AD5425/AD5426/AD5432/AD5443 family of DACs. APPLICATIONS Portable, battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming Automotive radar The EV-AD5443/46/53SDZ board is available for evaluating DAC performance. For more information, see the UG-327 evaluation board user guide. 1 US Patent Number 5,689,257. FUNCTIONAL BLOCK DIAGRAM VDD VREF R AD5444/ AD5446 12-BIT R-2R DAC RFB IOUT1 IOUT2 DAC REGISTER POWER-ON RESET CONTROL LOGIC AND INPUT SHIFT REGISTER GND SDO 04588-001 SYNC SCLK SDIN INPUT LATCH Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5444/AD5446 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Section................................................................................ 15 Applications ....................................................................................... 1 Circuit Operation ....................................................................... 15 General Description ......................................................................... 1 Single-Supply Applications ....................................................... 17 Functional Block Diagram .............................................................. 1 Adding Gain ................................................................................ 17 Revision History ............................................................................... 2 Divider or Programmable Gain Element ................................ 17 Specifications..................................................................................... 3 Amplifier Selection .................................................................... 18 Timing Characteristics ................................................................ 5 Reference Selection .................................................................... 18 Absolute Maximum Ratings............................................................ 6 Serial Interface ................................................................................ 20 ESD Caution .................................................................................. 6 Microprocessor Interfacing ....................................................... 21 Pin Configuration and Function Descriptions ............................. 7 PCB Layout and Power Supply Decoupling ................................ 23 Typical Performance Characteristics ............................................. 8 Overview of AD54xx and AD55xx Current Output Devices ... 24 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 25 General Description ....................................................................... 15 Ordering Guide .......................................................................... 25 REVISION HISTORY 6/13—Rev. D to Rev. E Changes to General Description Section ...................................... 1 Change to Figure 46 and Figure 47 .............................................. 21 Changes to Ordering Guide .......................................................... 25 4/12—Rev. C to Rev. D Changes to General Description Section ...................................... 1 Deleted Evaluation Board for the DAC Section ......................... 23 Deleted Power Supplies for the Evaluation Board Section ....... 23 Deleted Figure 54; Renumbered Sequentially ............................ 24 Deleted Figure 55 and Figure 56 ................................................... 25 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 Deleted Figure 57 ............................................................................ 26 4/07—Rev. B to Rev. C Changes to Table 9 .......................................................................... 19 Changes to Ordering Guide .......................................................... 28 Changes to Features.......................................................................... 1 Changes to General Description .................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 22 ...................................................................... 10 Changes to Figure 23 ...................................................................... 10 Changes to Table 9 .......................................................................... 19 Changes to Table 12 ........................................................................ 27 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 4/05—Rev. 0 to Rev. A Added AD5446 ................................................................... Universal Changes to Features ..........................................................................1 Changes to General Description .....................................................1 Changes to Specifications .................................................................3 Inserted Figure 7; Renumbered Sequentially.................................9 Inserted Figure 9; Renumbered Sequentially.................................9 Inserted Figure 13; Renumbered Sequentially ........................... 10 Changes to Figure 22...................................................................... 11 Changes to Figure 23...................................................................... 11 Changes to Serial Interface............................................................ 20 Changes to Figure 44...................................................................... 20 Changes to Figure 45...................................................................... 20 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 10/04—Revision 0: Initial Version Rev. E | Page 2 of 28 Data Sheet AD5444/AD5446 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE AD5444 Resolution Relative Accuracy Differential Nonlinearity Total Unadjusted Error (TUE) Gain Error AD5446 Resolution Relative Accuracy Differential Nonlinearity Total Unadjusted Error (TUE) Gain Error Gain Error Temperature Coefficient1 Output Leakage Current REFERENCE INPUT1 Reference Input Range VREF Input Resistance RFB Feedback Resistance Input Capacitance Zero-Scale Code Full-Scale Code DIGITAL INPUTS/OUTPUTS1 Input High Voltage, VIH Min Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance Max Unit Conditions 12 ±0.5 ±1 ±1 ±0.5 Bits LSB LSB LSB LSB Guaranteed monotonic 14 ±2 −1/+2 ±4 ±2.5 ±1 ±10 Bits LSB LSB Guaranteed monotonic LSB LSB ppm FSR/°C nA Data = 0x0000, TA = 25°C, IOUT1 nA Data = 0x0000, TA = −40°C to +125°C, IOUT1 ±10 9 9 11 11 V kΩ kΩ 18 18 22 22 pF pF ±2 7 7 2.0 1.7 Input Low Voltage, VIL Output High Voltage, VOH Typ 0.8 0.7 VDD − 1 VDD − 0.5 0.4 0.4 ±1 ±10 10 V V V V V V V V nA nA pF Rev. E | Page 3 of 28 Input resistance TC = −50 ppm/°C Input resistance TC = −50 ppm/°C VDD = 3.6 V to 5 V VDD = 2.5 V to 3.6 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V VDD = 4.5 V to 5 V, ISOURCE = 200 µA VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA VDD = 4.5 V to 5 V, ISINK = 200 µA VDD = 2.5 V to 3.6 V, ISINK = 200 µA TA = 25°C TA = −40°C to +125°C AD5444/AD5446 Parameter DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Multiplying Feedthrough Error Data Sheet Min Typ Max 12 Unit Conditions MHz VREF = ±3.5 V, DAC loaded with all 1s VREF = ±3.5 V, DAC loaded with all 0s 100 kHz 1 MHz 10 MHz VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 72 64 44 dB dB dB 110 40 33 40 30 ns ns ns ns ns nV-s Output Voltage Settling Time Measured to ±1 mV of FS Measured to ±4 mV of FS Measured to ±16 mV of FS Digital Delay 10%-to-90% Settling Time Digital-to-Analog Glitch Impulse Output Capacitance IOUT1 100 24 16 20 10 2 IOUT2 Digital Feedthrough Analog THD Digital THD 50 kHz fOUT 20 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) 50 kHz fOUT 20 kHz fOUT SFDR Performance (Narrow Band) 50 kHz fOUT 20 kHz fOUT Intermodulation Distortion POWER REQUIREMENTS Power Supply Range, VDD Supply Current, IDD 13 28 18 5 0.5 pF pF pF pF nV-s 83 dB 71 77 25 dB dB nV/√Hz 78 74 dB dB 87 85 79 dB dB dB DAC latches loaded with all 0s DAC latches loaded with all 1s DAC latches loaded with all 0s DAC latches loaded with all 1s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz Clock = 1 MHz, VREF = 3.5 V f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V V µA µA %/% TA = −40°C to +125°C, logic inputs = 0 V or VDD TA = 25°C, logic inputs = 0 V or VDD ∆VDD = ±5% @ 1 kHz Clock = 10 MHz, VREF = 3.5 V Clock = 1 MHz, VREF = 3.5 V 2.5 5.5 10 0.6 0.001 0.4 Power Supply Sensitivity1 1 Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 1 LSB change around major carry, VREF = 0 V Guaranteed by design and characterization; not subject to production test. Rev. E | Page 4 of 28 Data Sheet AD5444/AD5446 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 Update Rate 1 VDD = 4.5 V to 5.5 V 50 20 8 8 8 5 4.5 5 30 23 2.7 VDD = 2.5 V to 5.5 V 50 20 8 8 8 5 4.5 5 30 30 2.7 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min MSPS Conditions/Comments Maximum clock frequency. SCLK cycle time. SCLK high time. SCLK low time. SYNC falling edge to SCLK active edge setup time. Data setup time. Data hold time. SYNC rising edge to SCLK active edge setup time Minimum SYNC high time. SCLK active edge to SDO valid. Consists of cycle time, SYNC high time, data setup time and output voltage settling time. Guaranteed by design and characterization; not subject to production test. t1 SCLK t2 t4 t3 t7 SYNC t5 t6 DB15 SDIN 04588-002 t8 DB0 Figure 2. Standalone Timing Diagram t1 SCLK t2 t3 t7 t4 t8 SYNC t5 SDIN DB15 (N) t6 DB0 (N) DB15 (N + 1) DB0 (N + 1) DB15 (N) DB0 (N) SDO NOTES ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram Rev. E | Page 5 of 28 04588-003 t9 AD5444/AD5446 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Inputs and Outputs 1 Input Current (All Pins Except Supplies) Operating Temperature Range Extended (Y Version) Storage Temperature Range Junction Temperature 10-lead MSOP θJA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) 1 Rating −0.3 V to +7 V −12 V to +12 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V ±10 mA −40°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. 200µA −65°C to +150°C 150°C 206°C/W 300°C 235°C Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. TO OUTPUT PIN IOL VOH (MIN) +VOL (MAX) 2 CL 20pF 200µA IOH Figure 4. Load Circuit for SDO Timing Specifications ESD CAUTION Rev. E | Page 6 of 28 04588-004 TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Data Sheet AD5444/AD5446 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IOUT1 1 IOUT2 2 AD5444/ AD5446 10 RFB 9 VREF VDD TOP VIEW SCLK 4 (Not to Scale) 7 SDO SDIN 5 8 6 SYNC 04588-005 GND 3 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic IOUT1 IOUT2 GND SCLK 5 SDIN 6 SYNC 7 SDO 8 9 10 VDD VREF RFB Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low, data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising edge of SYNC. Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to data loaded to the shift register. Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input. DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output. Rev. E | Page 7 of 28 AD5444/AD5446 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 2.0 TA = 25°C VREF = 10V VDD = 5V 1.2 0.8 0.1 0.4 DNL (LSB) 0.2 0 –0.1 0 –0.4 –0.2 –0.8 –0.3 –1.2 04588-006 INL (LSB) 0.3 –0.4 –0.5 0 512 TA = 25°C VREF = 10V VDD = 5V 1.6 1024 1536 2048 CODE 2560 3072 3584 04588-077 0.4 –1.6 –2.0 0 4096 2048 6144 8192 10240 12288 14336 16384 9 10 9 10 CODE Figure 6. INL vs. Code (12-Bit DAC) Figure 9. DNL vs. Code (14-Bit DAC) 2.0 1.00 TA = 25°C VREF = 10V VDD = 5V 1.6 4096 TA = 25°C VDD = 5V AD5444 0.75 1.2 0.50 MAX INL 0.25 0.4 INL (LSB) INL (LSB) 0.8 0 –0.4 0 MIN INL –0.25 –0.8 –0.50 –1.2 –2.0 0 2048 4096 6144 8192 10240 12288 14336 04588-047 –0.75 04588-076 –1.6 –1.00 16384 2 3 4 CODE 5 6 7 8 REFERENCE VOLTAGE (V) Figure 10. INL vs. Reference Voltage Figure 7. INL vs. Code (14-Bit DAC) 1.0 2.0 TA = 25°C VREF = 10V VDD = 5V 0.8 0.6 TA = 25°C VDD = 5V AD5444 1.5 1.0 MAX DNL 0.5 DNL (LSB) 0.2 0 –0.2 0 MIN DNL –0.5 –0.4 –1.0 –0.6 –0.8 –1.0 0 512 1024 1536 2048 CODE 2560 3072 3584 04588-048 –1.5 04588-008 DNL (LSB) 0.4 –2.0 4096 2 Figure 8. DNL vs. Code (12-Bit DAC) 3 4 8 5 6 7 REFERENCE VOLTAGE (V) Figure 11. DNL vs. Reference Voltage Rev. E | Page 8 of 28 Data Sheet AD5444/AD5446 0.3 1.0 VREF = 10V TA = 25°C VREF = 10V VDD = 5V 0.8 0.6 0.2 GAIN ERROR (LSB) 0.2 0 –0.2 –0.4 –0.6 0.1 VDD = 3V VDD = 5V 0 –0.1 04588-013 –0.2 –0.8 –1.0 0 512 1024 1536 2048 CODE 2560 3072 3584 –0.3 –60 4096 2.0 –20 0 100 120 140 9 10 TA = 25°C VDD = 5V AD5444 1.5 1.0 GAIN ERROR (LSB) 0.8 0.4 0 –0.4 –0.8 0.5 0 –0.5 –1.0 04588-078 –1.2 –2.0 0 2048 4096 6144 8192 10240 12288 14336 –1.5 04588-051 –1.6 –2.0 16384 2 3 4 CODE Figure 13. TUE vs. Code (14-Bit DAC) 6 5 7 8 REFERENCE VOLTAGE (V) Figure 16. Gain Error vs. Reference Voltage 2.0 2.0 TA = 25°C VDD = 5V AD5444 1.5 IOUT1, VDD = 5V 1.6 IOUT1 LEAKAGE (nA) 1.0 MAX TUE 0.5 0 MIN TUE –0.5 IOUT1, VDD = 3V 1.2 0.8 –1.0 0.4 –1.5 –2.0 2 3 4 5 8 6 7 REFERENCE VOLTAGE (V) 9 0 –40 10 04588-017 04588-052 TUE (LSB) 20 40 60 80 TEMPERATURE (°C) 2.0 TA = 25°C VREF = 10V VDD = 5V 1.2 INL (LSB) –40 Figure 15. Gain Error vs. Temperature Figure 12. TUE vs. Code (12-Bit DAC) 1.6 04588-049 TUE (LSB) 0.4 –20 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 17. IOUT1 Leakage Current vs. Temperature Figure 14. TUE vs. Reference Voltage Rev. E | Page 9 of 28 120 AD5444/AD5446 Data Sheet 2.5 1.8 TA = 25°C TA = 25°C 1.6 VIH 1.5 VDD = 5V 1.0 0.5 0 0 3 2 INPUT VOLTAGE (V) 1 1.0 0.8 0.6 0.4 0 2.5 5 4 1.2 0.2 04588-018 VDD = 3V 3.0 Figure 18. Supply Current vs. Logic Input Voltage 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 10 ALL 1s ALL 0s 0.6 0 –10 GAIN (dB) VDD = 5V 0.3 TA = 25°C LOADING ZS TO FS ALL ON DB13 DB12 0.5 0.4 5.5 Figure 21. Threshold Voltage vs. Supply Voltage 0.7 –20 DB11 DB10 –30 DB9 DB8 –40 DB7 DB6 –50 DB5 0.2 VDD = 3V 0 –40 04588-019 0.1 –20 0 20 40 60 80 100 –60 DB4 DB3 –70 DB2 –80 10k 120 VDD = 5V VREF = ±3.5V CCOMP = 1.8pF AD8038 AMPLIFIER 100k 1M 10M 04588-083 SUPPLY CURRENT (µA) VIL 1.4 04588-053 THRESHOLD VOLTAGE (V) SUPPLY CURRENT (mA) 2.0 100M FREQUENCY (Hz) TEMPERATURE (°C) Figure 22. Reference Multiplying Bandwidth vs. Frequency and Code Figure 19. Supply Current vs. Temperature 0.6 6 TA = 25°C AD5444 LOADING 0101 0101 0101 5 0.4 4 3 GAIN (dB) 0 VDD = 5V 2 –0.2 –0.4 –0.6 VDD = 3V 0 1 10 100 1k 10k 100k 1M –1.0 –1.2 10k 10M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. Supply Current vs. Update Rate TA = 25°C VDD = 5V VREF = ±3.5V CCOMP = 1.8pF AD8038 AMPLIFIER 04588-084 –0.8 1 04588-055 SUPPLY CURRENT (mA) 0.2 Figure 23. Reference Multiplying Bandwidth vs. Frequency—All 1s Loaded Rev. E | Page 10 of 28 Data Sheet AD5444/AD5446 3 10 TA = 25°C VDD = 5V TA = 25°C VDD = 3V AD8038 AMPLIFIER 0 –10 0 –20 PSRR (dB) GAIN (dB) –30 –3 –40 FULL SCALE –50 –60 100k 1M ZERO SCALE –70 = ±2V, AD8038 C COMP = 1pF = ±2V, AD8038 C COMP = 1.5pF = ±15V, AD8038 C COMP = 1pF = ±15V, AD8038 C COMP = 1.5pF = ±15V, AD8038 C COMP = 1.8pF –80 –90 –100 100M 10M 04588-060 –9 10k VREF VREF VREF VREF VREF 04588-057 –6 1 10 100 1k 1M 10M –60 0.08 VDD = 3V 0x7FF TO 0x800 NRG = 1.794nV-s –65 –70 0.02 0 –0.04 –85 50 75 100 125 150 04588-058 VDD = 5V 0x800 TO 0x7FF NRG = 0.694nV-s –0.06 –75 –80 VDD = 5V 0x800 TO 0x7FF NRG = 0.694nV-s –0.02 TA = 25°C VDD = 5V VREF = ±3.5V 175 200 225 04588-061 0.04 TA = 25°C VREF = 0V AD8038 AMP CCOMP = 1.8pF THD + N (dB) VDD = 5V 0x7FF TO 0x800 NRG = 2.154nV-s 0.06 –90 100 250 1k 10k 100k FREQUENCY (Hz) TIME (ns) Figure 28. THD + Noise vs. Frequency Figure 25. Midscale Transition, VREF = 0 V 100 –1.66 VDD = 5V 0x7FF TO 0x800 NRG = 2.154nV-s –1.68 VDD = 3V 0x7FF TO 0x800 NRG = 1.794nV-s MCLK = 1MHz –1.72 –1.74 –1.76 VDD = 5V 0x800 TO 0x7FF NRG = 0.694nV-s VDD = 5V 0x800 TO 0x7FF NRG = 0.694nV-s –1.80 50 75 100 125 150 60 40 20 TA = 25°C VREF = 3.5V AD8038 AMP 04588-059 –1.78 MCLK = 200kHz MCLK = 500kHz 80 SFDR (dB) –1.70 TA = 25°C VREF = 3.5V AD8038 AMP CCOMP = 1.8pF 175 200 225 04588-062 OUTPUT VOLTAGE (V) 100k Figure 27. Power Supply Rejection Ratio vs. Frequency Figure 24. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor OUTPUT VOLTAGE (V) 10k FREQUENCY (Hz) FREQUENCY (Hz) 0 250 0 10 20 30 40 fOUT (kHz) TIME (ns) Figure 29. Wideband SFDR vs. fOUT Frequency Figure 26. Midscale Transition, VREF = 3.5 V Rev. E | Page 11 of 28 50 AD5444/AD5446 Data Sheet 0 0 TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMP –20 –20 –40 –40 –60 –60 –80 –100 –100 04588-063 –80 –120 0 100k 200k 300k 400k –120 10k 500k 04588-065 SFDR (dB) SFDR (dB) TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMP 15k FREQUENCY (Hz) Figure 30. Wideband SFDR , fOUT = 20 kHz, Clock = 1 MHz 0 0 30k TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMP –20 –40 –40 –60 –60 –80 –100 –100 04588-064 –80 –120 0 100k 200k 300k 400k –120 30k 500k FREQUENCY (Hz) 04588-066 SFDR (dB) SFDR (dB) 25k Figure 32. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMP –20 20k FREQUENCY (Hz) 40k 50k 60k 70k FREQUENCY (Hz) Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz Figure 33. Narrow-Band SFDR, fOUT = 50 kHz, Clock = 1 MHz Rev. E | Page 12 of 28 Data Sheet AD5444/AD5446 0 80 TA = 25°C VREF = 3.5V AD8038 AMP –10 TA = 25°C AD8038 AMP 70 IMD (dB) –30 –40 –50 –60 –70 60 FULL SCALE LOADED TO DAC 50 40 MIDSCALE LOADED TO DAC 30 20 04588-067 –80 –90 –100 10k 15k 20k 25k 30k 0 100 35k FREQUENCY (Hz) 0 TA = 25°C VREF = 3.5V AD8038 AMP –20 IMD (dB) –30 –40 –50 –60 –70 04588-068 –80 –90 –100 0 100k 200k 300k 1k 10k 100k FREQUENCY (Hz) Figure 34. Narrow-Band IMD, fOUT = 20 kHz and 25 kHz, Clock = 1 MHz –10 ZERO SCALE LOADED TO DAC 10 400k 500k FREQUENCY (Hz) Figure 35. Wideband IMD, fOUT = 20 kHz and 25 kHz, Clock = 1 MHz Rev. E | Page 13 of 28 Figure 36. Output Noise Spectral Density 04588-069 OUTPUT NOISE (nV/ Hz) –20 1M AD5444/AD5446 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity Relative accuracy or integral nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Digital Feedthrough When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled through the device to show up as noise on the IOUT1 and IOUT2 pins and, subsequently, into the following circuitry. This noise is digital feedthrough. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Multiplying Feedthrough Error Multiplying feedthrough error is due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 line, when all 0s are loaded to the DAC. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For this DAC, ideal maximum output is VREF − 1 LSB. Gain error of the DAC is adjustable to zero with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when the ladder is turned off. For the IOUT1 line, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time The amount of time it takes for the output to settle to a specified level for a full-scale input change. For this device, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from the SYNC rising edge to the full-scale output change. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either picoamps per second or nanovolts per second, depending upon whether the glitch is measured as a current or voltage signal. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics, such as second to fifth, are included. THD = 20 log V 2 2 + V3 2 + V 4 2 + V5 2 V1 Digital Intermodulation Distortion Second-order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones digitally generated by the DAC and the second-order products at 2fa − fb and 2fb − fa. Compliance Voltage Range The maximum range of (output) terminal voltage for which the device provides the specified characteristics. Spurious-Free Dynamic Range (SFDR) The usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate or fS/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Rev. E | Page 14 of 28 Data Sheet AD5444/AD5446 GENERAL DESCRIPTION CIRCUIT OPERATION DAC SECTION Unipolar Mode The AD5444/AD5446 are 12-bit and 14-bit current output DACs consisting of segmented (4 bits), inverting R– 2R ladder configurations. A simplified diagram for the 12-bit AD5444 is shown in Figure 37. R R R 2R 2R 2R 2R S1 S2 S3 S12 When an output amplifier is connected in unipolar mode, the output voltage is given by 2R R VOUT RFB IOUT1 IOUT2 where: 04464-029 DAC DATA LATCHES AND DRIVERS D is the fractional representation of the digital word loaded to the DAC: Figure 37. Simplified Ladder D = 0 to 4095 (12-bit AD5444) D = 0 to 16383 (14-bit AD5446) The feedback resistor (RFB) has a value of R. The value of R is typically 9 kΩ (7 kΩ minimum, 11 kΩ maximum). If IOUT1 is kept at the same potential as GND, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output (IOUT1) is code-dependent, producing various resistances and capacitances. The external amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node. n is the number of bits. Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. This DAC is designed to operate with either negative or positive reference voltages. The VDD power pin is used by the internal digital logic only to drive the on and off states of the DAC switches. The DAC is also designed to accommodate ac reference input signals in the range of −10 V to +10 V. With a fixed +10 V reference, the circuit shown in Figure 38 provides a unipolar 0 V to −10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Access is provided to the VREF, RFB, and both IOUT terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes. For example, the device provides unipolar output mode, 4-quadrant multiplication in bipolar mode, and single-supply mode of operation. Note that a matching switch is used in series with the internal RFB. Power must be applied to VDD to achieve continuity when measuring RFB. VDD VREF R1 Table 5 shows the relationship between digital code and expected output voltage for unipolar operation. Table 5. Unipolar Code Digital Input 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 Analog Output (V) −VREF (4095/4096) −VREF (2048/4096) = −VREF/2 −VREF (1/4096) −VREF (0/4096) = 0 R2 VDD VREF D V REF 2n AD5444/ AD5446 C1 RFB IOUT1 A1 IOUT2 VOUT = 0V TO –VREF SYNC SCLK SDIN AGND MICROCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. Figure 38. Unipolar Operation Rev. E | Page 15 of 28 04588-030 VREF Using a single op amp, the AD5444/AD5446 can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 38. AD5444/AD5446 Data Sheet Bipolar Operation Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. In some applications, it may be necessary to generate a full 4-quadrant multiplying operation, or a bipolar output swing. This can easily be accomplished by using another external amplifier and some external resistors, as shown in Figure 39. In this circuit, the second amplifier (A2) provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in a full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = −VREF) to midscale (VOUT − 0 V) to full scale (VOUT = +VREF) Table 6. Bipolar Code Digital Input 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 Analog Output (V) +VREF (2047/2048) 0 −VREF (2047/2048) −VREF (0/2048) Stability In the current-to-voltage (I-to-V) configuration, the IOUT1of the DAC and the inverting node of the op amp must be connected as closely as possible, and proper PCB layout techniques must be employed. Because every code change corresponds to a step function, gain peaking can occur if the op amp has limited GBP and excessive parasitic capacitance exists at the inverting node. This parasitic capacitance introduces a pole into the open-loop response that can cause ringing or instability in the closed-loop applications circuit. D VOUT = VREF × n −1 − VREF 2 where: D is the fractional representation of the digital word loaded to the DAC: D = 0 to 4095 (12-bit AD5444) D = 0 to 16383 (14-bit AD5446) An optional compensation capacitor (C1) can be added in parallel with RFB for stability, as shown in Figure 38 and Figure 39. Too small a value for C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation. n is the resolution of the DAC. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. R3 20kΩ VDD VREF ±10V VREF AD5444/ AD5446 R5 20kΩ C1 RFB IOUT1 A1 IOUT2 R4 10kΩ A2 VOUT = –VREF TO +VREF SYNC SCLK SDIN AGND MICROCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 39. Bipolar Operation (4-Quadrant Multiplication) Rev. E | Page 16 of 28 04588-031 VDD R1 R2 Data Sheet AD5444/AD5446 SINGLE-SUPPLY APPLICATIONS VDD = +5V ADR03 VOUT VIN Voltage Switching Mode of Operation VDD R1 RFB VIN R2 VDD VREF IOUT1 VOUT NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. 04588-032 GND Figure 40. Single-Supply Voltage Switching Mode Operation It is important to note that, with this configuration, VIN is limited to low voltages, because the switches in the DAC ladder do not have the same source-drain drive voltage. As a result, their on resistance differs, which degrades the integral linearity of the DAC. In addition, VIN must not go negative by more than 0.3 V, or an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of the multiplying capability of the DAC is lost. GND +5V VDD –2.5V C1 RFB IOUT1 VREF IOUT2 VOUT = 0V TO +2.5V GND –5V Figure 41. Positive Voltage Output with Minimum Components ADDING GAIN In applications in which the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier, or it can be achieved in a single stage. It is important to take into consideration the effect of the temperature coefficients of the DAC’s thin film resistors. Simply placing a resistor in series with the RFB resistor can cause mismatches in the temperature coefficients and result in larger gain temperature coefficient errors. Instead, increase the gain of the circuit by using the recommended configuration shown in Figure 42. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of greater than 1 are required. VDD VDD VIN C1 RFB IOUT1 R1 VREF IOUT2 VOUT R3 GND Positive Output Voltage R2 The output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor’s tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and −2.5 V, respectively, as shown in Figure 41. 04588-033 NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. GAIN = R2 + R3 R2 R2R3 R1 = R2 + R3 NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. 04588-034 Figure 40 shows the AD5444/AD5446 DACs operating in the voltage switching mode. The reference voltage (VIN) is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance). Therefore, an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance but rather one that varies with code, so the voltage input should be driven from a low impedance source. Figure 42. Increasing Gain of Current Output DAC DIVIDER OR PROGRAMMABLE GAIN ELEMENT Current-steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor, as shown in Figure 43, then the output voltage is inversely proportional to the digital input fraction, D. For D = 1 − 2−n, the output voltage is VOUT = −VIN/D = −VIN/(1 − 2−n) Rev. E | Page 17 of 28 AD5444/AD5446 Data Sheet The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent any significant errors in 12-bit applications. VDD VIN RFB VDD VREF IOUT1 GND Common-mode rejection of the op amp is important in voltage switching circuits because it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at 8-bit, 10-bit, and 12-bit resolutions. NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY. 04588-035 VOUT Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element As D is reduced, the output voltage increases. For small values of the digital fraction (D), it is important to ensure that the amplifier does not saturate and the required accuracy is met. For example, an 8-bit DAC driven with the binary code 0x10 (0001 0000), that is, 16 decimal, in the circuit of Figure 43, should cause the output voltage to be 16 × VIN. However, if the DAC has a linearity specification of ±0.5 LSB, then D can, in fact, have a weight in the range of 15.5/256 to 16.5/256, so the possible output voltage is in the range 15.5 VIN to 16.5 VIN. This is an error of 3%, even though the DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Because only a fraction (D) of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change, as follows: Output Error Voltage due to DAC Leakage = (Leakage × R)/D where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R equal to 10 kΩ, and a gain (1/D) of 16, the error voltage is 1.6 mV. AMPLIFIER SELECTION The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Provided that the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low input, capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which, in turn, requires an amplifier that can handle rail-to-rail signals. A large range of single-supply amplifiers is available from Analog Devices, Inc. (see Table 8 and Table 9 for suitable suggestions). REFERENCE SELECTION When selecting a reference for use with the AD5444/AD5446 current output DAC, pay attention to the output voltage temperature coefficient specification. This parameter affects not only the full-scale error but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0°C to 50°C dictates that the maximum system drift with temperature should be less than 78 ppm/°C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/°C. By choosing a precision reference with low output temperature coefficient, this error source can be minimized. Table 7 suggests some of the dc references available from Analog Devices that are suitable for use with this range of current output DACs. Rev. E | Page 18 of 28 Data Sheet AD5444/AD5446 Table 7. Suitable Analog Devices Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5 5 2.5 2.5 3 3 2.5 5 2.5 5 Initial Tolerance Accuracy (%) 0.05 0.05 0.06 0.06 0.10 0.10 0.10 0.10 0.04 0.04 0.16 0.10 Temperature Drift Coefficient (ppm/°C) 3 9 3 9 3 9 3 9 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.8 0.8 0.12 0.12 Output Noise (µV p-p) 20 20 10 10 6 6 10 10 3.5 8 5 8 Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23 Table 8. Suitable Analog Devices Precision Op Amps Part No. OP97 OP1177 AD8551 AD8603 AD8628 Supply Voltage (V) ±2 to ±20 ±2.5 to ±15 2.7 to 5 1.8 to 6 2.7 to 6 VOS (Max) (µV) 25 60 5 50 5 IB (Max) (nA) 0.1 2 0.05 0.001 0.1 0.1 Hz to 10 Hz Noise (µV p-p) 0.5 0.4 1 2.3 0.5 Supply Current (µA) 600 500 975 50 850 Package SOIC-8 MSOP, SOIC-8 MSOP, SOIC-8 TSOT TSOT, SOIC-8 Table 9. Suitable Analog Devices High Speed Op Amps Part No. AD8065 AD8021 AD8038 AD9631 Supply Voltage (V) 5 to 24 ±2.25 to ±12 3 to 12 ±3 to ±6 BW @ ACL (Typ) (MHz) 145 490 350 320 Slew Rate (Typ) (V/µs) 180 120 425 1300 Rev. E | Page 19 of 28 VOS (Max) (µV) 1500 1000 3000 10,000 IB (Max) (nA) 0.006 10500 750 7000 Package SOIC-8, SOT-23, MSOP SOIC-8, MSOP SOIC-8, SC70-5 SOIC-8 AD5444/AD5446 Data Sheet SERIAL INTERFACE The AD5444/AD5446 have an easy-to-use, 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. Data is written to the device in 16-bit words. This 16-bit word consists of two control bits, 12 data bits or 14 data bits, as shown in Figure 44 and Figure 45. The AD5446 uses all 14 bits of DAC data while AD5444 uses 12 bits and ignores the 2 LSBs. After the falling edge of the 16th SCLK pulse, bring SYNC high to transfer data from the input shift register to the DAC register. Daisy-Chain Mode Daisy-chain mode is the default power-on mode. To disable the daisy-chain function, write 01 to the control word. In daisychain mode, the internal gating on the SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of the SCLK (this is the default; use the control word to change the active edge) and is valid for the next device on the falling edge (default). By connecting this line to the SDIN input on the next device in the chain, a multidevice interface is constructed. Sixteen clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16 N, where N is the number of devices in the chain. Control Bit C1 and Control Bit C0 allow the user to load and update the new DAC code and to change the active clock edge. By default, the shift register clocks data on the falling edge, but this can be changed via the control bits. If changed, the DAC core is inoperative until the next data frame. A power cycle resets this back to the default condition. On-chip, power-on reset circuitry ensures the device powers on with zero scale loaded to the DAC register and the IOUT line. Table 10. DAC Control Bits C1 0 0 1 1 C0 0 1 0 1 Function Implemented Load and update (power-on default) Disable SDO No operation Clock data to shift register on rising edge When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data from being clocked into the shift register. A burst clock containing the exact number of clock cycles can be used, and SYNC can be taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device’s input register to the addressed DAC. SYNC Function SYNC is an edge-triggered input that acts as a frame synchronization signal. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC falling to the SCLK falling edge setup time, t4. To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. When the control bits = 10, the device is in no operation mode. This can be useful in daisy-chain applications where the user does not want to change the settings of a particular DAC in the chain. Simply write 10 to the control bits for that DAC and the following data bits are ignored. The SCLK and DIN input buffers are powered down on the rising edge of SYNC. DB15 (MSB) C0 DB0 (LSB) DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X 04588-037 C1 DATA BITS CONTROL BITS Figure 44. AD5444 12-Bit Input Shift Register Contents DB15 (MSB) C0 DB0 (LSB) DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DATA BITS CONTROL BITS Figure 45. AD5446 14-Bit Input Shift Register Contents Rev. E | Page 20 of 28 04588-038 C1 Data Sheet AD5444/AD5446 MICROPROCESSOR INTERFACING Table 11. SPORT Control Register Setup Microprocessor interfacing to the AD5444/AD5446 DAC is through a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5444/AD5446 requires a 16-bit word, with the default being data valid on the falling edge of SCLK, but this can be changed using the control bits in the data-word. Name TFSW INVTFS DTYPE ISCLK TFSR ITFS SLEN ADSP-21xx to AD5444/AD5446 Interface ADSP-BF5xx to AD5444/AD5446 Interface The ADSP-21xx family of DSPs is easily interfaced to the AD5444/AD5446 DAC without the need for extra glue logic. Figure 46 is an example of an SPI interface between the DAC and the ADSP-2191M. SCK of the DSP drives the serial clock line, SCLK. SYNC is driven from one of the port lines, in this case SPIxSEL. The ADSP-BF5xx family of processors has an SPI-compatible port that enables the processor to communicate with SPIcompatible devices. A serial interface between the ADSP-BF5xx and the AD5444/AD5446 DAC is shown in Figure 48. In this configuration, data is transferred through the MOSI (master output/slave input) pin. SYNC is driven by the SPI chip select pin, which is a reconfigured programmable flag pin. SCK SPIxSEL SDIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. SYNC SDIN ADSP-BF5xx* SCLK 04588-082 SCLK SCLK The ADSP-BF5xx processor incorporates channel synchronous serial ports (SPORT). A serial interface between the DAC and the DSP SPORT is shown in Figure 49. When the SPORT is enabled, initiate transmission by writing a word to the Tx register. The data is clocked out on each rising edge of the DSPs serial clock and clocked into the DAC input shift register on the falling edge of its SCLK. The DAC output is updated by using the transmit frame synchronization (TFS) line to provide a SYNC signal. AD5444/AD5446* DT SDIN SCK Figure 48. ADSP-BF5xx to AD5444/AD5446 Interface A serial interface between the DAC and DSP SPORT is shown in Figure 47. In this interface example, SPORT0 is used to transfer data to the DAC shift register. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP serial clock and clocked into the DAC input shift register on the falling edge of its SCLK. The update of the DAC output takes place on the rising edge of the SYNC signal. TFS SYNC MOSI *ADDITIONAL PINS OMITTED FOR CLARITY Figure 46. ADSP-2191M SPI to AD5444/AD5446 Interface ADSP-2101/ ADSP-2191M* AD5444/AD5446* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 47. ADSP-2101/ADSP-2191M to AD5444/AD5446 Interface AD5444/AD5446* TFS SYNC DT SDIN SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC interface expects a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns minimum. See the ADSP-21xx User Manual for information on clock and frame sync frequencies for the SPORT register. Table 11 shows the setup for the SPORT control register. Rev. E | Page 21 of 28 Figure 49. ADSP-BF5xx to AD5444/AD5446 Interface 04588-040 MOSI ADSP-BF5xx* SYNC 04588-074 SPIxSEL Description Alternate framing Active low frame signal Right-justify data Internal serial clock Frame every word Internal framing signal 16-bit data-word 04588-039 AD5444/ AD5446* ADSP-2191M* Setting 1 1 00 1 1 1 1111 AD5444/AD5446 Data Sheet MC68HC11* A serial interface between the DAC and the 80C51/80L51 is shown in Figure 50. TxD of the 80C51/80L51 drives SCLK of the DAC serial interface, while RxD drives the serial data line, SDIN. P1.1 is a bit-programmable pin on the serial port and is used to drive SYNC. When data is to be transmitted to the switch, P1.1 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data correctly to the DAC, P1.1 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result, no glue logic is required between the DAC and microcontroller interface. P1.1 is taken high following the completion of this cycle. The 80C51/80L51 provides the LSB of its SBUF register as the first bit in the data stream. The DAC input register requires its data with the MSB as the first bit received. The transmit routine should take this into account. AD5444/AD5446* PC7 SYNC SCK SCLK MOSI SDIN 04588-042 80C51/80L51 to AD5444/AD5446 Interface *ADDITIONAL PINS OMITTED FOR CLARITY Figure 51. MC68HC11 to AD5444/AD5446 Interface If the user wants to verify the data previously written to the input shift register, the SDO line can be connected to MISO of the MC68HC11, and, with SYNC low, the shift register clocks data out on the rising edges of SCLK. MICROWIRE to AD5444/AD5446 Interface Figure 52 shows an interface between the DAC and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the DAC input shift register on the rising edge of SK, which corresponds to the falling edge of the DAC SCLK. MICROWIRE* AD5444/AD5446* SCLK TxD SCLK SO SDIN RxD SDIN CS SYNC P1.1 SYNC *ADDITIONAL PINS OMITTED FOR CLARITY Figure 50. 80C51/80L51 to AD5444/AD5446 Interface *ADDITIONAL PINS OMITTED FOR CLARITY Figure 52. MICROWIRE to AD5444/AD5446 Interface PIC16C6x/7x to AD5444/AD5446 Interface MC68HC11 Interface to AD5444/AD5446 Interface Figure 51 is an example of a serial interface between the DAC and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR); see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the DAC interface, the MOSI output drives the serial data line (SDIN) of the AD5444/AD5446. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5444/AD5446, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the DAC, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is done by writing to the synchronous serial port control register (SSPCON); see the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is used to provide a SYNC signal and enable the serial port of the DAC. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. Figure 53 shows the connection diagram. PIC16C6x/7x* AD5444/AD5446* SCK/RC3 SCLK SDI/RC4 SDIN RA1 SYNC *ADDITIONAL PINS OMITTED FOR CLARITY Rev. E | Page 22 of 28 Figure 53. PIC16C6x/7x to AD5444/AD5446 Interface 04588-044 8051* 04588-043 SK 04588-041 AD5444/AD5446* Data Sheet AD5444/AD5446 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit boards on which the AD5444/AD5446 are mounted should be designed so the analog and digital sections are separated and confined to certain areas of the board. If the DACs are in systems in which multiple devices require a AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the devices. The DAC should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. A microstrip technique, by far the best, is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead-length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. Rev. E | Page 23 of 28 AD5444/AD5446 Data Sheet OVERVIEW OF AD54xx AND AD55xx CURRENT OUTPUT DEVICES Table 12. Part Number AD5424 AD5426 AD5428 AD5429 AD5450 AD5432 AD5433 AD5439 AD5440 AD5451 AD5443 AD5444 AD5415 AD5405 AD5445 AD5447 AD5449 AD5452 AD5446 AD5453 AD5553 AD5556 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 1 Resolution (Bits) 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 Number of DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2 INL (LSB) ±0.25 ±0.25 ±0.25 ±0.25 ±0.25 ±0.5 ±0.5 ±0.5 ±0.5 ±0.25 ±1 ±0.5 ±1 ±1 ±1 ±1 ±1 ±0.5 ±1 ±2 ±1 ±1 ±1 ±1 ±2 ±2 ±2 ±2 Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. E | Page 24 of 28 Package 1 RU-16, CP-20 RM-10 RU-20 RU-10 UJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 UJ-8 RM-10 RM-10 RU-24 CP-40 RU-20, CP-20 RU-24 RU-16 UJ-8, RM-8 RM-10 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38 Features 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 12 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 12 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 12 MHz BW, 50 MHz serial interface 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 12 MHz BW, 50 MHz serial 12 MHz BW, 50 MHz serial 12 MHz BW, 50 MHz serial 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width Data Sheet AD5444/AD5446 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 54. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5444YRM AD5444YRM-REEL AD5444YRM-REEL7 AD5444YRMZ AD5444YRMZ-REEL AD5444YRMZ-REEL7 AD5446YRM AD5446YRM-REEL AD5446YRM-REEL7 AD5446YRMZ AD5446YRMZ-RL7 EV-AD5443/46/53SDZ 1 Resolution (Bits) 12 12 12 12 12 12 14 14 14 14 14 INL (LSB) ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±2 ±2 ±2 ±2 ±2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. Rev. E | Page 25 of 28 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D27 D27 D27 D6X D6X D6X D28 D28 D28 D7Z D7Z AD5444/AD5446 Data Sheet NOTES Rev. E | Page 26 of 28 Data Sheet AD5444/AD5446 NOTES Rev. E | Page 27 of 28 AD5444/AD5446 Data Sheet NOTES ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04588-0-6/13(E) Rev. E | Page 28 of 28