MC14549B, MC14559B
Successive Approximation
Registers
The MC14549B and MC14559B successive approximation
registers are 8−bit registers providing all the digital control and storage
necessary for successive approximation analog−to−digital conversion
systems. These parts differ in only one control input. The Master Reset
(MR) on the MC14549B is required in the cascaded mode when more
than 8 bits are desired. The Feed Forward (FF) of the MC14559B is
used for register shortening where End−of−Conversion (EOC) is
required after less than eight cycles.
Applications for the MC14549B and MC14559B include
analog−to−digital conversion, with serial and parallel outputs.
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MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
Features
•
•
•
•
•
•
•
•
•
•
•
Totally Synchronous Operation
All Outputs Buffered
Single Supply Operation
Serial Output
Retriggerable
Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8−Bit D/A Converter
All Control Inputs Positive−Edge Triggered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving 2 Low−Power TTL Loads, 1 Low−Power Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
Chip Complexity: 488 FETs or 122 Equivalent Gates
Pb−Free Packages are Available*
16
MC145x9BCP
AWLYYWWG
1
1
16
1
SO−16W
DW SUFFIX
CASE 751G
MC145x9B
AWLYYWWG
1
x
A
WL
YY
WW
G
=
=
=
=
=
=
4 or 5
Assembly Location
Wafer Lot
Year
Work Week
Pb−Free Package
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
−0.5 to +18.0
V
Input Voltage Range, All Inputs
Vin
−0.5 to VDD + 0.5
V
Q4
1
16
VDD
DC Input Current per Pin
Iin
±10
mA
Q5
2
15
Q3
Power Dissipation per Package (Note 1)
PD
500
mW
Q6
3
14
Q2
Operating Temperature Range
TA
−55 to +125
°C
Q7
4
13
Q1
Storage Temperature Range
Tstg
−65 to +150
°C
Sout
5
12
Q0
D
6
11
EOC
C
7
10
*
VSS
8
9
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to
the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD).
PIN ASSIGNMENT
SC
*For MC14549B Pin 10 is MR input.
For MC14559B Pin 10 is FF input.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC14549B/D
MC14549B, MC14559B
TRUTH TABLES
MC14549B
MC14559B
SC SC(t−1) MR MR(t−1) Clock
Action
X
X
X
X
None
X
X
1
X
Reset
1
0
0
0
Start
Conversion
1
X
0
1
Start
Conversion
1
1
0
0
Continue
Conversion
0
X
0
X
Continue
Previous
Operation
X = Don’t Care
SC
SC(t−1) EOC Clock
X
1
X
0
X
0
X
1
0
0
0
0
0
X
1
1
X
1
Action
None
Start
Conversion
Continue
Conversion
Continue
Conversion
Retain
Conversion
Result
Start
Conversion
t−1 = State at Previous Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
25_C
VDD
Symbol
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.2
− 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
5.0
10
15
1.28
3.2
8.4
−
−
−
1.02
2.6
6.8
1.76
4.5
17.6
−
−
−
0.72
1.8
4.8
−
−
−
mAd
c
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAd
c
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
Input Voltage (Note 2)
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
Vdc
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
125_C
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Q Outputs
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Pin 5, 11 only
Input Current
IOL
Iin
mAd
c
Input Capacitance
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
(Clock = 0 V,
Other Inputs = VDD or 0 V, Iout = 0 mA)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package) (CL = 50 pF on all
outputs, all buffers switching)
IT = (0.8 mA/kHz) f + IDD
IT = (1.6 mA/kHz) f + IDD
IT = (2.4 mA/kHz) f + IDD
mAdc
2. Noise immunity specified for worst−case input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
3. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10−3 (CL = 50) VDDf where: IT is in mA (per package),
CL in pF, VDD in V, and f in kHz is input frequency.
4. The formulas given are for the typical characteristics only at 25_C.
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2
MC14549B, MC14559B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 177 ns
tPLH, tPHL = (0.5 ns/pF) CL + 130 ns
Clock to Sout
tPLH, tPHL = (1.7 ns/pF) CL + 665 ns
tPLH, tPHL = (0.66 ns/pF) CL + 277 ns
tPLH, tPHL = (0.5 ns/pF) CL + 195 ns
Clock to EOC
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
VDD
Min
Typ
Max
5.0
10
15
−
−
−
180
90
65
360
180
130
5.0
10
15
−
−
−
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
−
−
−
500
210
155
1000
420
310
5.0
10
15
−
−
750
310
220
1500
620
440
5.0
10
15
−
−
−
300
130
100
600
260
200
tsu
5.0
10
15
250
100
80
125
50
40
−
−
−
ns
tWH(cl)
5.0
10
15
700
270
200
350
135
100
−
−
−
ns
Pulse Width — D, SC, FF or MR
tWH
5.0
10
15
500
200
160
250
100
80
−
−
−
ns
Clock Rise and Fall Time
tTLH,
tTHL
5.0
10
15
−
−
−
ms
−
15
1.0
0.5
5.0
10
15
−
−
−
1.5
3.0
4.0
0.8
1.5
2.0
MHz
SC, D, FF or MR Setup Time
Clock Pulse Width
Clock Pulse Frequency
fcl
5. The formulas given are for the typical characteristics only.
ORDERING INFORMATION
Device
Package
MC14549BCP
PDIP−16
MC14549BCPG
PDIP−16
(Pb−Free)
MC14549BDWR2
SOIC−16
MC14549BDWR2G
SOIC−16
(Pb−Free)
MC14559BCP
PDIP−16
MC14559BCPG
PDIP−16
(Pb−Free)
MC14559BDWR2
SOIC−16
MC14559BDWR2G
SOIC−16
(Pb−Free)
Shipping †
25 / Rail
1000 / Tape & Reel
25 / Rail
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC14549B, MC14559B
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VDD
Q7
PROGRAMMABLE
PULSE
GENERATOR
C
Q6
Q5
SC
Q4
Q3
FF(MR)
Q2
Q1
CL
CL
CL
CL
CL
CL
Q0
EOC
D
CL
CL
Sout
CL
CL
VSS
1
fcl
C
50%
SC
D
tWH(cl)
tsu
50%
tsu
50%
tPLH
Q7
50%
90%
tTLH
Sout
tWH(D)
tsu
tPHL
10%
tTHL
50%
tPLH
90%
10%
tTLH
NOTE: Pin 10 = VSS
TIMING DIAGRAM
CLOCK
SC
D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
EOC
Sout
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH
— Don’t care condition
INH — Indicates Serial Out is inhibited low.
* — Q8 is ninth−bit of serial information available from 8−bit register.
NOTE: Pin 10 = VSS
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4
MC14549B, MC14559B
OPERATING CHARACTERISTICS
Both the MC14549B and MC14559B can be operated in
either the “free run” or “strobed operation” mode for
conversion schemes with any number of bits. Reliable
cascading and/or recirculating operation can be achieved if
the End of Convert (EOC) output is used as the controlling
function, since with EOC = 0 (and with SC = 1 for
MC14549B but either 1 or 0 for MC14559B) no stable state
exists under continual clocked operation. The MC14559B
will automatically recirculate after EOC = 1 during externally
strobed operation, provided SC = 1.
All data and control inputs for these devices are triggered
into the circuit on the positive edge of the clock pulse.
Operation of the various terminals is as follows:
C = Clock — A positive−going transition of the Clock is
required for data on any input to be strobed into the circuit.
SC = Start Convert — A conversion sequence is initiated
on the positive−going transition of the SC input on
succeeding clock cycles.
D = Data in — Data on this input (usually from a
comparator in A/D applications) is also entered into the
circuit on a positive−going transition of the clock. This input
is Schmitt triggered and synchronized to allow fast response
and guaranteed quality of serial and parallel data.
MR = Master Reset (MC14549B Only) — Resets all
output to 0 on positive−going transitions of the clock. If
removed while SC = 0, the circuit will remain reset until
SC = 1. This allows easy cascading of circuits.
FF = Feed Forward (MC14559B Only) — Provides
register shortening by removing unwanted bits from a system.
For operation with less than 8 bits, tie the output following
the least significant bit of the circuit to EOC. E.g., for a 6−bit
FROM A/D
COMPARATOR
C
SC
D
conversion, tie Q1 to FF; the part will respond as shown in the
timing diagram less two bit times. Not that Q1 and Q0 will
still operate and must be disregarded.
For 8−bit operation, FF is tied to VSS.
For applications with more than 8 but less than 16 bits, use
the basic connections shown in Figure 1. The FF input of the
MC14559B is used to shorten the setup. Tying FF directly to
the least significant bit used in the MC14559B allows EOC
to provide the cascading signal, and results in smooth
transition of serial information from the MC14559B to the
MC14549B. The Serial Out (Sout) inhibit structure of the
MC14559B remains inactive one cycle after EOC goes high,
while Sout of the MC14549B remains inhibited until the
second clock cycle of its operation.
Qn = Data Outputs — After a conversion is initiated the
Q’s on succeeding cycles go high and are then conditionally
reset dependent upon the state of the D input. Once
conditionally reset they remain in the proper state until the
circuit is either reset or reinitiated.
EOC = End of Convert — This output goes high on the
negative−going transition of the clock following FF = 1 (for
the MC14559B) or the conditional reset of Q0. This allows
settling of the digital circuitry prior to the End of Conversion
indication. Therefore either level or edge triggering can
indicate complete conversion.
Sout = Serial Out — Transmits conversion in serial
fashion. Serial data occurs during the clock period when the
corresponding parallel data bit is conditionally reset. Serial
Out is inhibited on the initial period of a cycle, when the
circuit is reset, and on the second cycle after EOC goes high.
This provides efficient operation when cascaded.
EXTERNAL
CLOCK
Sout
MC14559B
* FF
Q7 Q6 Q5 Q4 •• Q0 EOC
1/4 MC14001
D
C
SC
Sout
MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
**
MSB
{
NC
TO D/A AND PARALLEL DATA
LSB
TO D/A AND
PARALLEL DATA
FREE RUN MODE
EXTERNAL STROBE
* FF allows EOC to activate as if in 4−stage register.
** Cascading using EOC guaranteed; no stable unfunctional state.
†Completion of conversion automatically re−initiates cycle in free run mode.
Figure 1. 12−Bit Conversion Scheme
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5
SERIAL OUT
(CONTINUAL
UPDATE EVERY
13 CLOCK CYCLES)
MC14549B, MC14559B
TYPICAL APPLICATIONS
Externally Controlled 6−Bit ADC (Figure 2)
•
•
•
•
Continuously Cycling 12−Bit ADC (Figure 4)
Several features are shown in this application:
Shortening of the register to six bits by feeding the
seventh output bit into the FF input.
Continuous conversion, if a continuous signal is applied
to SC.
Externally controlled updating (the start pulse must be
shorter than the conversion cycle).
The EOC output indicating that the parallel data are
valid and that the serial output is complete.
Because each successive approximation register (SAR)
has a capability of handling only an eight−bit word, two
must be cascaded to make an ADC with more than eight bits.
When it is necessary to cascade two SAR’s, the second
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling,
because during switch−on or due to outside influences, the
first stage has entered a reset state, the entire ADC will
remain in a stable non−functional condition.
This 12−bit ADC is continuously recycling. The serial as
well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of the
12−bit conversion cycle, the end of the serial output word,
and the validity of the parallel data output.
Continuously Cycling 8−Bit ADC (Figure 3)
This ADC is running continuously because the EOC
signal is fed back to the SC input, immediately initiating a
new cycle on the next clock pulse.
SC
C
Sout
MC14559B
Q7 Q6
Q5
Q4
Q3
Q2
Q1
Q0
FF EOC
TO DAC
Figure 2. Externally Controlled 6−Bit ADC
SC
C
Sout
MC14559B
Q7 Q6
Q5
Q4
Q3
Q2
Q1
Q0
FF EOC
TO DAC
Figure 3. Continuously Cycling 8−Bit ADC
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6
MC14549B, MC14559B
Sout
C
SC
Sout
C
SC
MC14559B
Sout
MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
TO DAC
EOC
Figure 4. Continuously Cycling 12−Bit ADC
Externally Controlled 12−Bit ADC (Figure 5)
Additional Motorola Parts for Successive
Approximation ADC
In this circuit the external pulse starts the first SAR and
simultaneously resets the cascaded second SAR. When Q4 of
the first SAR goes high, the second SAR starts conversion,
and the first one stops conversion. EOC indicates that the
parallel data are valid and that the serial output is complete.
Updating the output data is started with every external control
pulse.
C
SC
Monolithic digital−to−analog converters — The
MC1408/1508 converter has eight−bit resolution and is
available with 6, 7, and 8−bit accuracy. The
amplifier−comparator block — The MC1407/1507
contains a high speed operational amplifier and a high speed
comparator with adjustable window.
With these two linear parts it is possible to construct
SA−ADCs with an accuracy of up to eight bits, using as the
register one MC14549B or one MC14559B. An additional
CMOS block will be necessary to generate the clock
frequency.
Additional information on successive approximation ADC
is found in Motorola Application Note AN−716.
Sout
SC
MC14559B
C
MC14549B
Sout
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
TO DAC
EOC
Figure 5. Externally Controlled 12−Bit ADC
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7
Sout
MC14549B, MC14559B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
SEATING
PLANE
K
H
D
M
J
G
16 PL
0.25 (0.010)
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16 WB
CASE 751G−03
ISSUE C
A
D
9
h X 45 _
E
0.25
1
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
8
16X
M
14X
e
T A
S
B
S
L
A
0.25
B
B
A1
H
8X
M
B
M
16
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
SEATING
PLANE
T
C
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8
MC14549B, MC14559B
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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