ONSEMI MC74HC03ADTR2G

MC74HC03A
Quad 2−Input NAND Gate
with Open−Drain Outputs
High−Performance Silicon−Gate CMOS
The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a high−performance
MOS N−Channel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wired−AND applications. Having
the output characteristic curves given in this data sheet, this device can
be used as an LED driver or in any other application that only requires
a sinking current.
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MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
14
1
Features
1
• Output Drive Capability: 10 LSTTL Loads With Suitable Pullup
•
•
•
•
•
•
•
Resistor
Outputs Directly Interface to CMOS, NMOS and TTL
High Noise Immunity Characteristic of CMOS Devices
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1mA
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 28 FETs or 7 Equivalent Gates
Pb−Free Packages are Available
14
SOIC−14
D SUFFIX
CASE 751A
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
1
B
14
HC
03
ALYWG
G
1
VCC
A
HC03AG
AWLYWW
1
LOGIC DIAGRAM
PIN 14 = VCC
PIN 7 = GND
* Denotes open−drain outputs
MC74HC03AN
AWLYYWWG
OUTPUT
PROTECTION
DIODE
3,6,8,11
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
Y*
1,4,9,12
FUNCTION TABLE
2,5,10,13
Inputs
Pinout: 14−Lead Packages (Top View)
VCC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
Output
A
B
Y
L
L
H
H
L
H
L
H
Z
Z
Z
L
Z = High Impedance
1
2
3
4
5
6
7
ORDERING INFORMATION
A1
B1
Y1
A2
B2
Y2
GND
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 10
1
Publication Order Number:
MC74HC03A/D
MC74HC03A
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ÎÎÎÎ
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ÎÎÎÎÎÎÎÎ
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ÎÎ
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DESIGN GUIDE
Criteria
Value
Unit
Internal Gate Count*
7.0
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
0.0075
pJ
Speed Power Product
*Equivalent to a two−input NAND gate
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2
MC74HC03A
ORDERING INFORMATION
Device
Package
MC74HC03AN
PDIP−14
MC74HC03ANG
PDIP−14
(Pb−Free)
MC74HC03AD
SOIC−14
MC74HC03ADG
SOIC−14
(Pb−Free)
MC74HC03ADR2
SOIC−14
MC74HC03ADR2G
SOIC−14
(Pb−Free)
MC74HC03ADTR2
TSSOP−14*
MC74HC03ADTR2G
TSSOP−14*
MC74HC03AFEL
SOEIAJ−14
MC74HC03AFELG
SOEIAJ−14
(Pb−Free)
Shipping†
25 Units/Rail
55 Units/Rail
2500/Tape & Reel
2000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74HC03A
DC CHARACTERISTICS (Voltages Referenced to GND)
Condition
VCC
V
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input Voltage
Vout = 0.1V or VCC −0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOL
Maximum Low−Level Output
Voltage
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
6.0
1.0
10
40
mA
IOZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±0.5
±5.0
±10
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
−55 to 25°C
≤85°C
≤125°C
Unit
tPLZ,
tPZL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
120
45
24
20
150
60
30
26
180
75
36
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
8.0
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no−load dynamic power consumption: PD = CPD VCC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2f
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4
pF
+ ICC VCC . For load considerations, see Chapter 2 of the
MC74HC03A
VCC
tf
tr
INPUT A
Rpd
OUTPUT
DEVICE
UNDER
TEST
GND
tPZL
tPLZ
HIGH
IMPEDANCE
90%
50%
10%
OUTPUT Y
1kW
VCC
90%
50%
10%
10%
TEST
POINT
CL*
VOL
tTHL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
25
VCC=5V
TYPICAL
T=25°C
I D, SINK CURRENT (mA)
20
T=25°C
15
T=85°C
10
T=125°C
EXPECTED MINIMUM*
5
0
0
1
2
3
4
VO, OUTPUT VOLTAGE (VOLTS)
5
*The expected minimum curves are not guarantees, but are design aids.
Figure 3. Open−Drain Output Characteristics
VCC
+
VR
−
+
VF
−
VCC
PULLUP
RESISTOR
A1
B1
A2
B2
An
Bn
1/4
HC03
Y1
1/4
HC03
Y2
1/4
HC03
OUTPUT
LED1
1/4
HC03
DESIGN EXAMPLE
CONDITIONS: ID^10mA
TYPICAL CURVE, at ID=10mA,
VDS^0.4V
LED2
LED
ENABLE
1/4
HC03
VCC
V * VF * VO
NR + CC
ID
Yn
+ 5V * 1.7V * 0.4V
10mA
OUTPUT = Y1 • Y2 • . . . • Yn
= A1B1 • A2B2 • . . . • AnBn
+ 290W
USE R = 270W
Figure 4. Wired AND
Figure 5. LED Driver With Blanking
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5
MC74HC03A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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6
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC74HC03A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74HC03A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K
A
−V−
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
MC74HC03A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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For additional information, please contact your local
Sales Representative
MC74HC03A/D