74HC14 Hex Schmitt−Trigger Inverter High−Performance Silicon−Gate CMOS The 74HC14 is identical in pinout to the LS14, LS04 and the HC04. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC14 is useful to “square up” slow input rise and fall times. Due to hysteresis voltage of the Schmitt trigger, the HC14 finds applications in noisy environments. http://onsemi.com MARKING DIAGRAMS Features • • • • • • • • • 14 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 60 FETs or 15 Equivalent Gates These are Pb−Free Devices SOIC−14 D SUFFIX CASE 751A 14 1 HC14G AWLYWW 1 14 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 HC 14 ALYW G G HC14 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 1 1 Publication Order Number: 74HC14/D 74HC14 Pinout: 14−Lead Packages (Top View) VCC A6 Y6 A5 Y5 A4 Y4 14 13 12 11 10 9 8 LOGIC DIAGRAM A1 A2 A3 1 2 3 4 5 6 7 A1 Y1 A2 Y2 A3 Y3 GND A4 FUNCTION TABLE Outputs A Y L H H L 2 3 4 5 6 9 8 11 10 13 12 Y1 Y2 Y3 Y=A A5 Inputs 1 A6 Y4 Pin 14 = VCC Pin 7 = GND Y5 Y6 ORDERING INFORMATION Package Shipping † SOIC−14 (Pb−Free) 2500 / Tape & Reel TSSOP−14* 2500 / Tape & Reel Device 74HC14DR2G 74HC14DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 74HC14 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature Range – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 No Limit* No Limit* No Limit* ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V *When Vin = 50% VCC, ICC > 1mA http://onsemi.com 3 74HC14 DC CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC (V) −55 to 25°C ≤85°C ≤125°C Unit Vout = 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 1.50 2.15 3.15 4.20 1.50 2.15 3.15 4.20 1.50 2.15 3.15 4.20 V Minimum Positive−Going Input Threshold Voltage (Figure 3) Vout = 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 1.0 1.5 2.3 3.0 0.95 1.45 2.25 2.95 0.95 1.45 2.25 2.95 V VT− max Maximum Negative−Going Input Threshold Voltage (Figure 3) Vout = VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 0.9 1.4 2.0 2.6 0.95 1.45 2.05 2.65 0.95 1.45 2.05 2.65 V VT− min Minimum Negative−Going Input Threshold Voltage (Figure 3) Vout = VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 0.3 0.5 0.9 1.2 0.3 0.5 0.9 1.2 0.3 0.5 0.9 1.2 V VHmax Note 2 Maximum Hysteresis Voltage (Figure 3) Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 1.20 1.65 2.25 3.00 1.20 1.65 2.25 3.00 1.20 1.65 2.25 3.00 V VHmin Note 2 Minimum Hysteresis Voltage (Figure 3) Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 0.20 0.25 0.40 0.50 0.20 0.25 0.40 0.50 0.20 0.25 0.40 0.50 V VOH Minimum High−Level Output Voltage Vin ≤ VT− min |Iout| ≤ 20mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Symbol Parameter VT+ max Maximum Positive−Going Input Threshold Voltage (Figure 3) VT+ min Condition Vin ≤ VT− min VOL Maximum Low−Level Output Voltage |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin ≥ VT+ max |Iout| ≤ 20mA Vin ≥ VT+ max |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0mA 6.0 2.0 20 40 mA 1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. VHmin > (VT+ min) − (VT− max); VHmax = (VT+ max) − (VT− min). http://onsemi.com 4 74HC14 AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns) Symbol Parameter Guaranteed Limit VCC (V) −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns 10 10 10 pF Cin Maximum Input Capacitance NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD 22 Power Dissipation Capacitance (Per Inverter)* pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). tf INPUT A tr VCC 90% 50% 10% GND tPLH tPHL 90% OUTPUT Y 50% 10% tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST C L* *Includes all probe and jig capacitance Figure 2. Test Circuit http://onsemi.com 5 VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS 74HC14 4 3 (VT+) VHtyp 2 (VT−) 1 2 3 4 5 VCC, POWER SUPPLY VOLTAGE (VOLTS) 6 VHtyp = (VT+ typ) − (VT− typ) Figure 3. Typical Input Threshold, VT+, VT− versus Power Supply Voltage A Y (a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times VH Vin (b) A Schmitt−Trigger Offers Maximum Noise Immunity VCC VH VT+ VT− Vin VCC VT+ VT− GND GND VOH VOH Vout Vout VOL VOL Figure 4. Typical Schmitt−Trigger Applications http://onsemi.com 6 74HC14 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 74HC14 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K A −V− K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 74HC14 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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