NID9N05CL Power MOSFET 9.0 A, 52 V, N−Channel, Logic Level, Clamped MOSFET w/ESD Protection in a DPAK Package http://onsemi.com Benefits • High Energy Capability for Inductive Loads • Low Switching Noise Generation VDSS (Clamped) RDS(ON) TYP ID MAX (Limited) 52 V 90 mW 9.0 A Features • • • • • • Drain (Pins 2, 4) Diode Clamp Between Gate and Source ESD Protection − HBM 5000 V Active Over−Voltage Gate to Drain Clamp Scalable to Lower or Higher RDS(on) Internal Series Gate Resistance Pb−Free Packages are Available Gate (Pin 1) RG MPWR Overvoltage Protection ESD Protection Applications • Automotive and Industrial Markets: Solenoid Drivers, Lamp Drivers, Small Motor Drivers Source (Pin 3) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage Internally Clamped VDSS 52−59 V Gate−to−Source Voltage − Continuous VGS ±15 V ID A Drain Current − Continuous @ TA = 25°C Drain Current − Single Pulse (tp = 10 ms) IDM 9.0 35 Total Power Dissipation @ TA = 25°C PD 28.8 W TJ, Tstg −55 to 175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 125°C (VDD = 50 V, ID(pk) = 1.5 A, VGS = 10 V, RG = 25 W) EAS 160 mJ Thermal Resistance, Junction−to−Case Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) RqJC RqJA RqJA 5.2 72 100 °C/W TL 260 °C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds MARKING DIAGRAM 1 2 DPAK CASE 369C STYLE 2 Y WW D9N05CL G 3 = Year = Work Week = Device Code = Pb−Free Package YWW D9N 05CLG 1 2 3 4 4 = Gate = Drain = Source = Drain ORDERING INFORMATION Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in2). 2. When surface mounted to a FR4 board using minimum recommended pad size, (Cu area 0.412 in2). Device NID9N05CLT4 NID9N05CLT4G NID9N05CL NID9N05CLG Package Shipping† DPAK 2500/Tape & Reel DPAK (Pb−Free) 2500/Tape & Reel DPAK 75 Units/Rail DPAK (Pb−Free) 75 Units/Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 7 1 Publication Order Number: NID9N05CL/D NID9N05CL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Min Typ Max Unit 52 50.8 − 55 54 −10 59 59.5 − V V mV/°C − − − − 10 25 − − − ±22 ±10 − 1.3 − 1.75 −4.5 2.5 − − − − 70 67 153 175 − 90 95 181 364 1210 − − gFS − 24 − Mhos Ciss − 155 250 pF Coss − 60 100 Crss − 25 40 Input Capacitance Ciss − 175 − Output Capacitance Coss − 70 − Crss − 30 − Characteristic OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 V, ID = 1.0 mA, TJ = 25°C) (VGS = 0 V, ID = 1.0 mA, TJ = −40°C to 125°C) Temperature Coefficient (Negative) Zero Gate Voltage Drain Current (VDS = 40 V, VGS = 0 V) (VDS = 40 V, VGS = 0 V, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±8 V, VDS = 0 V) (VGS = ±14 V, VDS = 0 V) IGSS mA mA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 100 mA) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.0 V, ID = 1.5 A) (VGS = 3.5 V, ID = 0.6 A) (VGS = 3.0 V, ID = 0.2 A) (VGS = 12 V, ID = 9.0 A) (VGS = 12 V, ID = 12 A) RDS(on) Forward Transconductance (Note 3) (VDS = 15 V, ID = 9.0 A) V mV/°C mW DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 40 V, VGS = 0 V, f = 10 kHz) Transfer Capacitance (VDS = 25 V, VGS = 0 V, f = 10 kHz) Transfer Capacitance 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 pF NID9N05CL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit td(on) − 130 200 ns tr − 500 750 td(off) − 1300 2000 tf − 1150 1850 td(on) − 200 − tr − 500 − td(off) − 2500 − tf − 1800 − td(on) − 120 − tr − 275 − td(off) − 1600 − SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 V, VDD = 40 V, ID = 9.0 A, RG = 9.0 W) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 V, VDD = 15 V, ID = 1.5 A, RG = 2 kW) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 V, VDD = 15 V, ID = 1.5 A, RG = 50 W) Fall Time ns ns tf − 1100 − QT − 4.5 7.0 Q1 − 1.2 − Q2 − 2.7 − QT − 3.6 − Q1 − 1.0 − Q2 − 2.0 − VSD − − − 0.86 0.845 0.725 1.2 − − V trr − 700 − ns ta − 200 − tb − 500 − QRR − 6.5 − mC ESD 5000 − − V 500 − − Gate Charge (VGS = 4.5 V, VDS = 40 V, ID = 9.0 A) (Note 3) Gate Charge (VGS = 4.5 V, VDS = 15 V, ID = 1.5 A) (Note 3) nC nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 4.5 A, VGS = 0 V) (Note 3) (IS = 4.0 A, VGS = 0 V) (IS = 4.5 A, VGS = 0 V, TJ = 125°C) Reverse Recovery Time (IS = 4.5 A, VGS = 0 V, dIs/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge ESD CHARACTERISTICS Electro−Static Discharge Capability Human Body Model (HBM) Machine Model (MM) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NID9N05CL 18 18 TJ = 25°C 8V 14 6.5 V ID, DRAIN CURRENT (AMPS) 16 ID, DRAIN CURRENT (AMPS) 6V VGS = 10 V 5V 12 4.6 V 10 4.2 V 4V 3.8 V 8 6 3.2 V 4 3.4 V 2 1 2 3 4 5 6 7 TJ = 100°C 10 8 6 4 VDS ≥ 10 V 1 8 2 4 3 7 6 5 8 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.5 ID = 4.5 A TJ = 25°C 0.4 0.3 0.2 0.1 2 4 6 8 10 12 9 0.4 0.35 TJ = 25°C VGS = 4 V 0.3 0.25 0.2 0.15 VGS = 12 V 0.1 0.05 0 0 2 4 6 10 8 12 14 16 18 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.5 1,000,000 ID = 9 A VGS = 12 V VGS = 0 V 100,000 2 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C 12 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 14 2 2.8 V 0 0 TJ = −55°C 16 1.5 TJ = 150°C 10,000 1 0.5 −50 −25 TJ = 100°C 1000 100 0 25 50 75 100 125 150 175 20 25 30 35 40 45 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 50 NID9N05CL 500 C, CAPACITANCE (pF) Frequency = 10 kHz TJ = 25°C VGS = 0 V 400 300 200 Ciss Coss 100 Crss 0 10 0 20 30 40 50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 50 QT 4 40 VGS Qgs 3 Qgd 30 20 2 ID = 9 A TJ = 25°C VDS 1 10 0 0 0 1 2 3 4 Qg, TOTAL GATE CHARGE (nC) 5 10,000 VDD = 40 V ID = 9 A VGS = 10 V t, TIME (ns) 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) td(off) 1000 tf tr td(on) 100 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 10 IS, SOURCE CURRENT (AMPS) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation VGS = 0 V TJ = 25°C 8 6 4 2 0 0.4 0.6 0.8 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.2 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 100 NID9N05CL SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. I D, DRAIN CURRENT (AMPS) 100 VGS = 12 V SINGLE PULSE TC = 25°C 100 ms 10 1 ms 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 ms 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 Figure 11. Maximum Rated Forward Biased Safe Operating Area 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) Figure 12. Thermal Response http://onsemi.com 6 0.1 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1 10 NID9N05CL PACKAGE DIMENSIONS DPAK CASE 369C ISSUE O C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE −T− E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 7 For additional information, please contact your local Sales Representative. NID9N05CL/D