NTD85N02R Power MOSFET 85 Amps, 24 Volts N−Channel DPAK Features • • • • • http://onsemi.com Pb−Free Packages are Available Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge VDSS RDS(ON) TYP ID MAX 24 V 4.8 m 85 A N−Channel D MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Value Unit Drain−to−Source Voltage VDSS 24 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance − Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current Continuous @ TC = 25°C, Limited by Package Continuous @ TA = 25°C, Limited by Wires Single Pulse (tp ≤ 10 s) RJC PD 1.6 78.1 °C/W W ID ID IDM 85 32 96 A A A Thermal Resistance, Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA 52 °C/W PD ID 2.4 16 W A Thermal Resistance, Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA 100 °C/W PD ID 1.25 12 W A Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C EAS 85 mJ Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 10 Vdc, IL = 13 Apk, L = 1 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds September, 2004 − Rev. 6 S 4 4 3 DPAK CASE 369C STYLE2 2 3 1 3 DPAK−3 CASE 369D STYLE 2 4 °C 260 2 MARKING DIAGRAM & PIN ASSIGNMENTS 1 TL 1 1 2 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 inch pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2004 G YWW 85 N02 4 1 Gate 2 Drain 3 Source 4 Drain Y = Year WW = Work Week 85N02R = Specific Device Code YWW 85 N02 Symbol Parameter 1 2 3 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Publication Order Number: NTD85N02R/D NTD85N02R ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics Symbol Min Typ Max 24 − 28 20.5 − − − − − − 1.5 10 − − ±100 1.0 − 1.5 4.0 2.0 − − − 6.5 4.8 − 5.2 − 38 − Ciss − 2050 − Coss − 871 − Crss − 359 − td(on) − 6.3 − tr − 77 − td(off) − 25 − tf − 12 − QT − 17.7 − Q1 − 2.6 − Q2 − 7.1 − − − 0.78 0 63 0.63 1.0 − trr − 37.5 − ta − 16.8 − tb − 20.7 − QRR − 0.027 − Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(br)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 20 Adc) RDS(on) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 15 Adc) Vdc mV/°C m gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 30 Adc, RG = 3) Fall Time Gate Charge (VGS = 5 Vdc, ID = 10 Adc, VDS = 10 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage VSD ((IS = 10 Adc, VGS = 0 Vdc) ((Note 3)) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 Vdc ns C NTD85N02R 160 4.4 V 5V 3.8 V 6V 120 VDS ≥ 10 V VGS = 4 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 160 10 V 3.6 V 3.4 V 3.2 V 80 3V 2.8 V 40 2.6 V 120 80 TJ = 25°C 40 TJ = 125°C 2.4 V 2 6 4 10 8 0 2 1 3 4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE () VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.018 VGS = 10 V 0.014 0.010 TJ = 125°C 0.006 TJ = 25°C TJ = −55°C 0.002 0 40 120 80 160 6 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.018 VGS = 4.5 V 0.014 TJ = 125°C 0.010 TJ = 25°C 0.006 TJ = −55°C 0.002 0 80 40 120 160 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature 100,000 1.8 1.6 VGS = 0 V ID = 40 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE () 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C 0 0 TJ = 150°C 10,000 1.4 1.2 1.0 TJ = 125°C 1000 0.8 0.6 −50 100 −25 0 25 50 75 100 125 150 0 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 25 NTD85N02R POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4800 TJ = 25°C C, CAPACITANCE (pF) 4000 3200 Ciss Crss 2400 Ciss 1600 Coss 800 Crss VDS = 0 V VGS = 0 V 0 10 0 5 VGS 5 10 15 20 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 6 1000 QT VGS 4 Q1 t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTD85N02R Q2 100 tr td(off) tf 10 2 td(on) VDS = 10 V ID = 40 A VGS = 10 V ID = 10 A TJ = 25°C 0 1 0 4 8 12 16 QG, TOTAL GATE CHARGE (nC) 20 1 10 RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 80 VGS = 0 V 70 60 50 40 30 20 10 TJ = 25°C 0 0 0.2 0.6 0.4 0.8 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 NTD85N02R SAFE OPERATING AREA I D, DRAIN CURRENT (AMPS) 100 10 s 100 s VGS = 20 V SINGLE PULSE TC = 25°C 10 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 1 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 Figure 11. Maximum Rated Forward Biased Safe Operating Area EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RJC at Steady State 1 r(t), 0.1 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) Figure 12. Thermal Response http://onsemi.com 6 0.1 1 10 NTD85N02R EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 10 Normalized to RJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 r(t), 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, TIME (s) Figure 13. Thermal Response ORDERING INFORMATION Device NTD85N02R Package Shipping† DPAK DPAK (Pb−Free) 75 Units / Rail NTD85N02R−001 DPAK−3 800 Tape & Reel NTD85N02R−1G DPAK−3 (Pb−Free) 800 Tape & Reel DPAK 2500 Tape & Reel DPAK (Pb−Free) 2500 Tape & Reel NTD85N02RG NTD85N02RT4 NTD85N02RT4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NTD85N02R PACKAGE DIMENSIONS DPAK CASE 369C ISSUE O −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD85N02R PACKAGE DIMENSIONS DPAK−3 CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− 3 PL 0.13 (0.005) M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T http://onsemi.com 9 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− NTD85N02R ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 10 For additional information, please contact your local Sales Representative. NTD85N02R/D