MC14598B 8−Bit Bus−Compatible Latches The MC14598B is an 8−bit latch addressed with an external binary address. The 8 latch−outputs are high drive, three−state and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. http://onsemi.com PDIP−18 P SUFFIX CASE 707 Features • • • • • • • • • • 1 Serial Data Input Three−State Bus Compatible Parallel Outputs Three−State Control Pin (Enable) TTL Compatible Input Open Drain Full Flag (Multiple Latch Wire−O Ring) Master Reset Level Shifting Inputs on All Except Enable Diode Protection — All Inputs Supply Voltage Range — 3.0 Vdc to 18 Vdc Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows: 1 TTL Load 4 LSTTL Loads Pb−Free Package is Available* MARKING DIAGRAM 18 MC14598BCP AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter OUTPUT TRUTH TABLE Symbol Value Unit DC Supply Voltage Range VDD −0.5 to +18.0 V Enable Outputs Input Voltage Range, enable (DC or Transient) Vin −0.5 to VDD +0.5 V 1 High Impedance 0 Dn Input Voltage Range, all Other Inputs (DC or Transient) Vin −0.5 to VDD +12 V Output Voltage Range, (DC or Transient) Vout −0.5 to VDD +0.5 V Input or Output Current (DC or Transient) per Pin Iin, Iout ±10 mA Power Dissipation per Package (Note 1) PD 500 mW Ambient Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8−Second Soldering) TL 260 °C *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. June, 2006 − Rev. 6 ORDERING INFORMATION Device Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C © Semiconductor Components Industries, LLC, 2006 Dn = State of nth latch NC = NO CONNECTION 1 Package Shipping MC14598BCP PDIP−18 20 Units/Rail MC14598BCPG PDIP−18 (Pb−Free) 20 Units/Rail This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Publication Order Number: MC14598B/D MC14598B PIN ASSIGNMENT D0 1 18 VDD RESET 2 17 D1 DATA 3 16 D2 ENABLE 4 15 D3 NC 5 14 D4 STROBE 6 13 D5 A0 7 12 D6 A1 8 11 D7 VSS 9 10 A2 BLOCK DIAGRAM ENABLE 4 RESET DATA STROBE A0 A1 A2 2 3 6 8 LATCHES 7 8 ADDRESS 10 DECODER 1 17 16 15 14 13 12 11 THREE STATE OUTPUT BUFFERS VDD = 18 VSS = 9 D0 D1 D2 D3 D4 D5 D6 D7 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C VDD Symbol Vdc Min Max Min “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 – − − 0 0 0 0.05 0.05 0.05 – − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 – − − 4.95 9.95 14.95 5.0 10 15 – − − 4.95 9.95 14.95 – − − Vdc “0” Level VIL 5.0 10 15 − − − 0.8 1.6 2.4 − − − 1.1 2.2 3.4 0.8 1.6 2.4 – − − 0.8 1.6 2.4 5.0 10 15 2.0 6.0 10 − − − 2.0 6.0 10 1.9 3.1 4.3 – − − 2.0 6.0 10 – − − Characteristic Output Voltage Vin = VDD or 0 Vin = 0 or VDD Input Voltage (Note 3), Enable (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) 125_C Typ (Note 2) “1” Level Min Max Unit Vdc VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Input Voltage Other Inputs (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) “1” Level VIH Source IOH Output Drive Current (Full — Sink Only) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Max Vdc VIL Vdc 5.0 10 15 − − − 1.5 3.0 4.0 – − − 2.25 4.50 6.75 1.5 3.0 4.0 – − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 – − − 3.5 7.0 11 2.75 5.50 8.25 – − − 3.5 7.0 11 – − − Vdc mAdc 5.0 10 15 –1.0 − − – − − –1.0 − − –2.0 –6.0 –12 – − − –1.0 − − – − − IOL 5.0 10 15 1.6 − − − − − 1.6 − − 3.2 6.0 12 – − − 1.6 − − – − − mAdc Input Current Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc 3−State Leakage Current ITL 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 3.0 mAdc (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 – − − 150 300 600 mAdc IT = (2.0 mA/kHz) f + IDD IT = (4.0 mA/kHz) f + IDD IT = (6.0 mA/kHz) f + IDD 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. Total Supply Current at an External Load Capacitance of 130 pF (Note 3) IT 5.0 10 http://onsemi.com 2 mAdc MC14598B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 4) (TA = 25_C, CL = 130 pF + 1 TTL Load) All Types VDD Vdc Min Typ (Note 5) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 160 125 100 320 250 200 Strobe to Output 5.0 10 15 − − − 200 100 80 400 200 160 Reset to Output 5.0 10 15 − − − 175 90 70 350 180 140 5.0 10 15 320 240 160 160 120 80 − − − Strobe 5.0 10 15 200 100 80 100 50 40 − − − Increment 5.0 10 15 200 100 80 100 50 40 − − − Reset 5.0 10 15 300 160 100 150 80 50 − − − 5.0 10 15 100 50 35 50 25 20 − − − 5.0 10 15 200 100 70 100 50 35 − − − 5.0 10 15 100 50 35 50 25 20 − − − 5.0 10 15 100 50 35 50 25 20 − − − 5.0 10 15 20 20 20 – 25 – 15 – 10 − − − Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (0.5 ns/pF) CL + 35 ns tTLH, tTHL = (0.2 ns/pF) CL + 25 ns tTLH, tTHL = (0.16 ns/pF) CL + 20 ns tTLH, tTHL Propagation Delay Time Enable to Output tPLH, tPHL Pulse Width Enable ns ns tsu Address ns th Hold Time Data Address Reset Removal Time ns tWH, tWL Setup Time Data trem ns 4. The formulas given are for the typical characteristics only at 25_C. 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 3 Unit ns MC14598B MC14598B FUNCTION DIAGRAM RESET2 VDD DATA3 1D0 TO OTHER LATCHES STROBE6 ENABLE4 VSS EACH LATCH TO OTHER LATCHES ZERO SELECT 17D1 16D2 15D3 14D4 13D5 12D6 11D7 A07 ADDRESS DECODER A18 ADDITIONAL 7 LATCHES A210 (M.S.B) MC14598B TIMING DIAGRAM 50% tTHL D7 90% 10% tPLH 90% 10% 50% 1 tPLH tPHL tTLH RESET 20 ns tW A0, A1, A2 90% 10% 50% tsu DATA 90% 10% STROBE ENABLE * tsu 50% 90% 10% th 20 ns 20 ns tW *1.4 V with VDD = 5.0 V NOTES: 1. High−impedance output state (another device controls bus). 2. Output Load as for MC14597B. http://onsemi.com 4 tW th MC14598B LATCH TRUTH TABLE TRUTH TABLE FOR MC14597B Address Latch Other Latches Strobe Reset 0 1 * 1 1 Data X 0 0 0 Increment Address Counter Enable Reset * X 1 Count Up − * X 1 No Change − X 1 0 Reset to Zero Set to One X 0 1 No Change Set to One 1 If at ADDRESS 7 To Zero on Falling Edge of STROBE *= No change in state of latch X = Don’t care X 1 Full X = Don’t care TEST LOAD, ALL OUTPUTS +5.0 V RL = 2.5 k Dn 130 pF 11.7 k Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and is believed to be reliable. Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under the patent rights of Motorola or others. The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time. http://onsemi.com 5 MC14598B PACKAGE DIMENSIONS PDIP−18 CASE 707−02 ISSUE D NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH. J 18 10 1 9 B L M A DIM A B C D F G H J K L M N C N F H D G K SEATING PLANE INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15 _ 0.51 1.02 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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