FAIRCHILD SG5851ASY

SG5851A
Low-Cost, Green-Mode, PWM Controller for Flyback
Converters
Features
Description
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Green-Mode PWM
This highly integrated PWM controller provides several
enhancements designed to meet the low standby-power
needs of low-power SMPS. To minimize standby power
consumption, the proprietary green-mode function
provides off-time modulation to linearly decrease the
switching frequency under light-load conditions. This
green-mode function enables the power supply to meet
power conservation requirements.
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VDD Over-Voltage Protection (Auto Restart)
Supports the “Blue Angel” Standard
Low Startup Current: 9µA
Low Operating Current: 3mA
Leading-Edge Blanking
Constant Output Power Limit
Universal Input
Built-in Synchronized Slope Compensation
Current Mode Operation
Cycle-by-cycle Current Limiting
Under-Voltage Lockout (UVLO)
Programmable PWM Frequency with Frequency
Hopping
Gate Output Voltage Clamped at 17V
Low Cost
The BiCMOS fabrication process enables reducing the
startup current to 9µA and the operating current to 3mA.
To further improve power conservation, a large startup
resistance can be used. Built-in synchronized slope
compensation ensures the stability of peak-currentmode control. Proprietary internal compensation
provides a constant output power limit over a universal
AC input range (90VAC to 264VAC). Pulse-by-pulse
current limiting ensures safe operation even during
short circuits.
To protect the external power MOSFET from being
damaged by supply over voltage, the output driver is
clamped at 17V. SG5851A controllers, available in an
SOP package, can be used to improve the performance
and reduce the production cost of power supplies.
Few External Components Required
Applications
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Power Adaptors
Open-Frame SMPS
Ordering Information
Part Number
Operating
Temperature Range
Package
Eco Status
Packing
Method
SG5851ASY
-40°C to +105°C
8-pin Small Outline Package (SOP)
Green
Tape & Reel
SG5851ADY
-40°C to +105°C
8-pin Dual in-line Package (DIP)
Green
Tube
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
August 2008
10µ
SG5851A
Figure 1.
Typical Application
Block Diagram
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Application Diagram
Figure 2. Function Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
2
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Marking Information
F- Fairchild logo
Z- Plant code
X- 1 digit year code
Y- 1 digit week code
TT: 2 digits die run code
T: Package type (S=SOP, D=DIP)
P: Y: Green compound
M: Manufacture flow code
5851A
TPM
Figure 3. Marking Information
Pin Configuration
GA TE
VDD
SENSE
NC
8
7
6
5
1
2
3
4
GN D
FB
VDD
RI
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
1
GND
2
FB
3
VDD
Description
Ground
Feedback
Power Supply
4
RI
Reference Setting. A resistor connected from the RI pin to ground generates a constant
current source used to charge an internal capacitor and determine the switching frequency.
Increasing the resistance reduces the amplitude of the current source and reduces the
switching frequency. A 95kΩ resistor, RI, results in a 13µA constant current, II, and a 70kHz
switching frequency.
5
NC
No Connection
6
SENSE
7
VDD
8
GATE
Current Sense. This pin senses the voltage across a resistor. When the voltage reaches the
internal threshold, PWM output is disabled. This activates over-current protection. This pin also
provides current amplitude information for current-mode control.
Power Supply
Driver Output. The totem-pole output driver for driving the power MOSFET.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are
given with respect to GND pin. Stresses beyond those listed under “absolute maximum ratings “may cause
permanent damage to the device.
Symbol
Parameter
Min.
Max.
Unit
30
V
VVDD
DC Supply Voltage
VFB
Input Voltage to FB Pin
-0.3
7.0
V
Input Voltage to Sense Pin
-0.3
7.0
V
VSENSE
PD
Power Dissipation
300
mW
TJ
Operating Junction Temperature
+150
°C
θJA
Thermal Resistance (Junction-to-Air)
141
°C/W
+150
°C
+260
°C
Electrostatic Discharge Capability,
Human Body Model, JESD22-A114
3.0
KV
Electrostatic Discharge Capability,
Machine Model, JESD22-A115
200
V
TSTG
TL
ESD
-55
Storage Temperature Range
Lead Temperature (Wave soldering, or IR 10 seconds)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Min.
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
-40
Typ.
Max.
Unit
+105
°C
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Absolute Maximum Ratings
www.fairchildsemi.com
4
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
22
V
VDD Section
VDD-OP
Continuous Operation Voltage
VDD-ON
Turn-on Threshold Voltage
15.5
16.5
17.5
V
VDD-OFF
Turn-off Threshold Voltage
10.5
11.5
12.5
V
9
15
µA
3.0
3.5
mA
25
26
V
IDD-ST
Startup Current
VDD=VDD-ON – 0.1V
IDD-OP
Operating Supply Current
VDD=15V, GATE with
1nF to GND
VDD-OVP
VDD Over-Voltage Protection Level
Auto Restart
tD-VDDOVP
VDD Over-Voltage Protection Debounce
Auto Restart
24
100
µs
Feedback Input Section
VFB-OPEN
FB Output High Voltage
VFB-OL
FB Open-loop Trigger Level
tD-OLP
Delay Time of FB Pin Open-Loop Protection
VFB-N
Green-Mode Entry FB Voltage
VFB-G
Green-Mode Ending FB Voltage
SG
VOZ-OFF
5
4.3
V
4.6
4.9
56
2.60
2.85
ms
3.10
2.2
Green-Mode Modulation Slope
RI=95KΩ
40
70
V
V
100
1.75
FB Threshold Voltage for Zero-Duty
V
Hz/mV
V
Current-Sense Section
ZSENSE
Input Impedance
tPD
Delay to Output
10
VDD=13.5 to 22V
40
KΩ
55
100
VSTHFL
Flat Threshold Voltage for Current Limit
VSTHVA
Valley Threshold Voltage for Current Limit
0.75
0.80
0.85
V
Leading-Edge Blanking Time
250
310
370
ns
tLEB
DCYSAW
1
ns
Duty Cycle of SAW Limit
Maximum Duty Cycle
V
45
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Electrical Characteristics
%
Oscillator Section
fOSC
tHOP
Center Frequency
RI=95KΩ
Hopping Range
65
70
75
±4.9
KHz
Hopping Period
RI=95KΩ
3.7
ms
Green-Mode Frequency
RI=95KΩ
22
KHz
fDV
Frequency Variation vs. VDD Deviation
VDD=13.5 to 22V
fDT
Frequency Variation vs. Temperature
Deviation
TA=-20 to +85°C
fOSC-G
0
0.2
2.0
%
2
%
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
5
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
70
75
80
%
1.5
V
Output Section
DCYMAX
Maximum Duty Cycle
VGATE-L
Output Voltage Low
VDD=15V, IO=20mA
VGATE-H
Output Voltage High
VDD=13.5V, IO=20mA
tr
Rising Time
VDD=15V, CL=1nF
120
ns
tf
Falling Time
VDD=15V, CL=1nF
65
ns
Output Clamp Voltage
VDD=22V
VGATECLAMP
8
16
V
17
Frequency
+4.9kHz
70 kHz
-4.9kHz
+1.45kHz
20 kHz
-1.45kHz
No Jitter if VFB < V FB-G
VOZ-OFF
VFB_G
VFB-N
18
V
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Electrical Characteristics
FB
Figure 5. PWM Frequency
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
6
SG5851A devices integrate many useful designs into
one controller for low-power, switch-mode, power
supplies. The following descriptions highlight some of
the features of the SG5851A series.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage (~1.00V), the output
GATE drive is turned off after propagation delay, tPD.
This propagation delay introduces an additional current
proportional to tPD•VIN/Lp. The propagation delay is
nearly constant regardless of the input line voltage VIN.
Higher input line voltages result in larger additional
currents. At high input line voltages, the output power
limit is higher than at low input line voltages.
Startup Current
The startup current is only 9µA, which allows a startup
resistor with a high resistance and a low-wattage to
supply the startup power for the controller. A 1.5MΩ,
0.25W, startup resistor and a 10µF/25V VDD hold-up
capacitor are sufficient for an AC-to-DC power adapter
with a wide input range (90VAC to 264VAC).
To compensate for this output power limit variation
across a wide AC input range, the threshold voltage is
adjusted by adding a positive ramp. This ramp signal
rises from 0.80V to 1.00V, then flattens out at 1.00V. A
smaller threshold voltage forces the output GATE drive
to terminate earlier. This reduces the total PWM turn-on
time and makes the output power equal to that of lowline input. This proprietary internal compensation
ensures a constant output power limit for a wide AC
input voltage range (90VAC to 264VAC).
Operating Current
The operating current has been reduced to 3mA, which
results in higher efficiency and reduces the VDD hold-up
capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. On-time is limited to provide
stronger protection against brownouts and abnormal
conditions. The feedback current, which is sampled
from the voltage feedback loop, is taken as the
reference. Once the feedback current exceeds the
threshold current, the switching frequency starts to
decrease. Green mode dramatically reduces power
consumption under light-load and zero-load conditions.
Power supplies using SG5851A meet even the strictest
regulations regarding standby power consumption.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 11.5V. During startup, the hold-up
capacitor must be charged to 16.5V through the startup
resistor to enable SG5851A. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 11.5V during the startup process.
This UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
Gate Output
Oscillator Operation
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
17V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
A resistor connected from the RI pin to ground
generates a constant current source used to charge an
internal capacitor. The charge time determines the
internal clock speed and the switching frequency.
Increasing the resistance reduces the amplitude of the
input current and reduces the switching frequency. A
95kΩ resistor, RI, results in a 13µA constant current, II,
and a 70kHz switching frequency. The relationship
between RI and the switching frequency is:
fPWM =
6650
(kHz )
RI ( kΩ)
Built-in Slope Compensation
The sensed voltage across the current sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current-mode control. The SG5851A has a
synchronized, positively-sloped ramp built-in at each
switching cycle. The slope of the ramp is:
0.36 × Duty
(2)
(1)
The range of the oscillation frequency is designed to be
within 50kHz ~ 80kHz.
Leading-Edge Blanking (LEB)
Duty (max .)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a 310ns leadingedge blanking time is built in. Conventional RC filtering
can therefore be omitted. During this blanking period,
the current-limit comparator is disabled and it cannot
switch off the gate driver.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Functional Description
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode. While slope compensation
helps alleviate these problems, further precautions should
be taken. Good placement and layout practices should be
followed. Avoiding long PCB traces and component
leads, locating compensation and filter components near
the SG5851A, and increasing power MOS gate
resistance improve performance.
www.fairchildsemi.com
7
14.0
16.8
12.8
V DD-O F F (V )
V DD-O N (V )
17.0
16.6
16.4
11.6
10.4
9.2
16.2
16.0
8.0
-40
-25
-10
5
20
35
50
65
80
Temperature (℃ )
95
110
125
-40
-25
Figure 6. VDD-ON vs. TA
8.4
1.88
IDD-O P (mA)
2.00
IDD-S T (µA )
5
20
35
50
65
Temperature (℃ )
80
95
110
125
Figure 7. VDD-OFF vs. TA
10.0
6.8
5.2
3.6
1.76
1.64
1.52
2.0
1.40
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
Temperature (℃ )
-25
Figure 8. IDD-ST vs. TA
70.0
76.0
69.2
75.2
68.4
67.6
66.8
66.0
-40
-25
-10
5
20
35
50
65
80
95
110
5
20
35
50
65
Temperature (℃ )
80
95
110
125
80
95
110
125
74.4
73.6
72.8
72.0
125
-40
Temperature (℃ )
Figure 10. fOSC vs. TA
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
-10
Figure 9. IDD-OP vs. TA
D C Y M A X (%)
fO S C (K H z)
-10
-25
-10
5
20
35
50
65
Temperature (℃ )
Figure 11. DCYMAX vs. TA
www.fairchildsemi.com
8
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Typical Performance Characteristics
2.40
3.12
2.36
V F B -G (V )
V F B -N (V )
3.20
3.04
2.96
2.88
2.32
2.28
2.24
2.80
2.20
-40
-25
-10
5
20
35
50
65
Temperature (℃ )
80
95
110
125
-40
-25
Figure 12. VFB-N vs. TA
5
20
35
50
65
Temperature (℃ )
80
95
110
125
80
95
110
125
Figure 13. VFB-G vs. TA
320
1.90
308
tLE B (ns )
1.86
V O Z (V )
-10
1.82
1.78
296
284
272
1.74
260
1.70
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
Figure 14. VOZ vs. TA
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
-25
-10
5
20
35
50
65
Temperature (℃ )
Temperature (℃ )
Figure 15. tLEB vs. TA
www.fairchildsemi.com
9
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Typical Performance Characteristics (Continued)
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Mechanical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
5.08 MAX
7.62
0.33 MIN
3.60
3.00
(0.56)
2.54
0.56
0.355
0.356
0.20
1.65
1.27
9.957
7.87
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 16.
8-Lead, PDIP, JEDEC MS-001, .300 Inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
10
5.00
4.80
A
0.65
3.81
8
5
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
Mechanical Dimensions (Continued)
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 17.
8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
11
SG5851A — Low-Cost, Green-Mode, PWM Controller for Flyback Converters
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
12