MC74LVX139 Dual 2-to-4 Decoder/ Demultiplexer The MC74LVX139 is an advanced high speed CMOS 2–to–4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. • • • • • • • • • • • High Speed: tPD = 6.0 ns (Typ) at VCC = 3.3 V http://onsemi.com MARKING DIAGRAMS 16 SOIC–16 D SUFFIX CASE 751B Low Power Dissipation: ICC = 4 µΑ (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs 9 LVX139 AWLYYWW 1 8 9 16 Balanced Propagation Delays Designed for 2 V to 3.6 V Operating Range Low Noise: VOLP = 0.5 V (Max) Pin and Function Compatible with Other Standard Logic Families LVX139 AWLYWW TSSOP–16 DT SUFFIX CASE 948F 1 8 Latchup Performance Exceeds 300 mA 16 ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 100 FETs or 25 Equivalent Gates SOIC EIAJ–16 M SUFFIX CASE 966 Ea 1 16 VCC A0a 2 15 Eb A1a 3 14 A0b Y0a 4 13 A1b Y1a 5 12 Y0b Y2a 6 11 Y1b Y3a 7 10 Y2b GND 8 9 Y3b Device Outputs E A1 A0 Y0 Y1 Y2 Y3 H L L L L X L L H H X L H L H H L H H H H H L H H H H H H L Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 1 1 8 ORDERING INFORMATION FUNCTION TABLE H H H L H LVX139 ALYW A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Figure 1. Pin Assignment Inputs 9 1 Package Shipping MC74LVX139D SO–16 48 Units/Rail MC74LVX139DR2 SO–16 2500 Units/Reel MC74LVX139DT TSSOP–16 96 Units/Rail MC74LVX139DTR2 TSSOP–16 2000 Units/Reel MC74LVX139M SO EIAJ–16 MC74LVX139MEL SO EIAJ–16 2000 Units/Reel 48 Units/Rail Publication Order Number: MC74LVX139/D MC74LVX139 ADDRESS INPUTS A0a A1a 2 4 3 5 Y0a Y1a 6 7 Ea ADDRESS INPUTS A0b A1b Y3a 1 14 12 13 11 10 9 Eb ACTIVE–LOW OUTPUTS Y2a Y0b Y1b Y2b ACTIVE–LOW OUTPUTS Y3b 15 Figure 2. Logic Diagram En Y0 Y1 A0 Y2 Y3 A1 Figure 3. Expanded Logic Diagram (1/2 of Device) A1a 3 A0a 2 Ea 1 X/Y 1 0 2 1 EN 2 3 A1b 13 A0b 14 Eb 15 4 Y0a A1a 3 5 Y1a A0a 2 6 Y2a Ea 1 7 Y3a 0 1 DMUX 0 0 G 3 1 4 Y0a 5 Y1a 12 Y0b 6 Y2a 7 Y3a 12 Y0b 11 Y1b A1b 13 10 Y2b A0b 14 10 Y2b Eb 15 9 Y3b 9 Y3b 2 3 INPUT 11 Y1b Figure 4. IEC Logic Diagram Figure 5. Input Equivalent Circuit http://onsemi.com 2 MC74LVX139 MAXIMUM RATINGS (Note 1.) Symbol Value Unit VCC Positive DC Supply Voltage Parameter –0.5 to +7.0 V VIN Digital Input Voltage –0.5 to +7.0 V VOUT DC Output Voltage –0.5 to VCC +0.5 V IIK Input Diode Current –20 mA IOK Output Diode Current 20 mA IOUT DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air 200 180 mW TSTG Storage Temperature Range –65 to +150 °C VESD ESD Withstand Voltage Human Body Model (Note 2.) Machine Model (Note 3.) Charged Device Model (Note 4.) >2000 >200 >2000 V ILATCH–UP Latch–Up Performance Above VCC and Below GND at 125°C (Note 5.) 300 mA JA Thermal Resistance, Junction to Ambient 143 164 °C/W SOIC Package TSSOP SOIC Package TSSOP 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22–A114–A 3. Tested to EIA/JESD22–A115–A 4. Tested to JESD22–C101–A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage TA Operating Temperature Range, all Package Types tr, tf Input Rise or Fall Time Output in 3–State High or Low State VCC = 5.0 V + 0.5 V http://onsemi.com 3 Min Max Unit 2.0 3.6 V 0 5.5 V 0 VCC V –40 85 °C 0 100 ns/V MC74LVX139 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition –40°C ≤ TA ≤ 85°C TA = 25°C (V) Min 0.75 VCC 0.7 VCC 0.7 VCC VIH Minimum High–Level Input Voltage 2.0 3.0 3.6 VIL Maximum Low–Level Input Voltage 2.0 3.0 3.6 VOH High–Level Output Voltage IOH = –50 µA IOH = –50 µA IOH = –4 mA 2.0 3.0 3.0 VOL Low–Level Output Voltage IOL = 50 µA IOH = 50 µA IOH = 4 mA 2.0 3.0 3.0 IIN Input Leakage Current VIN = 5.5 V or GND 0 to 3.6 ICC Maximum Quiescent Supply Current (per package) VIN = VCC or GND 3.6 Typ Max Min V 0.25 VCC 0.3 VCC 0.3 VCC 2.0 3.0 3.0 V 1.9 2.9 2.48 0.0 1.0 Unit 0.75 VCC 0.7 VCC 0.7 VCC 0.25 VCC 0.3 VCC 0.3 VCC 1.9 2.9 2.58 Max V 0.1 0.1 0.36 0.1 0.1 0.44 V ±0.1 ±1.0 µA 1.0 µA 2.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns –40°C ≤ TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL tPLH, tPHL CIN Parameter Maximum Propagation Delay, A to Y Maximum Propagation Delay, E to Y Typ Max Min Max Unit VCC = 2.7 V Test Conditions CL = 15 pF CL = 50 pF 8.5 11.0 15.0 16.5 1.0 1.0 17.8 18.0 ns VCC = 3.3 V ± 0.3 V CL = 15 pF CL = 50 pF 6.0 8.5 10.0 13.0 1.0 1.0 12.0 15.0 VCC = 2.7 V CL = 15 pF CL = 50 pF 8.0 10.0 13.0 16.5 1.0 1.0 15.5 18.0 VCC = 3.3 V ± 0.3 V CL = 15 pF CL = 50 pF 5.5 7.5 8.2 13.0 1.0 1.0 10.0 15.0 4 10 Maximum Input Capacitance Min 10 ns pF Typical @ 25°C, VCC = 3.3 V CPD 26 Power Dissipation Capacitance (Note 6.) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 4 MC74LVX139 VCC A 50% GND tPHL tPLH 50% VCC Y Figure 6. Switching Waveform E VCC 50% GND tPHL Y tPLH 50% VCC Figure 7. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 8. Test Circuit http://onsemi.com 5 MC74LVX139 P0 K t 10 PITCHES CUMULATIVE TOLERANCE ON TAPE ±0.2 mm (±0.008”) P2 D TOP COVER TAPE E A0 SEE NOTE 7. + K0 B1 + B0 SEE NOTE 7. F P EMBOSSMENT FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0 USER DIRECTION OF FEED CENTER LINES OF CAVITY 10° D1 FOR COMPONENTS 2.0 mm × 1.2 mm AND LARGER *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004”) MAX. R MIN. BENDING RADIUS W + TAPE AND COMPONENTS SHALL PASS AROUND RADIUS “R” WITHOUT DAMAGE EMBOSSED CARRIER EMBOSSMENT 100 mm (3.937”) MAXIMUM COMPONENT ROTATION 1 mm MAX TYPICAL COMPONENT CAVITY CENTER LINE TAPE 1 mm (0.039”) MAX TYPICAL COMPONENT CENTER LINE 250 mm (9.843”) CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity Figure 9. Carrier Tape Specifications http://onsemi.com 6 MC74LVX139 EMBOSSED CARRIER DIMENSIONS (See Notes 8. and 9.) Tape Size B1 Max 8 mm 4.35 mm (0.179”) 12 mm 8.2 mm (0.323”) 16 mm 24 mm D D1 E F K P P0 P2 R T W 1.5 mm + 0.1 –0.0 (0.059” ( 0 004 +0.004 –0.0) 1.0 mm Min (0.179”) 1.75 mm ±0.1 (0.069 ±0.004”)) 3.5 mm ±0.5 (1.38 ±0.002”) 2.4 mm Max (0.094”) 4.0 mm ±0.10 (0.157 ±0.004”) 4.0 mm ±0.1 (0.157 ±0.004”)) 2.0 mm ±0.1 (0.079 ±0.004”)) 25 mm (0.98”) 0.6 mm (0.024) 8.3 mm (0.327) 5.5 mm ±0.5 (0.217 ±0.002”) 6.4 mm Max (0.252”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.1 mm (0.476”) 7.5 mm ±0.10 (0.295 ±0.004”) 7.9 mm Max (0.311”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.0 mm ±0.10 (0.472 ±0.004”) 16.3 mm (0.642) 20.1 mm (0.791”) 11.5 mm ±0.10 (0.453 ±0.004”) 11.9 mm Max (0.468”) 16.0 mm ±0.10 (0.63 ±0.004”) 24.3 mm (0.957) 1.5 mm Min (0.060) 30 mm (1.18”) 12.0 mm ±0.3 (0.470 ±0.012”) 8. Metric Dimensions Govern–English are in parentheses for reference only. 9. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity t MAX 1.5 mm MIN (0.06”) A 13.0 mm ±0.2 mm (0.512” ±0.008”) 20.2 mm MIN (0.795”) 50 mm MIN (1.969”) FULL RADIUS G Figure 10. Reel Dimensions http://onsemi.com 7 MC74LVX139 REEL DIMENSIONS Tape Size T&R Suffix A Max G t Max 8 mm T1, T2 178 mm (7”) 8.4 mm, +1.5 mm, –0.0 (0.33” + 0.059”, –0.00) 14.4 mm (0.56”) 8 mm T3, T4 330 mm (13”) 8.4 mm, +1.5 mm, –0.0 (0.33” + 0.059”, –0.00) 14.4 mm (0.56”) 12 mm R2 330 mm (13”) 12.4 mm, +2.0 mm, –0.0 (0.49” + 0.079”, –0.00) 18.4 mm (0.72”) 16 mm R2 360 mm (14.173”) 16.4 mm, +2.0 mm, –0.0 (0.646” + 0.078”, –0.00) 22.4 mm (0.882”) 24 mm R2 360 mm (14.173”) 24.4 mm, +2.0 mm, –0.0 (0.961” + 0.078”, –0.00) 30.4 mm (1.197”) DIRECTION OF FEED BARCODE LABEL POCKET Figure 11. Reel Winding Direction http://onsemi.com 8 HOLE MC74LVX139 CAVITY TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN TOP TAPE TAPE LEADER NO COMPONENTS 400 mm MIN COMPONENTS DIRECTION OF FEED Figure 12. Tape Ends for Finished Goods User Direction of Feed Figure 13. TSSOP and SOIC R2 Reel Configuration/Orientation TAPE UTILIZATION BY PACKAGE Tape Size SOIC TSSOP QFN 8 mm 12 mm SC88A / SOT–353 SC88/SOT–363 5–, 6–Lead 8–Lead 8–, 14–, 16–Lead 8–, 14–, 16–Lead 16 mm 14–, 16–Lead 20–, 24–Lead 20–, 24–Lead 24 mm 18–, 20–, 24–, 28–Lead 48–, 56–Lead 48–, 56–Lead http://onsemi.com 9 MC74LVX139 PACKAGE DIMENSIONS SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 10 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74LVX139 PACKAGE DIMENSIONS TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉ ÇÇÇ ÇÇÇ ÉÉ ÇÇÇ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A –V– M N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE H D DETAIL E G http://onsemi.com 11 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74LVX139 PACKAGE DIMENSIONS SOIC EIAJ–16 M SUFFIX CASE 966–01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.031 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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