ONSEMI MC74VHC125D

MC74VHC125
Quad Bus Buffer
with 3–State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC125 requires the 3–state control input (OE) to be set
High to place the output into the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 3.8ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 72 FETs or 18 Equivalent Gates
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14–LEAD SOIC
D SUFFIX
CASE 751A
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
A1
OE1
A2
OE2
A3
OE3
A4
OE4
5
6
8
VCC
A1
2
13
OE4
12
A4
4
11
Y4
A2
5
10
OE3
Y2
6
9
A3
GND
7
8
Y3
For detailed package marking information, see the Marking
Diagram section on page 5 of this data sheet.
Y2
4
9
14
3
Y1
1
1
Y1
Active–Low Output Enables
3
OE1
OE2
LOGIC DIAGRAM
2
14–LEAD TSSOP
DT SUFFIX
CASE 948G
Y3
ORDERING INFORMATION
10
12
11
Device
Y4
Package
Shipping
SOIC
55 Units/Rail
MC74VHC125DT
TSSOP
96 Units/Rail
MC74VHC125M
SOIC EIAJ
50 Units/Rail
MC74VHC125D
13
FUNCTION TABLE
VHC125
Inputs
OE
Y
H
L
X
L
L
H
H
L
Z
 Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 2
Output
A
1
Publication Order Number:
MC74VHC125/D
MC74VHC125
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MAXIMUM RATINGS*
Symbol
Value
Unit
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
– 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
VCC
Parameter
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
v
v
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute–maximum–rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage
Min
Max
Unit
2.0
5.5
V
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
– 40
+ 85
_C
0
0
100
20
ns/V
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
Min
1.5
2.1
3.15
3.85
VIH
Minimum High–Level
Input Voltage
2.0
3.0
4.5
5.5
VIL
Maximum Low–Level
Input Voltage
2.0
3.0
4.5
5.5
VOH
Minimum High–Level
Output Voltage
VIN = VIH or VIL
VOL
IOZ
Maximum Low–Level
Output Voltage
VIN = VIH or VIL
Maximum 3–State
Leakage Current
TA ≤ 85°C
TA = 25°C
(V)
Typ
Max
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
VIN = VIH or VIL
IOH = –50µA
2.0
3.0
4.5
1.9
2.9
4.4
VIN = VIH or VIL
IOH = –4mA
IOH = –8mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50µA
2.0
3.0
4.5
VIN = VIH or VIL
IOL = 4mA
IOL = 8mA
Max
2.0
3.0
4.5
TA ≤ 125°C
Min
Max
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
V
0.5
0.9
1.35
1.65
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
5.5
±0.25
±2.5
±2.5
V
V
VIN = VIH or VIL
VOUT = VCC or GND
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2
µA
MC74VHC125
IIN
Maximum Input
Leakage Current
VIN = 5.5V or GND
0 to
5.5
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
4.0
40
40
µA
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Cin
Cout
Parameter
Test Conditions
Min
TA = ≤ 85°C
TA = ≤ 125°C
Typ
Max
Min
Max
Min
Max
Unit
ns
Maximum Propagation
Delay,
A to Y
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
12.0
16.0
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
8.5
10.5
Maximum Output Enable
TIme,
OE to Y
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 15pF
CL = 50pF
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
11.5
15.0
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 15pF
CL = 50pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
1.0
1.0
7.5
9.5
Maximum Output
Disable Time,
OE to Y
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 50pF
9.5
13.2
1.0
15.0
1.0
18.0
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 50pF
6.1
8.8
1.0
10.0
1.0
12.0
Output–to–Output Skew
VCC = 3.3 ± 0.3V
(Note 1.)
CL = 50pF
1.5
1.5
1.5
VCC = 5.0 ± 0.5V
(Note 1.)
CL = 50pF
1.0
1.0
1.0
10
10
10
Maximum Input
Capacitance
4
Maximum Three–State
Output Capacitance
(Output in High
Impedance State)
6
ns
ns
ns
pF
pF
Typical @ 25°C, VCC = 5.0V
CPD
Power Dissipation Capacitance (Note 2.)
pF
14
1. Parameter guaranteed by design. tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the
no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
– 0.3
– 0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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3
MC74VHC125
SWITCHING WAVEFORMS
OE
VCC
50%
VCC
GND
50%
A
tPZL tPLZ
GND
tPHL
tPLH
HIGH
IMPEDANCE
50% VCC
Y
50% VCC
VOL + 0.3V
tPZH tPHZ
Y
Figure 1.
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
VOH – 0.3V
HIGH
IMPEDANCE
50% VCC
Y
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
OUTPUT
1 kΩ
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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4
MC74VHC125
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
14 13 12 11 10
8
3
4
6
7
125
AWLYWW*
2
8
VHC
VHC125
1
9
ALYW*
5
6
7
1
2
14–LEAD SOIC
D SUFFIX
CASE 751A
3
4
5
14–LEAD TSSOP
DT SUFFIX
CASE 948G
14
13
12
11
10
9
8
6
7
VHC125
AWLYWW*
1
2
3
4
5
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
*See Applications Note #AND8004/D for date code and traceability information.
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5
MC74VHC125
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
P 7 PL
–B–
1
0.25 (0.010)
7
G
0.25 (0.010)
T
M
F
J
M
K
D 14 PL
M
R X 45°
C
SEATING
PLANE
B
M
B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
–V–
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
G
H
DETAIL E
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74VHC125
PACKAGE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965–01
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
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7
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
1.42
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.056
MC74VHC125
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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8
MC74VHC125/D