ONSEMI PCA9655E

PCA9655E
Remote 16-bit I/O Expander
for I2C Bus with Interrupt
The PCA9655E provides 16 bits of General Purpose parallel Input /
Output (GPIO) expansion through the I2C−bus / SMBus.
The PCA9655E consists of two 8−bit Configuration (Input or
Output selection); Input, Output and Polarity Inversion (active−HIGH
or active−LOW operation) registers. At power on, all I/Os default to
inputs. Each I/O may be configured as either input or output by writing
to its corresponding I/O configuration bit. The data for each Input or
Output is kept in its corresponding Input or Output register. The
Polarity Inversion register may be used to invert the polarity of the
read register. All registers can be read by the system master.
The PCA9655E provides an open−drain interrupt output which is
activated when any input state differs from its corresponding input
port register state. The interrupt output is used to indicate to the system
master that an input state has changed. The power−on reset sets the
registers to their default values and initializes the device state
machine.
Three hardware pins (AD0, AD1, AD2) are used to configure the
I2C−bus slave address of the device. Up to 64 devices are allowed to
share the same I2C−bus / SMBus.
Features
•
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•
•
•
•
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VDD Operating Range: 1.65 V to 5.5 V
SDA Sink Capability: 30 mA
5.5 V Tolerant I/Os
Polarity Inversion Register
Active LOW Interrupt Output
Low Standby Current
Noise Filter on SCL/SDA Inputs
No Glitch on Power−up
Internal Power−on Reset
64 Programmable Slave Addresses Using Three Address Pins
16 I/O Pins Which Default to 16 Inputs
I2C SCL Clock Frequencies Supported:
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
ESD Performance: 2000 V Human Body Model,
200 V Machine Model
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 1
1
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MARKING
DIAGRAMS
SOIC−24
DW SUFFIX
CASE 751E
TSSOP−24
DT SUFFIX
CASE 948H
1
WQFN24
MT SUFFIX
CASE 485BG
PCA9655E
AWLYYWWG
PCA96
55EG
AWLYYWW
PCA
9655E
ALYWG
G
XXXX = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Publication Order Number:
PCA9655E/D
PCA9655E
BLOCK DIAGRAM
PCA9655E
IO1_0
IO1_1
8−bit
AD0
IO1_2
INPUT/
OUTPUT
PORTS
AD1
AD2
write pulse
IO1_3
IO1_4
IO1_5
IO1_6
read pulse
IO1_7
I2C−BUS/SMBus
CONTROL
SCL
IO0_0
INPUT
FILTER
SDA
IO0_1
8−bit
IO0_2
INPUT/
OUTPUT
PORTS
write pulse
VDD
IO0_3
IO0_4
IO0_5
IO0_6
read pulse
POWER−ON
RESET
IO0_7
VSS
VDD
LP filter
INT
Remark: All I/Os are set as inputs at reset.
Figure 1. Block Diagram
data from
shift register
data from
shift register
write
configuration
pulse
write pulse
output port
register data
configuration
register
D
VDD
Q1
Q
FF
CK
100 kW
Q
D
Q
FF
I/O pin
Q2
CK
output port
register
input port
register
D
Q
FF
read pulse
CK
VSS
input port
register data
to INT
polarity inversion
register
data from
shift register
D
Q
FF
write polarity
pulse
CK
At power−on reset, all registers return to default values.
Figure 2. Simplified Schematic of I/Os
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2
polarity
inversion
register data
PCA9655E
19 SCL
20 SDA
21 VDD
22 INT
23 AD1
terminal 1
index area
24 AD2
PIN ASSIGNMENT
INT 1
24 VDD
AD1 2
23 SDA
IO0_0 1
18 AD0
AD2 3
22 SCL
IO0_1 2
17 IO1_7
IO0_0 4
21 AD0
IO0_2 3
IO0_1 5
20 IO1_7
IO0_3 4
IO0_2 6
19 IO1_6
IO0_4 5
14 IO1_4
18 IO1_5
IO0_5 6
13 IO1_3
15 IO1_2
IO0_7 11
14 IO1_1
VSS 12
13 IO1_0
15 IO1_5
IO1_2 12
16 IO1_3
IO0_6 10
IO1_1 11
IO0_5 9
IO1_0 10
17 IO1_4
VSS 9
IO0_4 8
IO0_7 8
PCA9655E
IO0_6 7
IO0_3 7
16 IO1_6
PCA9655E
Transparent top view
(The exposed thermal pad at the bottom
is not connected to internal circuitry)
Figure 4. WQFN24
Figure 3. SOIC24 / TSSOP24
Table 1. PIN DESCRIPTIONS
Pin
Symbol
SOIC24, TSSOP24
WQFN24
INT
1
22
Interrupt Output (active−LOW)
AD1
2
23
Address Input 1
AD2
3
24
Address Input 2
IO0_0
4
1
Port 0 I/O 0
IO0_1
5
2
Port 0 I/O 1
IO0_2
6
3
Port 0 I/O 2
IO0_3
7
4
Port 0 I/O 3
IO0_4
9
5
Port 0 I/O 4
IO0_5
9
6
Port 0 I/O 5
IO0_6
10
7
Port 0 I/O 6
IO0_7
11
9
Port 0 I/O 7
VSS
12
9
Supply Ground
IO1_0
13
10
Port 1 I/O 0
IO1_1
14
11
Port 1 I/O 1
IO1_2
15
12
Port 1 I/O 2
IO1_3
16
13
Port 1 I/O 3
IO1_4
17
14
Port 1 I/O 4
IO1_5
18
15
Port 1 I/O 5
IO1_6
19
16
Port 1 I/O 6
IO1_7
20
17
Port 1 I/O 7
AD0
21
18
Address Input 0
SCL
22
19
Serial Clock Line
SDA
23
20
Serial Data Line
VDD
24
21
Supply Voltage
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3
Description
PCA9655E
Table 2. MAXIMUM RATINGS
Symbol
Value
Unit
VDD
DC Supply Voltage
Parameter
−0.5 to +7.0
V
VI/O
Input / Output Pin Voltage
−0.5 to +7.0
V
II
Input Current
$20
mA
IO
Output Current
$50
mA
IDD
DC Supply Current
$100
mA
IGND
DC Ground Current
$600
mA
PTOT
Total Power Dissipation
600
mW
POUT
Power Dissipation per Output
200
mW
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
150
°C
qJA
Thermal Resistance (Note 1)
85
91
68
°C/W
MSL
Moisture Sensitivity
FR
VESD
ILATCHUP
SOIC−24
TSSOP−24
WQFN24
Level 1
Flammability Rating Oxygen Index: 28 to 34
ESD Withstand Voltage
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Latchup Performance Above VDD and Below GND at 125°C (Note 4)
> 2000
> 200
V
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VDD
Positive DC Supply Voltage
VI/O
Switch Input / Output Voltage
Min
Max
Unit
1.65
5.5
V
0
5.5
V
TA
Operating Free−Air Temperature
−55
+125
°C
Dt / DV
Input Transition Rise or Fall Rate
0
5
nS/V
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4
PCA9655E
Table 4. DC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V, unless otherwise specified.
TA = −555C to +1255C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.1
0.25
1.5
1
mA
mA
1.5
1.65
V
SUPPLIES
ISTB
Standby Current
VPOR
Power−On Reset Voltage
(Note 5)
Standby mode; no load;
VI = 0 V; fSCL = 0 Hz; I/O = inputs
VI = VDD; fSCL = 0 Hz; I/O = inputs
INPUT SCL; Input / Output SDA
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
IOL
Low−Level Output Current
0.7 x VDD
V
0.3 x VDD
VOL = 0.4 V; VDD < 2.3 V
10
VDD w 2.3 V
20
IL
Leakage Current
VI = VDD or 0 V
CI
Input Capacitance
VI = 0 V
V
mA
4.6
$1
mA
6
pF
I/Os
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
IOL
Low−Level Output Current
(Note 6)
VOL = 0.5 V; VDD = 1.65 V
VOL = 0.5 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
VOL = 0.5 V; VDD = 4.5 V
Total Low−Level Output Current
(Note 6)
VOL = 0.5 V; VDD = 4.5 V
VOH
High−Level Output Voltage
IOH = −3 mA; VDD = 1.65 V
IOH = −4 mA; VDD = 1.65 V
IOH = −8 mA; VDD = 2.3 V
IOH = −10 mA; VDD = 2.3 V
IOH = −8 mA; VDD = 3.0 V
IOH = −10 mA; VDD = 3.0 V
IOH = −8 mA; VDD = 4.5 V
IOH = −10 mA; VDD = 4.5 V
ILH
Input Leakage Current
VDD = 5.5 V; VI = VDD
1
mA
ILL
Input Leakage Current
VDD = 5.5 V; VI = 0 V
−100
mA
6.0
pF
IOL(tot)
CI/O
0.7 x VDD
V
0.3 x VDD
8
12
17
25
20
28
35
42
mA
400
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
Input / Output Capacitance
(Note 7)
V
mA
V
5.0
INTERRUPT (INT)
IOL
Low−Level Output Current
CO
Output Capacitance
VOL = 0.4 V
6.0
mA
5.0
5.5
pF
INPUTS AD0, AD1, AD2
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
IL
Leakage Current
CI
Input Capacitance
0.7 x VDD
V
VI = VDD or 0 V
4.5
0.3 x VDD
V
$1
mA
5.0
pF
5. The power−on reset circuit resets the I2C bus logic with VDD < VPOR and set all I/Os to logic 1 upon power−up. Thereafter, VDD must be lower
than 0.2 V to reset the part.
6. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal bussing limits.
7. The value is not tested, but verified on sampling basis.
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5
PCA9655E
Table 5. AC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V; TA = −55°C to +125°C, unless otherwise specified.
Standard
Mode
Symbol
Parameter
Fast Mode
Fast Mode +
Min
Max
Min
Max
Min
Max
Unit
0
0.1
0
0.4
0
1.0
MHz
fSCL
SCL Clock Frequency
tBUF
Bus−Free Time between a STOP and START
Condition
4.7
1.3
0.5
ms
tHD:STA
Hold Time (Repeated) START Condition
4.0
0.6
0.26
ms
tSU:STA
Setup Time for a Repeated START Condition
4.7
0.6
0.26
ms
tSU:STO
Setup Time for STOP Condition
4.0
0.6
0.26
ms
tHD:DAT
Data Hold Time
0
0
0
ns
tVD:ACK
Data Valid Acknowledge Time (Note 8)
0.3
0.05
0.45
ms
tVD:DAT
Data Valid Time (Note 9)
300
50
50
450
ns
tSU:DAT
Data Setup Time
250
100
50
ns
tLOW
LOW Period of SCL
4.7
1.3
0.5
ms
tHIGH
HIGH Period of SCL
4.0
0.6
0.26
ms
3.45
0.1
0.9
tf
Fall Time of SDA and SCL (Notes 11 and 12)
300
20 + 0.1Cb
(Note 10)
300
120
ns
tr
Rise Time of SDA and SCL
1000
20 + 0.1Cb
(Note 10)
300
120
ns
50
50
50
ns
200
350
550
200
350
550
200
350
550
ns
tSP
Pulse Width of Spikes Suppressed by Input Filter
(Note 13)
PORT TIMING: CL v 100 pF (See Figures 6, 9 and 10)
tV(Q)
Data Output Valid Time
(VDD = 4.5 V to 5.5 V)
(VDD = 2.3 V to 4.5 V)
(VDD = 1.65 V to 2.3 V)
tSU(D)
Data Input Setup Time
100
100
100
ns
tH(D)
Data Input Hold Time
1
1
1
ms
INTERRUPT TIMING: CL v 100 pF (See Figures 9 and 10)
tV(INT_N)
tRST(INT_N)
Data Valid Time
4
4
4
ms
Reset Delay Time
4
4
4
ms
8. tVD:ACK = time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
9. tVD:DAT = minimum time for SDA data out to be valid following SCL LOW.
10. Cb = total capacitance of one bus line in pF.
11. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to VIL of the SCL signal) in order to bridge
the undefined region SCL’s falling edge.
12. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.
This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified tf.
13. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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6
PCA9655E
Device Address
slave address
Before the bus master can access a slave device, it must
send the address of the slave it is accessing and the operation
it wants to perform (read or write) following a START
condition. The slave address of the PCA9655E is shown in
Figure 5. Address pins AD2, AD1, and AD0 choose 1 of 64
slave addresses. To conserve power, no internal pull−up
resistors are provided on AD2, AD1, and AD0.
A logic 1 on the last bit of the first byte selects a read
operation while a logic 0 selects a write operation.
A6
A5
A4
A3
A2
A1
A0
R/W
programmable
Figure 5. PCA9655E device Address
Table 6. PCA9655E ADDRESS MAP
Address Input
Slave Address
AD2
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
HEX
GND
SCL
GND
0
0
1
0
0
0
0
20h
GND
SCL
VDD
0
0
1
0
0
0
1
22h
GND
SDA
GND
0
0
1
0
0
1
0
24h
GND
SDA
VDD
0
0
1
0
0
1
1
26h
VDD
SCL
GND
0
0
1
0
1
0
0
28h
VDD
SCL
VDD
0
0
1
0
1
0
1
2Ah
VDD
SDA
GND
0
0
1
0
1
1
0
2Ch
VDD
SDA
VDD
0
0
1
0
1
1
1
2Eh
GND
SCL
SCL
0
0
1
1
0
0
0
30h
GND
SCL
SDA
0
0
1
1
0
0
1
32h
GND
SDA
SCL
0
0
1
1
0
1
0
34h
GND
SDA
SDA
0
0
1
1
0
1
1
36h
VDD
SCL
SCL
0
0
1
1
1
0
0
38h
VDD
SCL
SDA
0
0
1
1
1
0
1
3Ah
VDD
SDA
SCL
0
0
1
1
1
1
0
3Ch
VDD
SDA
SDA
0
0
1
1
1
1
1
3Eh
GND
GND
GND
0
1
0
0
0
0
0
40h
GND
GND
VDD
0
1
0
0
0
0
1
42h
GND
VDD
GND
0
1
0
0
0
1
0
44h
GND
VDD
VDD
0
1
0
0
0
1
1
46h
VDD
GND
GND
0
1
0
0
1
0
0
48h
VDD
GND
VDD
0
1
0
0
1
0
1
4Ah
VDD
VDD
GND
0
1
0
0
1
1
0
4Ch
VDD
VDD
VDD
0
1
0
0
1
1
1
4Eh
GND
GND
SCL
0
1
0
1
0
0
0
50h
GND
GND
SDA
0
1
0
1
0
0
1
52h
GND
VDD
SCL
0
1
0
1
0
1
0
54h
GND
VDD
SDA
0
1
0
1
0
1
1
56h
VDD
GND
SCL
0
1
0
1
1
0
0
58h
VDD
GND
SDA
0
1
0
1
1
0
1
5Ah
VDD
VDD
SCL
0
1
0
1
1
1
0
5Ch
VDD
VDD
SDA
0
1
0
1
1
1
1
5Eh
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7
PCA9655E
Table 6. PCA9655E ADDRESS MAP
Address Input
Slave Address
AD2
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
HEX
SCL
SCL
GND
1
0
1
0
0
0
0
A0h
SCL
SCL
VDD
1
0
1
0
0
0
1
A2h
SCL
SDA
GND
1
0
1
0
0
1
0
A4h
SCL
SDA
VDD
1
0
1
0
0
1
1
A6h
SDA
SCL
GND
1
0
1
0
1
0
0
A8h
SDA
SCL
VDD
1
0
1
0
1
0
1
AAh
SDA
SDA
GND
1
0
1
0
1
1
0
ACh
SDA
SDA
VDD
1
0
1
0
1
1
1
AEh
SCL
SCL
SCL
1
0
1
1
0
0
0
B0h
SCL
SCL
SDA
1
0
1
1
0
0
1
B2h
SCL
SDA
SCL
1
0
1
1
0
1
0
B4h
SCL
SDA
SDA
1
0
1
1
0
1
1
B6h
SDA
SCL
SCL
1
0
1
1
1
0
0
B8h
SDA
SCL
SDA
1
0
1
1
1
0
1
BAh
SDA
SDA
SCL
1
0
1
1
1
1
0
BCh
SDA
SDA
SDA
1
0
1
1
1
1
1
BEh
SCL
GND
GND
1
1
0
0
0
0
0
C0h
SCL
GND
VDD
1
1
0
0
0
0
1
C2h
SCL
VDD
GND
1
1
0
0
0
1
0
C4h
SCL
VDD
VDD
1
1
0
0
0
1
1
C6h
SDA
GND
GND
1
1
0
0
1
0
0
C8h
SDA
GND
VDD
1
1
0
0
1
0
1
CAh
SDA
VDD
GND
1
1
0
0
1
1
0
CCh
SDA
VDD
VDD
1
1
0
0
1
1
1
CEh
SCL
GND
SCL
1
1
1
0
0
0
0
E0h
SCL
GND
SDA
1
1
1
0
0
0
1
E2h
SCL
VDD
SCL
1
1
1
0
0
1
0
E4h
SCL
VDD
SDA
1
1
1
0
0
1
1
E6h
SDA
GND
SCL
1
1
1
0
1
0
0
E8h
SDA
GND
SDA
1
1
1
0
1
0
1
EAh
SDA
VDD
SCL
1
1
1
0
1
1
0
ECh
SDA
VDD
SDA
1
1
1
0
1
1
1
EEh
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8
PCA9655E
REGISTERS
Command Byte
During a write transmission, the address byte is followed
by the command byte. The command byte determines which
of the following registers will be written or read.
Table 7. COMMAND BYTE
COMMAND
REGISTER
0
Input Port 0
1
Input Port 1
2
Output Port 0
3
Output Port 1
4
Polarity Inversion Port 0
5
Polarity Inversion Port 1
6
Configuration Port 0
7
Configuration Port 1
Registers 0 and 1: Input Port Registers
The externally−applied logic level determines the default
value ‘X’.
These registers are input−only. They reflect the incoming
logic levels of the pins, regardless of whether the pin is
defined as an input or an output by Registers 6 or 7. Writes
to these registers have no effect.
Table 8. INPUT PORT 0 REGISTER
7
6
5
4
3
2
1
0
Symbol
Bit
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 9. INPUT PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
Registers 2 and 3: Output Port Registers
as inputs. In turn, reads from these registers reflect the values
that are in the flip−flops controlling the output selection, not
the actual pin values.
These registers are output−only. They reflect the outgoing
logic levels of the pins defined as outputs by Registers 6 and
7. Bit values in these registers have no effect on pins defined
Table 10. OUTPUT PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 11. OUTPUT PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
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9
PCA9655E
Registers 4 and 5: Polarity Inversion Registers
be inverted when its corresponding bit in these registers is
set (written with ‘1’), and retained when the bit is cleared
(written with a ‘0’).
These registers allow the polarity of the data in the input
port registers to be inverted. The input port data polarity will
Table 12. POLARITY INVERSION PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 13. POLARITY INVERSION PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
Registers 6 and 7: Configuration Registers
high−impedance. When a bit is cleared (written with ‘0’),
the corresponding port pin is enabled as an output. Note that
there is a high value resistor tied to VDD at each pin. At reset,
the device’s ports are inputs with a pull−up to VDD.
The I/O pin directions are configured through the
configuration registers. When a bit in the configuration
registers is set (written with ‘1’), the bit’s corresponding port
pin is enabled as an input with the output driver in
Table 14. CONFIGURATION PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 15. CONFIGURATION PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
Power−on Reset
I/O Port (see Figure 2)
Upon application of power, an internal Power−On Reset
(POR) holds the PCA9655E in a reset condition while VDD
is ramping up. When VDD has reached VPOR, the reset
condition is released and the PCA9655E registers and
SMBus state machine will initialize to their default states.
The reset is typically completed by the POR and the part
enabled by the time the power supply is above VPOR.
However, when doing a power reset cycle, it is necessary to
lower the power supply below 0.2 V, and then restored to the
operating voltage.
When an I/O pin is configured as an input, FETs Q1 and
Q2 are off, creating a high−impedance input with a weak
pull−up (100 kW typ) to VDD. The input voltage may be
raised above VDD to a maximum of 5.5 V.
When the I/O pin is configured as an output, then either Q1
or Q2 is enabled, depending on the state of the Output Port
register. Care should be exercised if an external voltage is
applied to an I/O configured as an output because of the
low−impedance path that exists between the pin and either
VDD or VSS.
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10
PCA9655E
BUS TRANSACTIONS
Writing to the Port Registers
Input Ports, Output Ports, Polarity Inversion Ports, and
Configuration Ports. Data bytes are sent alternately to each
register in a register pair (see Figures 6 and 7). For example,
if one byte is sent to Output Port 1 (register 3), then the next
byte will be stored in Output Port 0 (register 2). There is no
limitation on the number of data bytes sent in one write
transmission. In this way, each 8−bit register may be updated
independently of the other registers.
To transmit data to the PCA9655E, the bus master must
first send the device address with the least significant bit set
to logic 0 (see Figure 5 “PCA9655E device address”). The
command byte is sent after the address and determines
which registers will receive the data following the command
byte.
There are eight registers within the PCA9655E. These
registers are configured to operate as four register pairs:
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
0
0
0
0
0
0
data to port 1
data to port 0
1
0 A 0.7
DATA 0
0.0 A 1.7
acknowledge
from slave
R/W acknowledge
from slave
1.0 A
DATA 1
P
STOP
condition
acknowledge
from slave
write to port
tv(Q)
data out
from port 0
tv(Q)
data out
from port 1
DATA VALID
Figure 6. Write to Output Port Registers
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
data to register
command byte
A
0
0
0
0
0
1
MSB
1
0
R/W acknowledge
from slave
A
data to register
MSB
LSB
DATA 0
acknowledge
from slave
A
acknowledge
from slave
LSB
DATA 1
A
P
STOP
condition
Figure 7. Write to Configuration Registers
Reading the Port Registers
by the PCA9655E (see Figures 8, 9 and 10). Data is clocked
into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be
read but with data alternately coming from each register in
the pair. For example, if you read Input Port 1, then the next
byte read would be Input Port 0. There is no limitation on the
number of data bytes received in one read transmission but
the bus master must not acknowledge the data for the final
byte received.
To read data from the PCA9655E, the bus master must
first send the PCA9655E address with the least significant
bit set to logic 0 (see Figure 5 “PCA9655E device address”).
The command byte is sent after the address and determines
which register will be accessed.
After a restart, the device address must be sent again, but
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
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11
PCA9655E
slave address
SDA
S
A6 A5 A4 A3 A2 A1 A0
START condition
0
A
acknowledge
from slave
R/W
acknowledge
from slave
data from lower or
upper byte of register
slave address
(cont.)
MSB
A6 A5 A4 A3 A2 A1 A0
S
(repeated)
START condition
(cont.)
A
COMMAND BYTE
1
A
data from upper or
lower byte of register
LSB
A
DATA (last byte)
acknowledge
from master
R/W
acknowledge
from slave
MSB
LSB
DATA (first byte)
NA P
no acknowledge
from master
STOP
condition
at this moment master−transmitter becomes master−receiver
and slave−receiver becomes slave−transmitter
Remark: Transfer can be stopped at any time by a STOP condition.
Figure 8. Read from Register
SCL
1 2 3 4 5 6 7 8 9
slave address
I0.x
I1.x
I0.x
I1.x
STOP condition
SDA S A6 A5 A4 A3 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P
START condition
read from port 0
acknowledge
from master
R/W
acknowledge
from slave
acknowledge
from master
acknowledge
from master
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
t v(INT_N)
t rst(INT_N)
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Figure 9. Read from Input Port Register, Scenario 1
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12
PCA9655E
SCL
1 2 3 4 5 6 7 8 9
slave address
R/W
I0.x
SDA S A6 A5A4 A3 A2 A1 A0 1 A
START condition
acknowledge
from slave
DATA 00
I1.x
DATA 10
A
A
acknowledge
from master
tsu(D)
acknowledge
from master
th(D)
I0.x
DATA 03
I1.x
A
acknowledge
from master
DATA 12
STOP condition
1 P
non acknowledge
from master
read from port 0
data into port 0
DATA 00
DATA 01
DATA 02
DATA 03
tsu(D)
th(D)
read from port 1
data into port 1
DATA 10
DATA 11
DATA 12
INT
t v(INT_N)
t rst(INT_N)
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Figure 10. Read from Input Port Register, Scenario 2
Interrupt Output
each 8−bit port is read independently, the interrupt caused by
Port 0 will not be cleared by a read of Port 1 or the other way
around.
Remark: Changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
The open−drain interrupt output is activated when an I/O
pin configured as an input changes state. The interrupt is
deactivated when the input pin returns to its previous state
or when the Input Port register is read (see Figure 9). A pin
configured as an output cannot cause an interrupt. Since
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13
PCA9655E
APPLICATION INFORMATION
V DD
(5 V)
10 kW
10 kW
10 kW
V DD
V DD
MASTER
CONTROLLER
PCA9655E
SCL
SCL
SDA
SDA
INT
SUB−SYSTEM 1
(e.g., temp sensor)
2 kW
INT
IO0_0
SUB−SYSTEM 2
(e.g., counter)
IO0_1
RESET
IO0_2
INT
IO0_3
GND
A
IO0_4
controlled
switch
(e.g., 7SB or FST)
ENABLE
IO0_5
B
IO0_6
IO0_7
SUB−SYSTEM 3
(e.g., alarm system)
IO1_0
IO1_1
10 DIGIT
NUMERIC
KEYPAD
IO1_2
IO1_3
IO1_4
AD2
V DD
IO1_5
AD1
ALARM
IO1_6
IO1_7
AD0
V SS
Device address configured as 0100 000xb for this example.
IO0_0, IO0_2, IO0_3 configured as outputs.
IO0_1, IO0_4, IO0_5 configured as inputs.
IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.
Figure 11. Typical Application
Characteristics of the I2C−Bus
Bit Transfer
The I2C−bus is meant for 2−way, 2−line communication
between different ICs or modules. The two lines are the
serial data line (SDA) and the serial clock line (SCL). Both
lines must be connected to a positive supply via a pull−up
resistor when connected to the output stages of a device.
Data transfer may only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse. Changes in the data line during the
HIGH period of the clock pulse will be interpreted as control
signals (see Figure 12).
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14
PCA9655E
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 12. Bit Transfer
START and STOP Conditions
HIGH. A STOP condition (P) occurs when there is a
LOW−to−HIGH transition of the data line while the clock is
HIGH (see Figure 13).
Both data and clock lines remain HIGH when the bus is
not busy. A START condition (S) occurs when there is a
HIGH−to−LOW transition of the data line while the clock is
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
Figure 13. Definition of START and STOP Conditions
System Configuration
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 14).
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C−BUS
MULTIPLEXER
SLAVE
Figure 14. System Configuration
Acknowledge
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; set−up time and hold time must be taken into
account.
A master receiver signals an end of data to the transmitter
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each 8−bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also, a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
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15
PCA9655E
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
8
S
9
clock pulse for
acknowledgement
START
condition
Figure 15. Acknowledgement of the I2C Bus
TIMING AND TEST SETUP
SDA
tr
tBUF
tHD;STA
tf
tSP
tLOW
SCL
tHD;STA
P
S
tHD;DAT
tHIGH
tSU;STA
tSU;DAT
tSU;STO
Sr
P
Figure 16. Definition of Timing on the I2C Bus
VDD
PULSE
GENERATOR
VI
RL
500 W
VO
VDD
open
GND
DUT
CL
50 pF
RT
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance of Zo of the pulse generators.
Figure 17. Test Circuitry for Switching Times
RL
from output under test
500 W
CL
50 pF
RL
500 W
Figure 18. Load Circuit
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16
S1
2VDD
open
GND
PCA9655E
ORDERING INFORMATION
Package
Shipping†
PCA9655EDWR2G
SOIC−24
(Pb−Free)
1000 / Tape & Reel
PCA9655EDTR2G
TSSOP−24
(Pb−Free)
2500 / Tape & Reel
PCA9655EMTTXG
WQFN24
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
PCA9655E
PACKAGE DIMENSIONS
SOIC−24
CASE 751E−04
ISSUE E
−A−
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
−B−
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
−T−
SEATING
PLANE
22X
G
K
M
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18
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
PCA9655E
PACKAGE DIMENSIONS
24 LEAD TSSOP
CASE 948H
ISSUE A
24X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
2X
24
L/2
13
B
−U−
L
PIN 1
IDENT.
12
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
A
−V−
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
C
0.10 (0.004)
−T− SEATING
PLANE
G
D
H
−W−
DETAIL E
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
N
K
0.25 (0.010)
K1
J1
M
N
F
SECTION N−N
J
DETAIL E
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19
MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PCA9655E
PACKAGE DIMENSIONS
WQFN24 4x4, 0.5P
CASE 485BG
ISSUE A
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
TOP VIEW
A1
SIDE VIEW
DETAIL A
D2
7
24X
ALTERNATE
CONSTRUCTION
A3
DETAIL B
MOLD CMPD
DETAIL B
A
0.10 C
0.08 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉÉ
ÉÉÉ
EXPOSED Cu
0.15 C
NOTE 4
L
L
PIN ONE
REFERENCE
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
B
A
D
C
SEATING
PLANE
MOUNTING FOOTPRINT*
4.30
2.26
K
24X
0.63
1
13
L
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
4.00 BSC
2.00
2.20
4.00 BSC
2.00
2.20
0.50 BSC
0.20
−−−
0.30
0.50
0.00
0.15
E2
2.26
4.30
1
19
e
24X
e/2
BOTTOM VIEW
PACKAGE
OUTLINE
b
0.10 C A B
0.05 C
0.50
PITCH
24X
0.30
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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20
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
PCA9655E/D