MC74LVX259 8−Bit Addressable Latch/1−of−8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74LVX259 is an 8−bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The LVX259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non−addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one−of−eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the LVX259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MC74LVX259 input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74LVX259 to be used to interface 5.0 V circuits to 3.0 V circuits. Features • • • • • • • • • • High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb−Free Packages are Available* http://onsemi.com MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B LVX259 AWLYWW 1 16 LVX 259 ALYW TSSOP−16 DT SUFFIX CASE 948F 1 16 SOEIAJ−16 M SUFFIX CASE 966 LVX259 ALYW 1 A WL or L Y WW or W = = = = Assembly Location Wafer Lot Year Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 2 1 Publication Order Number: MC74LVX259/D MC74LVX259 A0 1 16 4 VCC A0 A1 2 15 RESET A2 3 14 ENABLE ADDRESS INPUTS A1 4 13 DATA IN Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 8 GND 9 Q0 Q1 2 6 Q2 7 9 10 Q3 Q4 Q5 13 DATA IN 11 12 14 ENABLE Figure 1. Pin Assignment A0 1 A1 2 A2 3 4 0 2 5 1 4 6 2 7 3 8 4 13 ID 14 EN 6 15 R 7 Q6 Q7 Figure 2. Logic Diagram BIN/OCT 1 NONINVERTING OUTPUTS PIN 16 = VCC PIN 8 = GND 15 RESET Q4 5 3 A2 Q0 1 10 5 11 12 A0 1 Q1 A1 2 Q2 A2 3 Q0 DMUX 0 0 0 G 7 2 1 2 Q3 3 Q4 4 13 Q5 ID 14 Q6 15 Q7 5 EN 6 R 7 4 Q0 5 Q1 6 Q2 7 Q3 8 Q4 10 Q5 11 Q6 12 Q7 Figure 3. IEC Logic Symbol MODE SELECTION TABLE Enable Reset LATCH SELECTION TABLE Mode Address Inputs Latch Addressed Addressable Latch C B A H Memory L L L Q0 L 8−Line Demultiplexer L L H Q1 L Reset L H L Q2 L H H Q3 H L L Q4 H L H Q5 H H L Q6 H H H Q7 L H H L H http://onsemi.com 2 MC74LVX259 DATA INPUT 13 D D D D 4 5 6 7 Q0 Q1 Q2 Q3 A0 ADDRESS INPUTS 3 TO 8 DECODER A1 D 9 Q4 A2 D ENABLE Q5 14 D D RESET 10 15 Figure 4. Expanded Logic Diagram http://onsemi.com 3 11 12 Q6 Q7 MC74LVX259 MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage −0.5 to +7.0 V VIN Digital Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC +0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current 20 mA IOUT DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air 200 180 mW TSTG Storage Temperature Range VESD ESD Withstand Voltage ILATCHUP JA SOIC Package TSSOP Latchup Performance −65 to +150 °C Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) >2000 >200 >2000 V Above VCC and Below GND at 125°C (Note 4) 300 mA 143 164 °C/W Thermal Resistance, Junction−to−Ambient SOIC Package TSSOP Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A 3. Tested to JESD22−C101−A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage TA Operating Temperature Range, all Package Types tr, tf Input Rise or Fall Time VCC = 3.3 V + 0.3 V http://onsemi.com 4 Min Max Unit 2.0 3.6 V 0 5.5 V 0 VCC V −40 85 °C 0 100 ns/V MC74LVX259 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition −40°C ≤ TA ≤ 85°C TA = 25°C (V) Min Typ Max Min Max Unit VIH Minimum High−Level Input Voltage 2.0 3.0 3.6 0.75 VCC 0.7 VCC 0.7 VCC − − − − − − 0.75 VCC 0.7 VCC 0.7 VCC − − − V VIL Maximum Low−Level Input Voltage 2.0 3.0 3.6 − − − − − − 0.25 VCC 0.3 VCC 0.3 VCC − − − 0.25 VCC 0.3 VCC 0.3 VCC V VOH High−Level Output Voltage IOH = −50 A 2.0 1.9 2.0 − 1.9 − V IOH = −50 A 3.0 2.9 3.0 − 2.9 − IOH = −4 mA 3.0 2.58 − − 2.48 − IOL = 50 A 2.0 − 0.0 0.1 − 0.1 IOL = 50 A 3.0 − 0.0 0.1 − 0.1 IOL = 4 mA 3.0 − − 0.36 − 0.44 VOL Low−Level Output Voltage V IIN Input Leakage Current VIN = 5.5 V or GND 0 to 3.6 − − ±0.1 − ±1.0 A ICC Maximum Quiescent Supply Current (per package) VIN = VCC or GND 3.6 1.0 1.0 2.0 − − A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns −40°C ≤ TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPHL CIN Min Typ Max Min Max Unit VCC = 2.7 V CL = 15pF CL = 50pF − − 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 ns VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF − − 5.6 8.0 8.0 12.0 1.0 1.0 11.0 14.0 Maximum Propagation Delay, Address Select to Output (Figures 6 and 9) VCC = 2.7 V CL = 15pF CL = 50pF − − 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF − − 5.6 8.0 8.0 12.0 1.0 1.0 11.0 14.0 Maximum Propagation Delay, Enable to Output (Figures 7 and 9) VCC = 2.7 V CL = 15pF CL = 50pF − − 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF − − 5.6 8.0 9.0 12.0 1.0 1.0 11.0 14.0 VCC = 2.7 V CL = 15pF CL = 50pF − − 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF − − 5.6 8.0 9.0 12.0 1.0 1.0 11.0 14.0 − 6 10 − 10 Parameter Maximum Propagation Delay, Data to Output (Figures 5 and 9) Maximum Propogation Delay, Reset to Output (Figures 7 and 9) Test Conditions Maximum Input Capacitance ns ns ns pF Typical @ 25°C, VCC = 3.3 V CPD 30 Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 5 MC74LVX259 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ Î ÎÎ ÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TIMING REQUIREMENTS Input tr = tf = 3.0 ns TA = ≤ 85°C TA = 25°C Symbol Parameter tw tsu th tr,, tf Test Conditions Min Typ Max Min Max Unit ns Minimum Pulse Width, Reset or Enable (Figure 8) VCC = 2.7 V 4.5 − − 5.0 − VCC = 3.3 V ± 0.3 V 4.5 − − 5.0 − Minimum Setup Time, Address or Data to Enable (Figure 8) VCC = 2.7 V 4.0 − − 4.0 − VCC = 3.3 V ± 0.3 V 3.0 − − 3.0 − Minimum Hold Time, Enable to Address or Data (Figure 7 or 8) VCC = 2.7 V 2.0 − − 2.0 − VCC = 3.3 V ± 0.3 V 2.0 − − 2.0 − Maximum Input, Rise and Fall Times (Figure 5) VCC = 2.7 V − − 400 − 300 VCC = 3.3 V ± 0.3 V − − 300 − 300 ns ns ns VCC DATA IN tf tr VCC 50% DATA IN GND ADDRESS SELECT VCC 50% GND GND tPLH tPHL VCC 50% GND 50% tPHL OUTPUT Q tPHL OUTPUT Q 50% Figure 5. Switching Waveform Figure 6. Switching Waveform VCC VCC GND DATA IN tw tw 50% 50% VCC RESET 50% tPHL GND tw VCC ENABLE tPHL DATA IN 50% GND GN D tPHL OUTPUT Q OUTPUT Q 50% Figure 7. Switching Waveform Figure 8. Switching Waveform TEST POINT DATA IN OR ADDRESS SELECT VCC OUTPUT 50% th(H) tsu th(H) tsu ENABLE GND DEVICE UNDER TEST CL * VCC 50% GND *Includes all probe and jig capacitance Figure 9. Switching Waveform Figure 10. Test Circuit http://onsemi.com 6 MC74LVX259 ORDERING INFORMATION Package Shipping† MC74LVX259D SOIC−16 48 Units / Rail MC74LVX259DG SOIC−16 (Pb−Free) 48 Units / Rail MC74LVX259DR2 SOIC−16 2500 Tape & Reel MC74LVX259DR2G SOIC−16 (Pb−Free) 2500 Tape & Reel MC74LVX259DT TSSOP−16* 96 Units / Rail MC74LVX259DTR2 TSSOP−16* 2500 Tape & Reel MC74LVX259M SOEIAJ−16 50 Units / Rail MC74LVX259MG SOEIAJ−16 (Pb−Free) 50 Units / Rail MC74LVX259MEL SOEIAJ−16 2000 Tape & Reel MC74LVX259MELG SOEIAJ−16 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7) Tape Size B1 Max 8 mm 4.35 mm (0.179”) 12 mm 8.2 mm (0.323”) 16 mm 24 mm D D1 E F K P P0 P2 R T W 1.5 mm + 0.1 −0.0 (0.059” ( 0 004 +0.004 −0.0) 1.0 mm Min (0.179”) 1.75 mm ±0.1 (0.069 ±0.004”)) 3.5 mm ±0.5 (1.38 ±0.002”) 2.4 mm Max (0.094”) 4.0 mm ±0.10 (0.157 ±0.004”) 4.0 mm ±0.1 (0.157 ±0.004”)) 2.0 mm ±0.1 (0.079 ±0.004”)) 25 mm (0.98”) 0.6 mm (0.024) 8.3 mm (0.327) 5.5 mm ±0.5 (0.217 ±0.002”) 6.4 mm Max (0.252”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.1 mm (0.476”) 7.5 mm ±0.10 (0.295 ±0.004”) 7.9 mm Max (0.311”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.0 mm ±0.10 (0.472 ±0.004”) 16.3 mm (0.642) 20.1 mm (0.791”) 11.5 mm ±0.10 (0.453 ±0.004”) 11.9 mm Max (0.468”) 16.0 mm ±0.10 (0.63 ±0.004”) 24.3 mm (0.957) 1.5 mm Min (0.060) 30 mm (1.18”) 12.0 mm ±0.3 (0.470 ±0.012”) 6. Metric Dimensions Govern−English are in parentheses for reference only. 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity http://onsemi.com 7 MC74LVX259 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 S TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G http://onsemi.com 8 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74LVX259 SOEIAJ−16 M SUFFIX CASE 966−01 ISSUE O 16 LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) http://onsemi.com 9 MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.031 MC74LVX259 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 10 For additional information, please contact your local Sales Representative. MC74LVX259/D