MC74VHC259 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL–Compatible Inputs http://onsemi.com The MC74VHC259 is an 8–bit Addressable Latch fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices while maintaining CMOS low power dissipation. The VHC259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table.. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non–addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one–of–eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the VHC259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MC74VHC259 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC259 to be used to interface 5 V circuits to 3 V circuits. • High Speed: tPD = 7.6 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 2 µA (Max) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC • CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: HBM > 2000 V MARKING DIAGRAMS 16 9 VHC259 AWLYYWW SOIC–16 D SUFFIX CASE 751B 1 8 16 9 VHC259 AWLYWW TSSOP–16 DT SUFFIX CASE 948F 1 8 16 SOIC EIAJ–16 M SUFFIX CASE 966 A L, WL Y, YY W, WW 9 VHC259 ALYW 1 8 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION A0 1 16 VCC A1 2 15 RESET A2 3 14 ENABLE Q0 4 13 DATA IN MC74VHC259DR2 Q1 5 12 Q7 MC74VHC259DT Q2 6 11 Q6 MC74VHC259DTR2 TSSOP–16 Q3 7 10 Q5 MC74VHC259M SOIC EIAJ–16 50 Units/Rail 9 Q4 MC74VHC259MEL SOIC EIAJ–16 2000 Units/Reel GND 8 Device MC74VHC259D Figure 1. Pin Assignment Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 2 1 Package Shipping SOIC–16 48 Units/Rail SOIC–16 2500 Units/Reel TSSOP–16 96 Units/Rail 2500 Units/Reel Publication Order Number: MC74VHC259/D MC74VHC259 A0 ADDRESS INPUTS A1 RESET ENABLE 5 2 6 7 9 10 3 A2 DATA IN 4 1 13 11 12 Q0 Q1 Q2 NONINVERTING OUTPUTS Q3 Q4 Q5 Q6 Q7 PIN 16 = VCC PIN 8 = GND 15 14 Figure 2. Logic Diagram A0 1 A1 2 A2 3 BIN/OCT 1 0 2 1 4 2 4 5 6 7 3 8 4 13 ID 14 5 EN 15 6 R 10 11 12 7 Q0 A0 1 Q1 A1 2 Q2 A2 3 DMUX 0 0 G 7 2 0 1 2 Q3 3 Q4 4 13 Q5 14 Q6 15 Q7 ID 5 EN 6 R 7 4 5 6 7 8 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Figure 3. IEC Logic Symbol LATCH SELECTION TABLE Address Inputs MODE SELECTION TABLE Enable Reset Mode L H Addressable Latch C B A Latch Addressed L L L Q0 H H Memory L L 8–Line Demultiplexer H L Reset L L H Q1 L H L Q2 L H H Q3 H L L Q4 H L H Q5 H H L Q6 H H H Q7 http://onsemi.com 2 MC74VHC259 DATA INPUT 13 D D D D 4 5 6 7 Q0 Q1 Q2 Q3 A0 ADDRESS INPUTS 3 TO 8 DECODER A1 D 9 A2 D ENABLE Q5 14 D D RESET 10 Q4 15 Figure 4. Expanded Logic Diagram http://onsemi.com 3 11 12 Q6 Q7 MC74VHC259 MAXIMUM RATINGS (Note 1.) Symbol Value Unit VCC Positive DC Supply Voltage Parameter –0.5 to +7.0 V VIN Digital Input Voltage –0.5 to +7.0 V VOUT DC Output Voltage –0.5 to VCC +0.5 V IIK Input Diode Current –20 mA IOK Output Diode Current 20 mA IOUT DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air 200 180 mW TSTG Storage Temperature Range –65 to +150 °C VESD ESD Withstand Voltage Human Body Model (Note 2.) Machine Model (Note 3.) Charged Device Model (Note 4.) >2000 >200 >2000 V ILATCH–UP Latch–Up Performance Above VCC and Below GND at 125°C (Note 5.) 300 mA JA Thermal Resistance, Junction to Ambient 143 164 °C/W SOIC Package TSSOP SOIC Package TSSOP 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22–A114–A 3. Tested to EIA/JESD22–A115–A 4. Tested to JESD22–C101–A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit 2.0 5.5 V VCC DC Supply Voltage VIN DC Input Voltage 0 5.5 V VOUT DC Output Voltage 0 VCC V TA Operating Temperature Range, all Package Types –55 125 °C tr, tf Input Rise or Fall Time 0 20 ns/V VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80 ° C 117.8 419,300 TJ = 90 ° C 1,032,200 90 TJ = 100 ° C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110° C Time, Years TJ = 120° C Time, Hours TJ = 130 ° C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 1000 TIME, YEARS Figure 5. Failure Rate vs. Time Junction Temperature http://onsemi.com 4 MC74VHC259 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition (V) Min 1.5 VCCX 0.7 VIH Minimum High–Level Input Voltage 2.0 3.0to 5.5 VIL Maximum Low–Level Input Voltage 2.0 3.0to 5.5 VOH Maximum High–Level Output Voltage VIN = VIH or VIL IOH = –50 µA VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VOL Maximum Low–Level Output Voltage –55°C ≤ TA ≤ 125°C TA = 25°C Typ Max Min Max 1.5 VCCX 0.7 0.5 VCCX 0.3 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 V 0.5 VCCX 0.3 2.0 3.0 4.5 Unit 1.9 2.9 4.4 V V V VIN = VIH or VIL IOL = 50 µA VIN = VIH or VIL IOL = 4 mA IOL = 8 mA 2.48 3.8 2.0 3.0 4.5 0.0 0.0 0.0 3.0 4.5 0.36 0.36 0.1 0.1 0.1 0.1 0.1 0.1 V V 0.44 0.44 IIN Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 4.0 40.0 µA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPHL CIN Parameter Test Conditions Min –55°C ≤ TA ≤ 125°C TA ≤ 85°C TA = 25°C Typ Max Min Max Min Max Unit ns Maximum Propagation Delay, g y D t to Data t Output O t t (Figures 6 and 11) VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 6.0 8.5 8.5 12.5 1.0 1.0 11.5 14.5 1.0 1.0 11.5 14.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.9 7.0 8.0 10.0 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 Maximum Propagation Delay, Address Select to Output (Figures 7 and 11) VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 6.0 8.5 8.5 12.5 1.0 1.0 11.5 14.5 1.0 1.0 11.5 14.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.9 7.0 8.0 10.0 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 Maximum Propagation Delay, g y E bl tto O t t Enable Output (Figures 8 and 11) VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 6.0 8.5 8.5 12.5 1.0 1.0 11.5 14.5 1.0 1.0 11.5 14.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.9 7.0 8.0 10.0 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 Maximum Propagation Delay, g y R Reset t to t Output O t t (Figures 9 and 11) VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 6.0 8.5 8.5 12.5 1.0 1.0 11.5 14.5 1.0 1.0 11.5 14.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.9 7.0 8.0 10.0 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 6 10 Maximum Input Capacitance 10 10 ns ns ns pF Typical @ 25°C, VCC = 5.0V CPD 30 Power Dissipation Capacitance (Note 6.) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 5 MC74VHC259 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ Î ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ Î ÎÎ ÎÎ ÎÎÎ Î ÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ Î ÎÎÎ ÎÎ Î ÎÎ ÎÎÎ Î Î ÎÎÎ ÎÎ ÎÎÎ Î ÎÎ Î ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ TIMING REQUIREMENTS (Input tr = tf = 3.0ns) TA = ≤ 85°C TA = 25°C Test Conditions Min tw Minimum Pulse Width,, Reset or Enable (Fi (Figure 10) VCC = 3.3 ± 0.3V 5.0 5.5 5.5 VCC = 5.0 ± 0.5V 5.0 5.5 5.5 tsu Minimum Setup Time,, Address or Data to Enable (Fi (Figure 10) VCC = 3.3 ± 0.3V 4.5 4.5 4.5 VCC = 5.0 ± 0.5V 3.0 3.0 3.0 th Minimum Hold Time,, Enable to Address or Data (Fi (Figure 8 or 9) VCC = 3.3 ± 0.3V 2.0 2.0 2.0 VCC = 5.0 ± 0.5V 2.0 2.0 2.0 Maximum Input,, Rise and Fall Times (Fi (Figure 6) VCC = 3.3 ± 0.3V 400 300 300 VCC = 5.0 ± 0.5V 200 100 100 Symbol tr, tf Parameter Typ Max Min TA = ≤ 125°C Max Min Max Unit ns ns ns ns VCC tr DATA IN tf VCC 50% DATA IN GND ADDRESS SELECT VCC 50% GND GND tPLH tPHL VCC 50% 50% tPHL OUTPUT Q GND tPHL OUTPUT Q 50% Figure 6. Switching Waveform Figure 7. Switching Waveform VCC VCC GND DATA IN tw ENABLE tw 50% 50% tPHL DATA IN VCC GND OUTPUT Q OUTPUT Q Figure 8. Switching Waveform DATA IN OR ADDRESS SELECT ENABLE tw RESET 50% tPHL GND VCC 50% GND tPHL 50% Figure 9. Switching Waveform TEST POINT VCC 50% th(H) tsu th(H) tsu GND VCC 50% OUTPUT DEVICE UNDER TEST CL* GND *Includes all probe and jig capacitance Figure 10. Switching Waveform Figure 11. Test Circuit http://onsemi.com 6 MC74VHC259 PACKAGE DIMENSIONS SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉ ÇÇÇ ÇÇÇ ÉÉ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A –V– M N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE DETAIL E H D G http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74VHC259 PACKAGE DIMENSIONS SOIC EIAJ–16 M SUFFIX CASE 966–01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.031 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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