ONSEMI MC74VHCT86AD

MC74VHCT86A
Product Preview
Quad 2−Input XOR Gate /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT86A is an advanced high speed CMOS 2−input
Exclusive−OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to
3.0V CMOS Logic while operating at the high−voltage power supply.
The MC74VHCT86A input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows it to be used to interface 5V circuits to 3V circuits. The output
structures also provide protection when VCC = 0V. These input and
output structures help prevent device destruction caused by supply
voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
•
•
•
•
•
•
•
•
•
•
w
High Speed: tPD = 4.8ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2μA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
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14−LEAD SOIC
D SUFFIX
CASE 751A
14−LEAD TSSOP
DT SUFFIX
CASE 948G
14−LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
L
H
H
L
ORDERING INFORMATION
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 1
1
Device
Package
Shipping
MC74VHCT86AD
SOIC
55 Units/Rail
MC74VHCT86ADT
TSSOP
96 Units/Rail
MC74VHCT86AM
SOIC EIAJ
50 Units/Rail
Publication Order Number:
MC74VHCT86A/D
MC74VHCT86A
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
Y1
4
6
5
Y2
Y = A)B
9
8
10
Y3
12
11
13
Y4
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
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MAXIMUM RATINGS*
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
VCC = 0
High or Low State
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
DC Supply Voltage
Characteristics
VCC
2.0
5.5
V
DC Input Voltage
VIN
0.0
5.5
V
VOUT
0.0
0.0
5.5
VCC
V
TA
−55
+85
°C
tr , tf
0
0
100
20
ns/V
DC Output Voltage
VCC = 0
High or Low State
Operating Temperature Range
Input Rise and Fall Time
VCC = 3.3V ± 0.3V
VCC = 5.0V ± 0.5V
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.3
− 0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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2
MC74VHCT86A
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
Min
1.2
2.0
2.0
VIH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA = 25°C
(V)
Typ
TA ≤ 85°C
Max
Min
1.2
2.0
2.0
3.0
4.5
2.9
4.4
VIN = VIH or VIL
IOH = −4mA
IOH = −8mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50μA
3.0
4.5
VIN = VIH or VIL
IOL = 4mA
IOL = 8mA
0.53
0.8
0.8
3.0
4.5
0.0
0.0
Min
Max
1.2
2.0
2.0
0.53
0.8
0.8
VIN = VIH or VIL
IOH = −50μA
TA ≤ 125°C
Max
V
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IIN
Maximum Input
Leakage Current
VIN = 5.5V or GND
0 to
5.5
±0.1
±1.0
±1.0
μA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
2.0
20
40
μA
ICCT
Quiescent Supply
Current
Input: VIN = 3.4V
5.5
1.35
1.50
1.65
mA
IOPD
Output Leakage
Current
VOUT = 5.5V
0.0
0.5
5.0
10
μA
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Cin
Typ
Max
Min
Max
Unit
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
ns
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.8
6.3
6.8
8.8
1.0
1.0
8.0
10.0
4
10
Parameter
Propagation Delay,
A or B to Y
tPLH,
tPHL
Test Conditions
Input Capacitance
Min
TA = − 40 to 85°C
10
pF
Typical @ 25°C, VCC = 5.0V
18
CPD
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
TEST POINT
A or B
3.0V
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
Y
tPHL
CL*
VOH
50% VCC
VOL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
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3
MC74VHCT86A
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
14
8
13
12
3
4
9
8
5
6
7
86A
AWLYWW*
2
10
VHCT
VHCT86A
1
11
ALYW*
5
6
7
1
2
14−LEAD SOIC
D SUFFIX
CASE 751A
3
4
14−LEAD TSSOP
DT SUFFIX
CASE 948G
14
13
12
11
10
9
8
6
7
VHCT86A
AWLYWW*
1
2
3
4
5
14−LEAD SOIC EIAJ
M SUFFIX
CASE 965
*See Applications Note #AND8004/D for date code and traceability information.
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4
MC74VHCT86A
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
14
8
P 7 PL
−B−
1
0.25 (0.010)
7
G
SEATING
PLANE
0.25 (0.010)
T
F
J
M
K
M
M
R X 45°
C
D 14 PL
B
M
B
S
A
S
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5
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7° 0.228 0.244
0.010 0.019
MC74VHCT86A
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G−01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74VHCT86A
PACKAGE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965−01
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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7
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.056
MC74VHCT86A
Notes
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHCT86A/D