SPT7721 8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS TECHNICAL DATA NOVEMBER 8, 2001 FEATURES APPLICATIONS • • • • • • • • • • TTL/CMOS/PECL compatible High conversion rate: 250 MSPS Single +5 V power supply Very low power dissipation: 310 mW Power-down mode +3.0 V/+5.0 V (LVCMOS) digital output logic compatibility • Demuxed output ports RGB video processing Digital communications High-speed instrumentation Projection display systems GENERAL DESCRIPTION The SPT7721 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 310 mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5 V common mode reference is provided on chip for the singleended input mode to minimize external components. AGND DGND AVCC OVDD Data Output Latches BLOCK DIAGRAM The SPT7721 digital outputs are demuxed (double-wide) with both dual-channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0 V and +5.0 V compatible. The SPT7721 is available in a 44-lead TQFP surface mount package over the industrial temperature range of –40 to +85 °C. 8-Bit 250 MSPS ADC VIN+ VIN CLK CLK Common Mode Voltage Reference Data Output Mode Control DA0DA7 DB0DB7 DCLKOUT DCLKOUT 2 +2.5 V VCM PD CLK CLK 2 Reset DMODE1,2 & Reset ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C Supply Voltages AVCC ...................................................................... +6 V OVDD ..................................................................... +6 V Temperatures Operating Temperature ........................... –40 to +85 °C Storage Temperature ............................ –65 to +125 °C Input Voltages Analog Inputs ............................... –0.5 V to VCC +0.5 V Digital Inputs ................................ –0.5 V to VCC +0.5 V Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5.0 V, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL MIN Resolution DC Performance Differential Linearity Error (DLE) Integral Linearity Error (ILE) Best Fit No Missing Codes Analog Input Input Voltage Range (with respect to VIN–) Gain Variation Input Common Mode (VCM) Input Bias Current Input Resistance Input Capacitance Input Bandwidth Offset Error Offset Power Supply Rejection Ratio Timing Characteristics Maximum Conversion Rate Output Delay (Clock-to-Data) (tpd1) Output Delay Tempco Aperture Delay Time (tap) Aperture Jitter Time Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time Single Channel Mode (tpd2) Dual Channel Mode (tpd3) Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 70 MHz ƒIN = 70 MHz Signal-to-Noise Ratio (SNR) ƒIN = 70 MHz ƒIN = 70 MHz ƒIN = 1 kHz +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C +25 °C, ƒIN = 1 kHz +25 °C +25 °C +25 °C +25 °C (–3 dB of FS) MAX UNITS 8 Bits V V V V I –0.70/+1.05 –0.95/+1.5 ±1.7 ±2.25 Guaranteed LSB LSB LSB LSB V VI IV VI V V V VI V ±470 2 2.5 10 50 4 220 ±10 0.5 VI IV V IV IV –40 °C to +85 °C SPT7721 TYP 2.3 250 6 8 22 0.5 2 3.0 10.5 mVP-P % V µA kΩ pF MHz mV mV/V MSPS ns ps/°C ns ps rms V V 2.5 2.5 Clocks Clocks V V 2.5 3.5 Clocks Clocks IV IV 4 5.3 6 6.16 7 7.8 ns ns +25 °C –40 °C to +85 °C VI IV 5.8 5.5 6.4 6.0 Bits Bits +25 °C –40 °C to +85 °C VI IV 42 36 43 40 dB dB SPT7721 2 11/8/01 ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5 V, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL Dynamic Performance Total Harmonic Distortion (THD) +25 °C ƒIN = 70 MHz –40 °C to +85 °C ƒIN = 70 MHz Signal-to-Noise and Distortion (SINAD) +25 °C ƒIN = 70 MHz –40 °C to +85 °C ƒIN = 70 MHz MIN VI IV SPT7721 TYP MAX UNITS –43 –42 –40 –37 dB dB VI IV 37 35 40 38 Power Supply Requirements AVCC Voltage (Analog Supply) OVDD Voltage (Digital Supply) AVCC Current Power Dissipation with Internal Voltage Reference IV IV VI VI 4.75 2.75 5.0 Common Mode Reference Voltage Voltage Tempco Output Impedance Power Supply Rejection Ratio VI V V V 2.45 Clock and Reset Inputs (Differential and Single-Ended) Differential Signal Amplitude (VDIFF) Differential High Input Voltage (VIHD) Differential Low Input Voltage (VILD) Differential Common-Mode Input (VCMD) Single-Ended High Input Voltage (VIH) Single-Ended Low Input Voltage (VIL) VID = 1.5 V Input Current High (IIH) VID = 1.5 V Input Current Low (IIL) VI IV IV IV IV IV VI VI 400 1.4 0 1.2 1.8 –100 –100 Power Down and Mode Control Inputs (Single-Ended) High Input Voltage Low Input Voltage Maximum Input Current Low Maximum Input Current High <4.0 V IV IV VI VI 2.0 0 –100 –100 Digital Outputs Logic "1" Voltage Logic "0" Voltage TR/TF Data IOUT = ±50 µA 62 310 2.5 100 1 63 dB dB 5.25 5.25 70 350 V V mA mW 2.55 V ppm/°C kΩ mV/V 20 20 1.2 +100 +100 mVP-P V V V V V µA µA 10 10 AVCC 1.0 +100 +100 V V µA µA 0.2 V V 5 3.9 4.1 IOH = –0.5 mA IOL = +1.6 mA 10 pF load OVDD = 3 V OVDD = 5 V VI VI OVDD – 0.2 OVDD – 0.06 0.13 V V 3.5 2.0 ns ns OVDD = 3 V OVDD = 5 V V V 1.3 0.7 ns ns TR/TF DCLK = (10 pF load) TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT7721 3 11/8/01 TYPICAL PERFORMANCE CHARACTERISTICS AC Performance vs Temperature AC Performance vs Sample Rate 60 SFDR, SNR, THD, SINAD (dB) SFDR, THD, SNR, SINAD (dB) 60 55 IN = 70 MHz 50 SFDR 45 THD SNR 40 SINAD 35 30 40 20 0 20 40 Temperature (°C) 60 80 55 IN = 70 MHz 50 45 40 50 0 75 3.0 70 2.8 65 60 55 250 Sample Rate (MSPS) 300 2.6 2.4 2.2 50 40 20 0 20 40 Temperature (°C) 60 80 2.0 100 40 Voltage Offset Error vs Temperature mV 200 150 100 AVCC Current Power Down vs Temperature AVCC (mA) AVCC (mA) SINAD 35 AVCC Current vs Temperature 45 SNR THD 30 100 SFDR 0 20 40 Temperature (°C) 60 80 100 80 100 Percent Gain Error vs Temperature 6.0 1.06 4.0 1.05 2.0 1.04 0.0 % 2.0 1.03 1.02 4.0 6.0 40 20 1.01 20 0 20 40 Temperature (°C) 60 80 1.00 100 40 20 0 20 40 Temperature (°C) 60 SPT7721 4 11/8/01 TYPICAL PERFORMANCE CHARACTERISTICS Input Bandwidth Common-Mode Reference Voltage vs VCC 1 2.50 2.49 0 2.48 2.47 dB VCMOUT V 1 2 3 2.41 2.40 100 0 200 300 400 Input Frequency (MHz) 500 600 4.5 4.7 4.9 5.3 5.1 VCC V 5.5 5.7 OVDD Current vs Clock Frequency, Single Mode 60 120 Output VDD=5 V 50 100 Output VDD=5 V 40 mA 80 mA 2.44 2.42 OVDD Current vs Clock Frequency, Dual Mode 60 Output VDD=3 V 30 Output VDD=3 V 20 40 10 20 0 0 50 0 100 150 200 Clock Frequency (MHz) 250 300 0 25 50 125 150 400 mVP-P with 6 pF loads 1000 100 75 Clock Frequency (MHz) Differential Input Common-Mode Operating Range Total Power vs Clock Frequency 6 800 5 OVDD=5 V 700 4 600 Volts Power Dissipation (mW) 2.45 2.43 4 5 2.46 OVDD=3 V Common-Mode Operating Range 2 500 1 400 300 3 0 50 100 150 200 250 0 50 40 300 Clock Frequency (MHz) 20 0 20 40 Temperature (°C) 60 80 100 SPT7721 5 11/8/01 THEORY OF OPERATION The digital decode consists of comparators, exclusive of cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 3.5 clock cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate, no more than three bits at a time are decoded in any half clock cycle. The SPT7721 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two single-bit folding interpolator stages. There are pipelining THAs between each ADC block. The output data mode is controlled by the state of the demux mode inputs. There are three output modes. The analog decode functions are the input buffer, input THAs, three-bit folder, folding interpolators, and pipelining THAs. The input buffer enables the part to withstand railto-rail input signals without latchup or excessive currents and also performs single-ended to differential conversion. All of the THAs have the same basic architecture. Each has a differential pair buffer followed by switched emitter followers driving the hold capacitors. The input THA also has hold mode feedthrough cancellation devices. • All data on bank A with clock rate limited to one-half maximum • Interleaved mode with data alternately on banks A and B on alternate clock cycles • Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can synchronize with the divided clock to select the desired output bank via the differential RESET input. The three MSBs of the ADC are generated in the first three-bit folder block, the output of which drives a differential reference ladder which also sets the full-scale input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange, and underrange. Every other differential pair collector is crosscoupled to generate the eighth scale zero crossings. The middle ADC block generates two bits from the folded signals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the three LSBs to the next half clock cycle. The three LSBs are generated in interpolators that are latched one full clock cycle after the MSBs. The output logic family is LVCMOS with output VDD supply adjustable from 2.7 volts to 5.3 volts. There are also differential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 10 mW. There is a 2.5 V reference to supply common mode for single-ended inputs that is not shut down in power-down mode. Figure 1 – Single Mode Timing Diagram 2.5 CLK Cycles of Latency N VIN N+2 N+1 tap N+3 N+4 N+5 CLK /CLK tpd1 D0D7 (Port A) DCLKOUT N3 tpd2 N2 N1 N N+1 N+2 tpd2 /DCLKOUT SPT7721 6 11/8/01 Figure 2 – Dual Mode Timing Diagram 2.5 CLK Cycles N-2 Vin N N-1 tap of Latency N+1 N+3 N+2 N+4 /CLK Refer to AN7722 CLK 550ps U6-Reset 550ps treset /Reset tpd1 ts tpd1 tpd1 Reset INTERLEAVED DATA OUTPUT N-5 Port A Port B Invalid Data N-4 N-6 tpd2 tpd3 N+1 N-1 N-2 N PARALLEL DATA OUTPUT Port A N-7 N-5 Port B N-6 N-4 Invalid Data N-1 N-2 N tpd2 DCLKOUT /DCLKOUT 2.5 CLK Cycles o f Latenc y N-2 Vin N-1 tap N+1 N N+3 N+2 N+4 /CLK Refer to AN7722 CLK 550ps 550ps U6-Reset treset /Reset tpd1 tpd1 ts tpd1 Reset INTERLEAVED DATA OUTPUT N-4 N-6 Port A Port B N-5 tpd2 N+1 N-1 Invalid Data N-2 N PARALLEL DATA OUTPUT Port A N-6 Port B N-5 N-1 Invalid Data N-2 N tpd1 /DCLKOUT DCLKOUT Data Output Possibilities w/o Reset SPT7721 7 11/8/01 CLK Clock Diff In CLK Reset Reset DMode2 Reset Diff In DA0DA7 VIN+ DCLKOUT SPT7721 50 DGND (3) .01 AGND2 (2) AVCC1 (2) AVCC2 (2) AGND1 (4) VIN Mini-Circuit T1-6T 1) FB = Ferrite bead. It must placed as close to the ADC as possible. 2) All inputs are internally biased: a) DMode1 to GND through 100K Default = interleave dual channel output b) DMode2 to VCC through 50K c) CLK, PD and Rest pins to GND through 100K d) /CLK and /Reset pins to 1.5 V through 5K e) VIN+ and VIN to +2.5 V through 50K 3) All 0.01microfarad capacitors are surface mount caps. They must be placed as close to the respective pin as possible DB0DB7 .01(3x) .01(2x) Notes: Interfacing Logics DCLKOUT OVDD (3) AIN VCMOUT T1 DMode1 Mode Select Figure 3 – Typical Interface Circuit .01(3x) } + FB + 10 +D3/5 10 +A5 TYPICAL INTERFACE CIRCUIT +D3/5 Figure 4 – DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown) Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the SPT7721 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance. R3 VCM Input Voltage (±0.5 V) R3 R + (R3)/2 51 W R2 + VIN 51 W R R VIN+ 15 pF R2 ANALOG INPUT The input of the SPT7721 can be configured in various ways depending on whether a single-ended or differential input is desired. ADC R 51 W + R INPUT PROTECTION The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown in figure 3. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the input attenuates kickback noise from the internal trackand-hold. All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times. POWER SUPPLIES AND GROUNDING The SPT7721 is operated from a single power supply in the range of 4.75 to 5.25 volts. Normal operation is suggested to be 5.0 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible. Figure 4 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input is desired. It is very important to select op amps with a high open-loop gain, a bandwidth high enough so as not to impair the performance of the ADC, low THD, and high SNR. SPT7721 8 11/8/01 POWER DOWN MODE DIGITAL OUTPUTS To save on power, the SPT7721 incorporates a powerdown function. This function is controlled by the signal on pin PD. When pin PD is set high, the SPT7721 enters the power-down mode. All outputs are set to high impedance. In the power-down mode the SPT7721 dissipates 10 mW typically. The output circuitry of the SPT7721 has been designed to be able to support three separate output modes. The demuxed (double-wide) mode supports either parallel aligned or interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 125 MSPS. The output format is straight binary (table I). REFERENCES Table I – Output Data Format To save on parts count, design time, and PC board real estate, the SPT7721 utilizes an internal reference. No other external components are required to implement this feature. Analog Input Output Code D7–D0 +FS 1111 1111 +FS – 1/2 LSB 1111 111Ø +1/2 FS ØØØØ ØØØØ –FS + 1/2 LSB 0000 000Ø –FS 0000 0000 Ø indicates the flickering bit between logic 0 and 1 COMMON MODE VOLTAGE REFERENCE CIRCUIT The SPT7721 has an on-board common-mode voltage reference circuit (VCM). It is 2.5 volts and is capable of driving 50 µA loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. The data output mode is set using the DMODE1 and DMODE2 inputs (pins 32 & 31 respectively). Table II describes the mode switching options. Table II – Output Data Modes CLOCK INPUT Output Mode DMODE1 Parallel Dual Channel Output 0 Interleaved Dual Channel Output 0 Single Channel Data Output (Bank A only 125 MSPS max) 1 The clock input on the SPT7721 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible. For TTL/CMOS single-ended clock inputs, the rise time of the signal also becomes an important consideration. DMODE2 0 1 X EVALUATION BOARD The EB7721/22 evaluation board is available to aid designers in demonstrating the full performance of the SPT7721. This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (AN7721/22) describing the operation of this board, as well as information on the testing of the SPT7721, is also available. Contact the factory for price and availability of the EB7721/22. SPT7721 9 11/8/01 PACKAGE OUTLINE 44-Lead TQFP A INCHES B SYMBOL Pin 1 MIN MAX MILLIMETERS MIN MAX A 0.472 Typ 12.00 Typ B 0.394 Typ 10.00 Typ C 0.394 Typ 10.00 Typ D 0.472 Typ 12.00 Typ Index E C E D 0.031 Typ 0.80 Typ F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.020 0.030 0.500 0.750 J 0.039 Typ 1.00 Typ K 0-7° 0-7° F G H K I J SPT7721 10 11/8/01 PIN ASSIGNMENTS AGND AVCC VCM AVCC AGND VIN VIN+ AGND AVCC AVCC AGND 34 35 36 37 38 39 40 41 42 43 44 AGND 1 33 AGND PD 2 32 DMODE1 CLK 3 31 DMODE2 CLK 4 30 OVDD RESET 5 29 DGND RESET 6 28 DCLKOUT OVDD 7 27 DCLKOUT SPT7721 TOP VIEW 44L TQFP 21 22 DB1 DB2 DB3 DB0 (LSB) 20 19 OVDD DGND DB4 18 23 DA0 (LSB) 11 17 DA5 DA1 DB5 16 24 15 10 DA2 DA6 DA3 DB6 14 DB7 (MSB) 25 DA4 26 9 13 8 12 DGND DA7 (MSB) DB0–DB7 Data output; Bank B. 3 V / 5 V LVCMOS compatible. DCLKOUT Non-Inverted data output clock. 3 V / 5 V LVCMOS compatible. DCLKOUT Inverted data output clock. 3 V / 5 V LVCMOS compatible. CLK Non-Inverted clock input pin; 100k pulldown to AGND, internally CLK Inverted clock input pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally RESET RESET synchronizes the data sampling and data output bank relationship when in Dual Channel Mode (DMODE1 = 0); 100k pulldown to AGND, internally RESET Inverted RESET input pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally DMODE1,2 Internally: 100k pulldown to AGND on DMODE1 50k pullup to VCC on DMODE2 Data Output Mode pins: DMODE1 = 0, DMODE2 = 0: Parallel Dual Channel Output DMODE1 = 0, DMODE2 = 1: Interleaved Dual Channel Output DMODE1 = 1, DMODE2 = X: Single Channel Data Output on Bank A (125 MSPS max) PIN FUNCTIONS Pin Name Description PD VIN+ Non-Inverted Analog Input; nominally 1 VP-P; 100k pullup to VCC and 100k pulldown to AGND, internally Power Down pin; PD = 1 for power-down mode. Outputs set to high impedance in power-down mode; 100k pulldown to AGND, internally VCM 2.5 V Common Mode Voltage Reference Output VIN– Inverted Analog Input; nominally 1 VP-P; 100k pullup to VCC and 100k pulldown to AGND, internally AVCC +5 V Analog Supply OVDD +3 V / +5 V Digital Output Supply AGND Analog Ground DGND Digital Ground DA0–DA7 Data output; Bank A. 3 V / 5 V LVCMOS compatible. ORDERING INFORMATION PART NUMBER SPT7721SIT TEMPERATURE RANGE PACKAGE –40 to +85 °C 44L TQFP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT7721 11 11/8/01