SPT7610 6-BIT, 1 GSPS FLASH A/D CONVERTER JANUARY 21, 2002 FEATURES APPLICATIONS • • • • • • • • • • • • • 1:2 demuxed ECL-compatible outputs 1.0 GSPS conversion rate Wide input bandwidth: 1.4 GHz Low input capacitance: 8 pF Metastable errors reduced to 1 LSB Monolithic construction Binary/Two’s complement output GENERAL DESCRIPTION The SPT7610 is a full parallel (flash) analog-to-digital converter capable of digitizing full-scale (0 to –1 V) inputs into six-bit digital words at an update rate of 1 GSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data-ready outputs to ease the task of data capture. The SPT7610’s wide input bandwidth and low capacitance eliminate the need BLOCK DIAGRAM Radar, EW, ECM Direct RF down-conversion Microwave modems Industrial ultrasound Transient capture Test and measurement for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7610 operates from a single –5.2 V supply, with a nominal power dissipation of 2.75 W. The SPT7610 is available in a 44L hermetic cerquad surface-mount package in the industrial temperature range (–40 °C to +85 °C). CLKCLK CLOCK BUFFER Analog V RT Input Preamp DEMUX CLOCK BUFFER Comparator 64 48 33 VRM 32 17 V R1 16 D4B D3B D5 (MSB) D2B D1B D4 D3 D2 D1 D0B D6A D5A D4A D3A D2A D1A 2 1 VRB DO (LSB) TEST D5B ECL OUTPUT BUFFERS AND LATCHES V R3 TESTABILITY D6B D6 (OVR) 1:2 DEMULTIPLEXER 49 64 TO 6 BIT DECODER WITH METASTABLE ERROR CORRECTION 63 DRB (DATA READY) DRB (DATA READY) D6B (OVR) D5B (MSB) D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D6A (OVR) D5A (MSB) D4A D3A D2A D1A D0A (LSB) D0A MINV LINV BANK B BANK A ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Output Digital Output Current ................................... 0 to –25 mA Supply Voltages Negative Supply Voltage (AVEE TO GND) . –7.0 to +0.5 V Ground Voltage Differential ........................ –0.5 to +0.5 V Temperature Operating Temperature, Ambient ............... –40 to +85 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ............................... –65 to +150 °C Input Voltage Analog Input Voltage ................................ +0.5 V to AVEE Reference Input Voltage ........................... +0.5 V to AVEE Digital Input Voltage .................................. +0.5 V to AVEE Reference Current VRT to VRB ............................ +20 mA Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVEE = –5.2 V, VRB = –1.00 V, VRM = –0.5 V, VRT = 0.00 V, ƒCLK = 1000 MSPS, Duty Cycle = 50%, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL Resolution MIN MAX 6 DC Accuracy Integral Linearity Differential Linearity No missing codes VI VI VI –0.5 –0.5 Analog Input Offset Error VRT Offset Error VRB Input Voltage Range Input Capacitance Input Resistance Input Bias Current Bandwidth Input Slew Rate Clock Synchronous Input Currents VI VI VI V V VI V V V –30 –30 –1 Over Full Input Range Small Signal Power Supply Requirements Supply Current Power Dissipation VI VI Reference Inputs Ladder Resistance Reference Bandwidth VI V Digital Outputs Digital Output High Voltage Digital Output Low Voltage SPT7610 TYP R1 = 50 Ω to –2 V R1 = 50 Ω to –2 V Digital Inputs Digital Input High Voltage (CLK, NCLK) Digital Input Low Voltage (CLK, NCLK) Clock Input Swing (CLK, NCLK) Maximum Sample Rate Clock Low Width, TPW0 Clock High Width, TPW1 UNITS Bits +0.5 +0.5 LSB LSB +30 +30 0.0 mV mV Volts pF kΩ µA GHz V/ns µA Guaranteed 8 50 200 1.4 5 2 400 550 2.85 770 4.0 mA W 60 80 100 120 Ω MHz VI VI –1.2 –0.9 –1.8 VI –1.5 Volts Volts –1.1 –0.7 Volts VI –2.0 –1.5 Volts IV VI VI VI 100 1000 0.5 0.5 700 1200 0.4 0.4 mV MSPS ns ns SPT7610 2 1/21/02 ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVEE = –5.2 V, VRB = –1.00 V, VRM = –0.5 V, VRT = 0.00 V, ƒCLK = 1000 MSPS, Duty Cycle = 50%, unless otherwise specified. PARAMETERS Timing Characteristics Clock to Data Ready delay (tdr) Data Bank A Data Bank B Clock to Output Data (tod) Data Bank A Data Bank B Output Data to Data Ready (todr) Data Bank A Data Bank B Output Data Skew (tosk) Aperture Jitter Acquisition Time TEST CONDITIONS TEST LEVEL MIN SPT7610 TYP MAX UNITS +25 °C case +25 °C case V V 1.68 1.73 ns ns +25 °C case +25 °C case V V 2.14 2.00 ns ns –40 to 85 °C case –40 to 85 °C case –40 to 85 °C case IV IV IV V V 1.54 1.73 2 250 ns ns ps ps ps 45 34 dB dB Dynamic Performance Spurious Free Dynamic Range (SFDR) ƒIN = 250 MHz ƒIN = 400 MHz Signal-to-Noise and Distortion (SINAD) ƒIN = 250 MHz ƒIN = 400 MHz Signal to Noise Ratio (SNR) ƒIN = 250 MHz ƒIN = 400 MHz Total Harmonic Distortion (THD) ƒIN = 250 MHz ƒIN = 400 MHz TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. –150 V V VI VI 31 28 34 32 dB dB VI VI 33 32 36 36 dB dB VI VI LEVEL I II III IV V VI 150 –40 –34 –37 –30 dB dB TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. Unless otherwise noted, all test are pulsed tests; therefore, TJ = TC = TA. SPT7610 3 1/21/02 GENERAL OVERVIEW The top reference is typically 0 V or connected to AGND (analog ground). The device has top force and sense pins (VRFT and VRST) that are internally connected together. These voltage force and sense pins can be used to minimize the voltage drop across the parasitic line resistance. The SPT7610 is an ultra high-speed monolithic 6-bit parallel flash A/D converter. The nominal conversion rate is 1 GSPS, and the analog bandwidth is typically 1.4 GHz. A major advance over previous flash converters is the inclusion of 64 input preamplifiers between the reference ladder and input comparators. (See the block diagram.) This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The bottom reference is typically –1 V. The device also has bottom force and sense pins (VRFB and VRSB) that are internally connected together. These can also be used to minimize the voltage drop across the parasitic line resistance. Three additional reference taps (VR3 = –0.25 V typ, VRM = –0.5 V typ, and VR1 = –0.75 V typ) are brought out. These taps can be used to control the linearity error. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges. This makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to “trip” into or out of the active state. This gain reduces metastable states that can cause errors at the output. All logic levels are compatible with both 10K ECL or 100K ECL. It is recommended that the clock input be driven differentially (CLK and NCLK) to improve noise immunity and reduce aperture jitter. The digital outputs are split into two banks of 6-bit words and an overrange bit. Each bank is updated at 1/2 of the clock rate and is 180° out of phase from the other. The differential data ready signals for each bank are provided to accurately latch each data bank into the register. The output data is in a straight binary, inverted binary, two’s complement or inverted two’s complement format. Figure 1 shows a timing diagram of the device and shows the input-to-output relationship, clock-to-output delay and output latency. The SPT7610 has a built-in offset in the ÷2 clock divider (D Flip-Flop) to assure that output bank A will come up first after power turn on. The SPT7610 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 Ω loads. Only one –5.2 V power supply is required. Two external references are applied across the internal reference ladder that has a resistance of 80 Ω typical (60 Ω minimum). SPT7610 4 1/21/02 Figure 1 – Timing Diagram 1 nsec VIN N+1 N N+5 N+2 N+4 N+3 CLK (1 GHz) tdrA DRA todA DRA N2 Data Bank A N OutputA Skew (toskA) todB tdrB N+2 DOADRA Delay (todrA) DRB DRB Data Bank B N1 N3 N+1 OutputB Skew (toskB) DOBDRB Delay (todrB) Figure 2 – Test Mode Timing Diagram FIRST POWER RISING EDGE ON 8 1 9 7 10 6 2 VIN 3 5 11 4 CLK IN tsu LOGIC LOW TEST ADC (Normal Operation) ADC (Normal Operation) TEST MODE tdr DRA NDRA tod OUTPUT BANK A (DA0-6) INVALID DATA Bank A Test Pattern 1: - Even Bits = Hi - Odd Bits = Low 1 INVALID DATA Bank A Test Pattern 2: - Even Bits = Low - Odd Bits = Hi 9 7 DRB tdr NDRB tod OUTPUT BANK B (DB0-6) INVALID DATA INVALID DATA Bank B Test Pattern 1: - Even Bits = Hi - Odd Bits = Low 2 Bank B Test Pattern 2: - Even Bits = Low - Odd Bits = Hi 8 SPT7610 5 1/21/02 Figure 3 – Typical Interface Circuit VIN** 50 W VIN DRB DRB (DATA READY) VIN DRB DRB (DATA READY) DRA DRA (DATA READY) VRTF R * 22 W 5.2 V 2N2907 * VR1 D6A (OVR) D5A (MSB) D4A D3A D2A D1A D0A (LSB) SPT7610 VRBS VRBF 5.2 V CLK U2 MINV 5.2 V LINV 5.2 V Test 5.2 V NCLK 50 W AVEE 50 W 2 V Pulldown (Analog) * DGND +U1 VRM 50 W * VR3 50 W 22 W * AGND + U1 Convert D6B (OVR) D5B (MSB) D4B D3B D2B D1B D0B (LSB) VRTS R 2.0 V Reference DRA (DATA READY) DRA .1 µF 2.0 V Pulldown (Digital) FB = Ferrite bead U1 = TLV2464 or equivalent with low offset/noise. R = 1 kW; 0.05% matched or better = AGND FB = DGND 5.2 V U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver. * = 2.2 µF Tantalum Capacitor, 0.1 µF and 100 pF chip capacitors. ** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver. TYPICAL INTERFACE CIRCUIT ANALOG INPUT: VIN The typical interface circuit is shown in figure 3. External reference taps are provided for correcting integral nonlinearity errors. These taps can be actively driven to reduce these errors. (See the Reference Inputs discussion below.) The SPT7610 evaluation board application note contains more details on interfacing the SPT7610. The function of each pin and external connections to other components is as follows: There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7610 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. POWER SUPPLY PINS: AVEE, AGND, DGND CLOCK INPUTS: CLK, NCLK AVEE is the supply pin with AGND as ground for the device. The AVEE power supply pin should be bypassed as close to the device as possible with a 10 µF tantalum capacitor, in parallel with 100 pF and .01 µF chip capacitors. Place the 100 pF chip capacitor closest to the SPT7610. Digital ground (DGND) is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 3. The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. SPT7610 6 1/21/02 DIGITAL OUTPUTS: D0 TO D6, DR, NDR (A AND B) ladder taps are typically bypassed to add noise suppression as shown in figure 3 or may be driven with op amps to adjust integral linearity. The digital outputs can drive 50 Ω to ECL levels when pulled down to –2 V. When pulled down to –5.2 V, the outputs can drive 130 Ω to 1 kΩ loads. Fairchild recommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. SPT7610 TEST MODE FUNCTION: TEST PIN The SPT7610 supports a special test mode function that overrides the SPT7610’s internal data output latch stage and exercises the digital outputs in an alternating test pattern. This enables the user to test digital interface logic downstream from the SPT7610 with a known set of digital test patterns. BINARY AND TWO’S COMPLEMENT OUTPUT: MINV, LINV Control pins are provided that enable selection of one of four digital output formats. (Table I shows selection of these output formats as a function of the MINV and LINV pins.) When the MINV pin is high, the MSB output is inverted and when it is low, the it is noninverted. Likewise, when the LINV pin is high, the LSB output is inverted and when it is low, the it is noninverted. The user can select either binary, inverted binary, two’s complement or inverted two’s complement digital output format. Test mode pin 3 controls the SPT7610 mode of operation such that when it is low, the SPT7610 operates in normal mode. When test mode pin 3 is brought high, the SPT7610 will begin to output test pattern 1 (table II) on the next rising edge of the clock. (See figure 2.) It will output the test patterns alternating between test pattern 1 and test pattern 2 as long as test mode pin 3 is held high. The minimum set-up time (tsu) can be as low as 0 nsec. REFERENCE INPUTS: VRBF, VRBS, VR1, VRM, VR3, VRTF, VRTS Only the digital output stage is involved in the test mode operation. All ADC stages before the digital output stage continue normal data conversion operation while the test mode is active. When test mode pin 3 is brought back low, the SPT7610 will resume output of valid data on the next rising edge of the clock. The valid data output will correspond to a two-clock-cycle pipeline delay as shown in figure 2. There are two reference inputs and three external reference voltage taps. These are –1.0 V VRBF (bottom force) and VRBS (bottom sense), –0.75 V VR1 (1/4 tap), –0.5 V VRM (mid-point tap), –0.25 V VR3 (3/4 tap) and 0.0 V (AGND) VRTF (top force) and VRTS (top sense). The top reference pin is normally tied to analog ground (AGND) and the bottom reference pin can be driven by an op amp as shown in figure 3. Table II – SPT7610 Test Mode Output Bit Patterns The reference voltage taps can be used to control integral linearity over temperature. The mid-point reference tap (VRM) is normally driven by an op amp to insure temperature stable operation or may be bypassed for limited temperature operation. The 1/4 (VR1) and 3/4 (VR3) reference Table I – Output Coding Table –1 V + 1/2 LSB –0.5 V 0 V – 1/2 LSB 0V 1 Tie D5 D4 D3 D2 D1 D0 Test Pattern 1 1 0 1 0 1 0 1 Test Pattern 2 0 1 0 1 0 1 0 BINARY TRUE ANALOG INPUT VOLTAGE D6 TWOs COMPLEMENT INVERTED TRUE INVERTED MINV=LINV=0 MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1 D6 D5_______D0 D5______D0 0 0 0 0 0 0 0 0 0 D5______D0 D5______D0 1 1 1 1 1 1 1000000 0111111 0 0 0 0 0 1 1 1 1 1 1 0 1000001 0111110 0111111 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 MINV/LINV to GND for logic 1. 2 Float MINV/LINV for logic 0. (MINV/LINV are internally pulled down to –5.2 V.) SPT7610 7 1/21/02 THERMAL MANAGEMENT Adequate heat sinking and air flow must be provided to keep the die temperature below +150 °C. This device is packaged with the cavity up (the die is on the bottom of the package). Therefore, Fairchild recommends that the device be heat sinked by contacting the bottom of the package through a hole in the circuit board. The thermal coefficients of the SPT7610 (44L cerquad) are as follows: θja = +78 °C/W (junction to ambient in still air with no heat sink) θjc = +4 °C/W (junction to case) SUBCIRCUIT SCHEMATICS Figure 3A – Input Circuit Figure 3B – Output Circuit Figure 3C – Clock Input AGND AGND AGND VIN DGND Vr CLK CLK Data Out AVEE AVEE SPT7610 8 1/21/02 PACKAGE OUTLINE 44-Lead Cerquad INCHES SYMBOL C A A D B MIN MAX 0.551 typ MILLIMETERS MIN MAX 14.0 typ B 0.685 0.709 17.40 18.00 C 0.037 0.041 0.94 1.04 D E F G H 0.016 typ 0.008 typ 0.027 0.051 0.006 typ 0.080 0.150 0.41 typ 0.20 typ 0.69 1.30 0.15 typ 2.03 3.81 A B 05° H G E F SPT7610 9 1/21/02 PIN ASSIGNMENTS PIN FUNCTIONS VRTF AVEE VR3 AGND VIN VIN AGND VRM VR1 AVEE VRBF Name 44 43 42 41 40 39 38 37 36 35 34 VRBS MINV Test AGND AVEE D6A D5A D4A D3A DGND D2A 1 2 3 4 5 6 7 8 SPT7610 Top View 9 10 11 33 32 31 30 29 28 27 26 25 24 23 VRTS AGND CLK NCLK AGND LINV AVEE DRB NDRB D0B D1B 12 13 14 15 16 17 18 19 20 21 22 Function AVEE Negative Supply; nominally –5.2 V AGND Analog Ground VRTF Reference Voltage Force Top; nominally 0 V VRTS Reference Voltage Sense Top VRM Reference Voltage Middle; nominally –0.5 V VRBF Reference Voltage Force Bottom; nominally –1.0 V VRBS Reference Voltage Sense Bottom VIN Analog Input Voltage; can be either Voltage or Sense DGND Digital Ground D0–D5A Data Output Bank A D0–D5B Data Output Bank B DRA Data Ready Bank A DGND D2B D3B D4B D5B D6B DGND DRA NDRA D0A D1A NDRA Not Data Ready Bank A DRB Data Ready Bank B NDRB Not Data Ready Bank B D6A Overrange Output Bank A D6B Overrange Output Bank B CLK Clock Input NCLK Clock Input MINV MSB Control Pin LINV LSB Control Pin TEST Test Control Pin VR1 Reference Voltage 1/4, nominally –0.75 V VR3 Reference Voltage 3/4, nominally –0.25 V ORDERING INFORMATION PART NUMBER SPT7610SIQ TEMPERATURE RANGE –40 to +85 °C PACKAGE 44L Cerquad DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT7610 10 1/21/02