ONSEMI MC74LCX540DT

MC74LCX540
Low−Voltage CMOS
Octal Buffer
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Inverting)
The MC74LCX540 is a high performance, inverting octal buffer
operating from a 2.3 to 3.6 V supply. This device is similar in function
to the MC74LCX240, while providing flow through architecture.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX540 inputs to be safely driven from 5 V devices. The
MC74LCX540 is suitable for memory address driving and all TTL
level bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OE1, OE2) inputs, when HIGH, disables the outputs by placing them
in a HIGH Z condition.
•
•
•
MARKING
DIAGRAMS
20
20
1
Designed for 2.3 to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
Pb−Free Packages are Available*
SOIC−20
DW SUFFIX
CASE 751D
LCX540
AWLYYWW
1
20
20
Features
•
•
•
•
•
•
•
•
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1
LCX
540
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
1
20
20
1
SOEIAJ−20
M SUFFIX
CASE 967
1
A
L, WL
Y, YY
W, WW
=
=
=
=
74LCX540
AWLYWW
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 5
1
Publication Order Number:
MC74LCX540/D
MC74LCX540
OE1
OE2
1
19
D0
VCC
OE2
O0
O1
O2
O3
O4
O5
O6
O7
20
19
18
17
16
15
14
13
12
11
D1
D2
D3
1
2
3
4
5
6
7
8
9
10
OE1
D0
D1
D2
D3
D4
D5
D6
D7
GND
D4
Figure 1. Pinout: 20−Lead (Top View)
D5
D6
PIN NAMES
D7
Pins
Function
OEn
Dn
On
Output Enable Inputs
Data Inputs
3−State Outputs
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
O0
O1
O2
O3
O4
O5
O6
O7
Figure 2. LOGIC DIAGRAM
TRUTH TABLE
INPUTS
OUTPUTS
OE1
OE2
Dn
On
L
L
L
H
L
L
H
L
X
H
X
Z
H
X
X
Z
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions are Acceptable
For ICC reasons, DO NOT FLOAT Inputs
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2
MC74LCX540
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VI
VO
Value
Condition
Unit
−0.5 to +7.0
V
DC Input Voltage
−0.5 ≤ VI ≤ +7.0
V
DC Output Voltage
−0.5 ≤ VO ≤ +7.0
Output in 3−State
V
−0.5 ≤ VO ≤ VCC + 0.5
Note 1
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
2.0
1.5
3.3
3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
HIGH Level Output Current, VCC = 3.0 V − 3.6 V
−24
mA
IOL
LOW Level Output Current, VCC = 3.0 V − 3.6 V
24
mA
IOH
HIGH Level Output Current, VCC = 2.7 V − 3.0 V
−12
mA
IOL
LOW Level Output Current, VCC = 2.7 V − 3.0 V
TA
Operating Free−Air Temperature
t/V
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
Operating
Data Retention Only
(HIGH or LOW State)
(3−State)
12
mA
−40
+85
°C
0
10
ns/V
ORDERING INFORMATION
Package
Shipping†
MC74LCX540DWR2
SOIC−20
1000 Tape & Reel
MC74LCX540DR2G
SOIC−20
(Pb−Free)
1000 Tape & Reel
MC74LCX540DT
TSSOP−20*
75 Units / Rail
MC74LCX540DTR2
TSSOP−20*
2000 Tape & Reel
MC74LCX540MEL
SOEIAJ−20
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74LCX540
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
Condition
Min
VIH
HIGH Level Input Voltage (Note 2)
2.7 V ≤ VCC ≤ 3.6 V
2.0
VIL
LOW Level Input Voltage (Note 2)
2.7 V ≤ VCC ≤ 3.6 V
VOH
HIGH Level Output Voltage
VOL
Characteristic
LOW Level Output Voltage
Max
Unit
V
0.8
2.7 V ≤ VCC ≤ 3.6 V; IOH = −100 A
VCC − 0.2
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
V
V
2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 A
0.2
VCC = 2.7 V; IOL= 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
V
VCC = 3.0 V; IOL = 24 mA
0.55
II
Input Leakage Current
2.7 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5.0
A
IOZ
3−State Output Current
2.7 ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 5.5 V;
VI = VIH or V IL
±5.0
A
IOFF
Power−Off Leakage Current
VCC = 0 V; VI or VO = 5.5 V
10
A
ICC
Quiescent Supply
y Current
2.7 ≤ VCC ≤ 3.6 V; VI = GND or VCC
10
A
2.7 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±10
A
500
A
ICC
Increase in ICC per Input
2.7 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500)
Limits
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V
Symbol
Parameter
VCC = 2.7 V
Waveform
Min
Max
Max
Unit
tPLH
tPHL
Propagation Delay
Input to Output
1
1.5
1.5
6.5
6.5
7.5
7.5
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
1.5
8.5
8.5
9.5
9.5
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
7.5
7.5
8.5
8.5
ns
tOSHL
tOSLH
Output−to−Output Skew (Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
VOLP
Dynamic LOW Peak Voltage (Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
Min
Typ
0.8
Max
Unit
V
VOLV
Dynamic LOW Valley Voltage (Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
0.8
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
CPD
Power Dissipation Capacitance
Condition
Typical
Unit
VCC = 3.3 V, VI = 0 V or VCC
7
pF
VCC = 3.3 V, VI = 0 V or VCC
8
pF
10 MHz, VCC = 3.3V, VI = 0 V or VCC
25
pF
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4
MC74LCX540
2.7 V
Dn
1.5 V
1.5 V
0V
tPHL
tPLH
1.5 V
On
VOH
1.5 V
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
1.5 V
OEn
0V
tPZH
tPHZ
VCC
VOH − 0.3 V
1.5 V
On
≈0V
tPZL
tPLZ
≈ 3.0 V
1.5 V
On
VOL + 0.3 V
GND
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC Waveforms
VCC
PULSE
GENERATOR
R1
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
GND
CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500 or equivalent
RT = ZOUT of pulse generator (typically 50 )
Figure 4. Test Circuit
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5
6V
OPEN
GND
MC74LCX540
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 h
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
B
B
0.25
M
T A
B
S
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
A
B
M
D
e
18X
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
SEATING
PLANE
A1
C
T
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
L
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC74LCX540
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE O
20
LE
11
Q1
E HE
1
M
L
10
DETAIL P
Z
D
VIEW P
e
A
c
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
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7
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.032
MC74LCX540
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
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Phone: 81−3−5773−3850
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8
For additional information, please contact your
local Sales Representative.
MC74LCX540/D