MC74VHC138 3--to--8 Line Decoder The MC74VHC138 is an advanced high speed CMOS 3--to--8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs (A0 -- A2) determine which one of the outputs (Y0 -- Y7) will go Low. When enable input E3 is held Low or either E2 or E1 is held High, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • • • • • • • • • • • • High Speed: tPD = 5.7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 122 FETs or 30.5 Equivalent Gates These devices are available in Pb--free package(s). Specifications herein apply to both standard and Pb--free devices. Please see our website at www.onsemi.com for specific Pb--free orderable part numbers, or contact your local ON Semiconductor sales office or representative. http://onsemi.com MARKING DIAGRAMS 16 9 VHC138 AWLYYWW SOIC--16 D SUFFIX CASE 751B 1 8 16 9 VHC 138 AWLYWW TSSOP--16 DT SUFFIX CASE 948F 1 8 16 SOIC EIAJ--16 M SUFFIX CASE 966 A WL YY WW A WL Y WW 9 VHC138 ALYW 1 8 = Assembly Location = Wafer Lot = Year = Work Week = Assembly Location = Wafer Lot = Year = Work Week A L Y W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC74VHC138D SOIC--16 48 Units/Rail MC74VHC138DR2 SOIC--16 2500 Units/Reel TSSOP--16 96 Units/Rail MC74VHC138DT MC74VHC138DTR2 TSSOP--16 © Semiconductor Components Industries, LLC, 2006 March, 2006 -- Rev. 4 1 2500 Units/Reel MC74VHC138M SOIC EIAJ--16 48 Units/Rail MC74VHC138MEL SOIC EIAJ--16 2000 Units/Reel Publication Order Number: MC74VHC138/D MC74VHC138 PIN ASSIGNMENT A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 E1 4 13 Y2 E2 5 12 Y3 E3 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 FUNCTION TABLE Inputs LOGIC DIAGRAM Outputs E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X H X H X X X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L H H L H L H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L L H H L H L H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L A0 SELECT INPUTS A1 A2 ENABLE INPUTS E3 E2 E1 H = high level (steady state); L = low level (steady state); X = don’t care http://onsemi.com 2 1 2 3 6 5 4 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 ACTIVE--LOW OUTPUTS MC74VHC138 EXPANDED LOGIC DIAGRAM 15 14 13 1 A0 12 2 A1 11 3 A2 10 Y0 Y1 Y2 Y3 Y4 Y5 5 E2 4 E1 9 7 6 E3 IEC LOGIC DIAGRAM A0 1 A1 2 A2 3 BIN/OCT 1 0 6 E2 5 E1 4 A0 1 A1 2 A2 3 2 1 14 Y1 4 2 13 Y2 3 12 Y3 4 11 Y4 & E3 15 Y0 EN 2 & 5 10 Y5 E3 6 6 9 Y6 E2 5 7 Y7 E1 4 7 DMUX 0 http://onsemi.com 3 0 G 7 0 15 Y0 1 14 Y1 2 13 Y2 3 12 Y3 4 11 Y4 5 10 Y5 6 9 Y6 7 7 Y7 Y6 Y7 MC74VHC138 MAXIMUM RATINGS* Symbol Value Unit VCC DC Supply Voltage Parameter – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to VCC + 0.5 V IIK Input Diode Current -- 20 mA IOK Output Diode Current ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C SOIC Packages† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. †Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature tr, tf Input Rise and Fall Time VCC = 3.3V ±0.3V VCC =5.0V ±0.5V Min Max Unit 2.0 5.5 V 0 5.5 V 0 VCC V -- 55 + 125 _C 0 0 100 20 ns/V The θJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80 ° C 117.8 TJ = 90 ° C 1,032,200 TJ = 100 ° C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110° C Time, Years TJ = 120° C Time, Hours TJ = 130 ° C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 TIME, YEARS Figure 1. Failure Rate vs. Time Junction Temperature http://onsemi.com 4 1000 MC74VHC138 DC ELECTRICAL CHARACTERISTICS Test Conditions Min 1.5 2.1 3.15 3.85 Symbol Parameter VIH Minimum High--Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low--Level Input Voltage 2.0 3.0 4.5 5.5 VOH Minimum High--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = -- 50 μA VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VOL Maximum Low--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 50 μA TA = 25°C VCC (V) Typ TA = ≤ 85°C Max Min 0.5 0.9 1.35 1.65 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 2.0 3.0 4.5 Max 1.5 2.1 3.15 3.85 2.0 3.0 4.5 0.0 0.0 0.0 TA = ≤ 125°C Min Max 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 V 0.5 0.9 1.35 1.65 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 ± 1.0 μA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 4.0 40.0 40.0 μA TA = -- 40 to 85°C TA = -- 55 to 125°C AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Symbo l tPLH, tPHL tPLH, tPHL tPLH, tPHL CIN TA = 25°C Parameter Min Test Conditions Typ Max Min Max Min Max Unit ns Maximum Propagation Delay, A to Y VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 8.2 10.0 11.4 15.8 1.0 1.0 13.5 18.0 1.0 1.0 13.5 18.0 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 5.7 7.2 8.1 10.1 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 Maximum Propagation Delay, E3 to Y VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 8.1 10.6 12.8 16.3 1.0 1.0 15.0 18.5 1.0 1.0 15.0 18.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 5.6 7.1 8.1 10.1 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 Maximum Propagation Delay, E2 or E1 to Y VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 8.2 10.7 11.4 14.9 1.0 1.0 13.5 17.0 1.0 1.0 13.5 17.0 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 5.8 7.3 8.1 10.1 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 4 10 Maximum Input Capacitance 10 10 ns ns pF Typical @ 25°C, VCC = 5.0V 34 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD ¯ VCC ¯ fin + ICC. CPD is used to determine the no--load dynamic power consumption; PD = CPD ¯ VCC2 ¯ fin + ICC ¯ VCC. http://onsemi.com 5 MC74VHC138 SWITCHING WAVEFORMS VALID A VALID VCC 50% GND Y 50% tPLH tPHL tPHL tPLH VCC E3 50% VCC 50% VCC Y Figure 2. Figure 3. TEST POINT E2 or E1 VCC 50% tPHL Y tPLH OUTPUT DEVICE UNDER TEST GND CL* 50% VCC *Includes all probe and jig capacitance Figure 4. Figure 5. Test Circuit INPUT Figure 6. Input Equivalent Circuit http://onsemi.com 6 GND MC74VHC138 PACKAGE DIMENSIONS D SUFFIX SOIC CASE 751B--05 ISSUE J --A-16 9 1 8 --B-- P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K DIM A B C D F G J K M P R F X 45 _ C --T-- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 DT SUFFIX TSSOP CASE 948F--01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K K1 2X L/2 16 9 J1 B --U-- L SECTION N--N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A --V-- M N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. F DETAIL E --W-- C 0.10 (0.004) --T-- SEATING PLANE D G DETAIL E H http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHC138 PACKAGE DIMENSIONS M SUFFIX SOIC EIAJ--16 CASE 966--01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.78 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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