MC74VHC126 Quad Bus Buffer with 3−State Control Inputs The MC74VHC126 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves noninverting high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC126 requires the 3−state control input (OE) to be set Low to place the output into high impedance. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. • • • • • • • • • • • • High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 μA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant http://onsemi.com 14−LEAD SOIC D SUFFIX CASE 751A 14−LEAD TSSOP DT SUFFIX CASE 948G PIN CONNECTIONS OE1 1 14 VCC A1 2 13 OE4 Y1 3 12 A4 OE2 4 11 Y4 A2 5 10 Y2 6 9 A3 GND 7 8 Y3 OE3 (Top View) ORDERING INFORMATION Device MC74VHC126DR2G MC74VHC126DTR2G Package Shipping SOIC 2500 Units/Reel TSSOP 2500 Units/Reel DEVICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 5 1 Publication Order Number: MC74VHC126/D MC74VHC126 Active−High Output Enables 2 A1 3 Y1 1 OE1 5 A2 6 Y2 4 OE2 9 A3 8 Y3 10 OE3 12 A4 11 Y4 13 OE4 FUNCTION TABLE VHC126 Inputs Output A OE Y H L X H H L H L Z Figure 1. Logic Diagram http://onsemi.com 2 MC74VHC126 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS (Note 1) Symbol Value Unit VCC DC Supply Voltage Parameter –0.5 to +7.0 V Vin DC Input Voltage –0.5 to +7.0 V Vout DC Output Voltage –0.5 to VCC + 0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins PD Power Dissipation in Still Air (Note 2) Tstg Storage Temperature ±50 mA 500 450 mW –65 to +150 _C SOIC Packages TSSOP Package 1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum−rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 2. Derating − SOIC Packages: – 7.0 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 5.5 V VCC DC Supply Voltage Vin DC Input Voltage 0 5.5 V Vout DC Output Voltage 0 VCC V −55 +125 _C 0 0 100 20 ns/V TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time VCC = 3.3 V ±0.3 V VCC = 5.0 V ±0.5 V http://onsemi.com 3 MC74VHC126 DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter VIH Test Conditions TA = 25°C (V) Min Minimum High−Level Input Voltage 2.0 3.0 4.5 5.5 1.5 2.1 3.15 3.85 VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 5.5 VOH Minimum High−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = −50 μA VIN = VIH or VIL IOH = −4.0 mA IOH = −8.0 mA VOL Maximum Low−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 50 μA VIN = VIH or VIL IOL = 4.0 mA IOL = 8.0 mA Typ TA ≤ 85°C Max Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 2.0 3.0 4.5 Max 2.0 3.0 4.5 0.0 0.0 0.0 TA ≤ 125°C Min Max 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 V 0.5 0.9 1.35 1.65 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V V IOZ Maximum 3−State Leakage Current VIN = VIH or VIL VOUT = VCC or GND 5.5 ±0.25 ±2.5 ±2.5 μA IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 μA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 4.0 40 40 μA http://onsemi.com 4 MC74VHC126 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25°C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Parameter Min Test Conditions TA = ≤ 85°C TA = ≤ 125°C Typ Max Min Max Min Max Unit ns Maximum Propagation Delay, A to Y VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 5.6 8.1 8.0 11.5 1.0 1.0 9.5 13.0 1.0 1.0 12.0 15.0 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 3.8 5.3 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 8.5 10.5 Maximum Output Enable TIme, OE to Y VCC = 3.3 ± 0.3 V RL = 1.0 kΩ CL = 15 pF CL = 50 pF 5.4 7.9 8.0 11.5 1.0 1.0 9.5 13.0 1.0 1.0 11.5 15.0 VCC = 5.0 ± 0.5 V RL = 1.0 kΩ CL = 15 pF CL = 50 pF 3.6 5.1 5.1 7.1 1.0 1.0 6.0 8.0 1.0 1.0 7.5 9.5 Maximum Output Disable Time, OE to Y VCC = 3.3 ± 0.3 V RL = 1.0 kΩ CL = 50 pF 9.5 13.2 1.0 15.0 1.0 18.0 VCC = 5.0 ± 0.5 V RL = 1.0 kΩ CL = 50 pF 6.1 8.8 1.0 10.0 1.0 12.0 Output−to−Output Skew VCC = 3.3 ± 0.3 V (Note 3) CL = 50 pF 1.5 1.5 1.5 VCC = 5.0 ± 0.5 V (Note 3) CL = 50 pF 1.0 1.0 1.0 10 10 10 Cin Maximum Input Capacitance 4.0 Cout Maximum Three−State Output Capacitance (Output in High Impedance State) 6.0 ns ns ns pF pF Typical @ 25°C, VCC = 5.0V CPD 15 Power Dissipation Capacitance (Note 4) pF 3. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V VOLV Quiet Output Minimum Dynamic VOL − 0.3 − 0.8 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V Symbol Characteristic http://onsemi.com 5 MC74VHC126 SWITCHING WAVEFORMS VCC OE VCC 50% GND 50% A tPZL GND tPHL tPLH tPLZ HIGH IMPEDANCE 50% VCC Y 50% VCC tPZH Y VOL + 0.3V tPHZ VOH - 0.3V 50% VCC Y Figure 2. Figure 3. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST HIGH IMPEDANCE DEVICE UNDER TEST CL* *Includes all probe and jig capacitance OUTPUT 1 kΩ CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 4. Test Circuit Figure 5. Test Circuit INPUT Figure 6. Input Equivalent Circuit http://onsemi.com 6 MC74VHC126 MARKING DIAGRAMS 14 13 12 11 10 9 14 13 12 11 10 8 3 4 6 7 126 AWLYWW* 2 8 VHC VHC126 1 9 ALYW* 5 6 7 1 14−LEAD SOIC D SUFFIX CASE 751A 2 3 4 5 14−LEAD TSSOP DT SUFFIX CASE 948G *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 7 MC74VHC126 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− 0.25 (0.010) M T B S A DIM A B C D F G J K M P R J M K D 14 PL F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS http://onsemi.com 8 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74VHC126 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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