MC74VHC50 Hex Buffer The MC74VHC50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. • • • • • • • • High Speed: tPD = 3.8 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) http://onsemi.com 14--LEAD SOIC D SUFFIX CASE 751A These devices are available in Pb--free package(s). Specifications herein apply to both standard and Pb--free devices. Please see our website at www.onsemi.com for specific Pb--free orderable part numbers, or contact your local ON Semiconductor sales office or representative. 14--LEAD TSSOP DT SUFFIX CASE 948G 14--LEAD SOIC EIAJ M SUFFIX CASE 965 PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 14 A1 A2 A3 1 2 3 4 5 6 Y1 Y=A A4 A5 A6 9 8 11 10 13 12 Y4 Figure 1. Logic Diagram © Semiconductor Components Industries, LLC, 2006 March, 2006 -- Rev. 4 A1 1 A2 1 A3 1 A4 1 A5 1 A6 1 Y5 Y6 Y6 12 A5 11 Y5 10 A4 9 Y4 8 1 2 3 4 5 6 7 A1 Y1 A2 Y2 A3 Y3 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. Y2 Y3 A6 13 Y1 FUNCTION TABLE Y2 A Input Y Output Y3 L H L H Y4 Y5 Y6 Figure 2. Logic Symbol 1 ORDERING INFORMATION Device Package Shipping MC74VHC50D SOIC 55 Units/Rail MC74VHC50M SOIC EIAJ 50 Units/Rail Publication Order Number: MC74VHC50/D MC74VHC50 MAXIMUM RATINGS Symbol Parameter VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IOUT ICC TSTG Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature under Bias θJA Thermal Resistance Value Unit −0.5 to +7.0 V −0.5 to +7.0 V −0.5 to VCC +0.5 V VI < GND −20 mA VO < GND ±20 mA DC Output Sink Current ±25 mA DC Supply Current per Supply Pin ±50 mA −65 to +150 °C 260 °C +150 (Note 1) SOIC TSSOP °C °C/W 125 170 MSL Moisture Sensitivity FR Flammability Rating Level 1 VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) > 2000 > 200 2000 V ILatch--Up Latch--Up Performance Above VCC and Below GND at 85°C (Note 5) ±300 mA Oxygen Index: 30 to 35 UL 94 V--0 @ 0.125 in Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm--by--1 inch, 2--ounce copper trace with no air flow. 2. Tested to EIA/JESD22--A114--A. 3. Tested to EIA/JESD22--A115--A. 4. Tested to JESD22--C101--A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free--Air Temperature Δt/ΔV Input Transition Rise or Fall Rate Min Max Unit 2.0 5.5 V (Note 6) 0 5.5 V (HIGH or LOW State) 0 VCC V −55 +125 °C 0 0 100 20 ns/V VCC = 3.0 V ±0.3 V VCC = 5.0 V ±0.5 V 6. Unused inputs may not be left open. All inputs must be tied to a high-- or low--logic input voltage level. NOTE: The θJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. http://onsemi.com 2 MC74VHC50 DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter Test Conditions Min 1.5 2.0 3.15 3.85 VIH Minimum High--Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low--Level Input Voltage 2.0 3.0 4.5 5.5 VOH Minimum High--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = --50 mA VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VOL Maximum Low--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 50 mA TA = 25°C (V) Typ Min 0.5 0.9 1.35 1.65 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 Max 1.5 2.0 3.15 3.85 2.0 3.0 4.5 2.0 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA TA ≤ 85°C Max 0.0 0.0 0.0 TA ≤ 125°C Min Max 1.5 2.0 3.15 3.85 V 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 2.0 20 40 mA AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0 ns) TA = 25°C Symbol tPLH, tPHL CIN Parameter Maximum Propogation Delay, Input A to Y Min Test Conditions TA ≤ 85°C Typ Max Min Max TA ≤ 125°C Min Max Unit ns VCC = 3.0 ± 0.3 V CL = 15 pF CL = 50 pF 5.0 7.5 7.1 10.6 8.5 12.0 10.0 14.5 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 3.8 5.3 5.5 7.5 6.5 8.5 8.0 10.0 4 10 10 10 Maximum Input Capacitance pF Typical @ 25°C, VCC = 5.0 V 18 CPD Power Dissipation Capacitance (Note 7) pF 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD ¯ VCC ¯ fin + ICC. CPD is used to determine the no--load dynamic power consumption; PD = CPD ¯ VCC2 ¯ fin + ICC ¯ VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.8 1.0 V VOLV Quiet Output Minimum Dynamic VOL --0.8 --1.0 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 3 MC74VHC50 TEST POINT VCC 50% A OUTPUT DEVICE UNDER TEST GND tPHL tPLH CL* 50% VCC Y *Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 14 13 12 11 10 8 3 4 6 7 50 AWLYWW* 2 8 VHC VHC50 1 9 ALYW* 5 6 7 1 2 14--LEAD SOIC D SUFFIX CASE 751A 3 4 5 14--LEAD TSSOP DT SUFFIX CASE 948G 14 13 12 11 10 9 8 5 6 7 VHC50 ALYW* 1 2 3 4 14--LEAD SOIC EIAJ M SUFFIX CASE 965 *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 4 MC74VHC50 PACKAGE DIMENSIONS SOIC--14 D SUFFIX CASE 751A--03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. --A-14 8 --B-1 0.25 (0.010) G 0.25 (0.010) M T B B M F J M K D 14 PL M R X 45 _ C --T-SEATING PLANE P 7 PL 7 S A S http://onsemi.com 5 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74VHC50 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 948G--01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B --U-- L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. S DETAIL E K A --V-- K1 J J1 SECTION N--N --W-- C 0.10 (0.004) --T-- SEATING PLANE D G H DETAIL E http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHC50 PACKAGE DIMENSIONS SO--14 M SUFFIX CASE 965--01 ISSUE O 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE L 7 1 M_ DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----1.42 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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