NCN6804
Dual Smart Card Interface
IC with SPI Programming
Interface
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MARKING
DIAGRAM
1
QFN32
CASE 488AM
A
L
Y
W
G
Features
•Point Of Sales (POS) and Transaction Terminals
•ATM (Automatic Teller Machine) / Banking Terminal Interfaces
•Set Top Box Decoder and Pay TV
May, 2007 - Rev. 0
1
I/O
CS
CLK_IN
CLK_SPI
MISO
MOSI
EN_RPU
VDD
32 31 30 29 28 27 26 25
S1
1
CRD_DETA
2
CRD_C4A
3
CRD_C8A
4
CRD_I/OA
5
CRD_RSTA
6
CRD_CLKA
7
CRD_VCCA
8
24 INT
23 CRD_DETB
22 CRD_C4B
EXPOSED PAD
21 CRD_C8B
33
20 CRD_I/OB
GNDD
19 CRD_RSTB
18 CRD_CLKB
17 CRD_VCCB
L2B
GNDPB
L1B
VDDPB
VDDPA
9 10 11 12 13 14 15 16
ORDERING INFORMATION
Device
Typical Application
© Semiconductor Components Industries, LLC, 2007
PIN CONNECTIONS
L1A
(division ratio 1/1, 1/2, 1/4) Managed Independently for Each Card
•Built-in Programmable CRD_CLK Stop Function handles Low State
•ESD Protection on Card pins (8 kV, Human Body Model)
•Activation / Deactivation built-in Sequencer
•Internal I/O Pull-up Resistor with Resistor Disconnection Option
(EN_RPU)
•4–Wire Series Bus Interface – SPI
•QFN32 (5x5 mm2) Package
•This is a Pb-Free Device
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
L2A
•Dual Smart Card / SAM Interface with SPI Programming Bus
•Fully Compatible with ISO 7816-3, EMV and GIE-CB Standards
•One Protected Bidirectional Buffered I/O Line per Card Port
•Wide Power Supply Voltage Range: 2.7V < VDDPA/B & VDD < 5.5V
•Programmable/Independent CRD_VCC Supply for Each Smart Card
•Multiplexed Mode of Operating
•Handles 1.8 V, 3.0 V and 5.0 V Smart Cards
•Programmable Rise & Fall Card Clock Slopes (Slow & Fast Modes)
•Support up to 40 MHz Clock with Internal Programmable Clock
NCN
6804
ALYWG
32
1
GNDPA
The NCN6804 is a dual interface IC with serial control. It is
dedicated for Smart Card/Secure Access Module (SAM) reader/writer
applications. It allows the management of two external ISO/EMV
cards (Class A, B or C). An SPI bus is used to control and configure
the dual interface. The cards are controlled in a multiplexed mode.
Two NCN6804 devices (4 smart card interfaces) can share one single
control bus thanks to a dedicated hardware address pin (S1).
An accurate protection system guarantees timely and controlled
shutdown in the case of external error conditions.
This device is an enhanced version of the NCN6004A, more
compact, more flexible and fully compatible with the NCN6001, its
single interface counterpart version. It is fully compatible with ISO
7816-3, EMV and GIE-CB standards.
NCN6804MNR2G
Package
Shipping†
QFN32
(Pb-Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCN6804/D
NCN6804
22 mH
22 mH
VBAT
VDDPA
VDDPB
10mF
VDD
0.1mF
L1A
L2A L1B
L2B
GND
SMART CARD A
S1
DET
CRD_DETA
VDD
10mF
CRD_VCCA
3
CRD_CLKA
4
SPI BUS
CLK_SPI
MISO
MOSI
NCN6804
CRD_C4A
CS
1
2
CRD_RSTA
INT
VCC
GND
RST
VPP
I/O
CLK
C4
C8
5
6
GND
7
8
CRD_C8A
CRD_I/OA
GNDPA
SMART CARD B
GNDPB
CRD_DETB
DET
DET
GND
DATA PORT
Microcontroller
DET
GND
10mF
CLK_IN
CRD_VCCB
I/O
CRD_RSTB
CRD_CLKB
VDD
CRD_C4B
CRD_C8B
EN_RPU
CRD_I/OB
GNDD
Figure 1. Typical Interface Application
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2
1
2
3
4
VCC
GND
RST
VPP
I/O
CLK
C4
C8
5
6
7
8
GND
NCN6804
VDD
DET#A
INTERRUPT BLOCK
24
INT#A
DET#B
CARD #A
INT
INT#B
VDD
VDD
32
VDD
DC-DC CONVERTER
INT#A
50 k
1
S1
12
VDDPA
11
L1A
9
L2A
8
CRD_VCCA
10
GNDPA
5
CRD_I/OA
6
CRD_RSTA
7
CRD_CLKA
4
CRD_C8A
3
CRD_C4A
CLK_SPI
28
CLK DIV
CARD #A
30
DC-DC CONVERTER
MOSI
CARD #A
29
ISO7816 SEQUENCER
MISO
ADDRESS DECODING
27
REGISTER
CS
DUAL 8-BIT SHIFT
18 k
VDD
DET#A
CARD #A DETECTION
2
CRD_DETA
DET#B
CARD #B DETECTION
23
CRD_DETB
22
CRD_C4B
21
CRD_C8B
18
CRD_CLKB
19
CRD_RSTB
20
CRD_I/OB
15
GNDPB
17
CRD_VCCB
16
L2B
14
L1B
13
VDDPB
I/O MUX
25
CARD #B
CLK DIV
DC-DC CONVERTER
I/O
CLOCK
MUX
26
CARD #B
CLK_IN
ISO7816 SEQUENCER
LOGIC CONTROL
18 k
31
CARD #B
EN_RPU
Exposed Pad
GNDD
33
GND
Figure 2. NCN6804 Block Diagram
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3
DC-DC CONVERTER
18 k
NCN6804
PIN FUNCTION AND DESCRIPTION
PIN
Name
Type
Description
1
S1
I
Address pin (Chip Identification pin) – allows having in parallel up to 2 NCN6804 devices (4
interfaces) managed by 1 Chip Select pin only (CS) – multiple interface application case. When one
dual interface only is used this pin can be connected to GROUND.
2, 23
CRD_DETA,
CRD_DETB
I
The signal coming from the external card connector is used to detect the presence of the card. A
built-in pull-up low current source biases this pin HIGH, making it active LOW, assuming one side of
the external switch is connected to ground. A built-in digital filter protects the system against voltage
spikes present on this pin. The polarity of the signal is programmable by the MOSI message; refer to
Table 2. On the other hand, the meaning of the feedback message contained in the MISO register bit
b4, depends upon the SPI mode of operation as defined here below:
SPI Normal Mode: The MISO bit b4 is HIGH when a card is inserted, whatever be the polarity of the
card detect switch.
SPI Special Mode: The MISO bit b4 copies the logic state of the card detect switch as depicted here
below, whatever be the polarity of the switch used to handle the detection:
CRD_DET = LOW => MISO/b4 = LOW
CRD_DET = HIGH => MISO/b4 = HIGH
In both cases, the chip must be programmed to control the right logic state (Table 2). Since the bias
current supplied by the chip is very low, typically 5.0 mA, care must be observed to avoid low
impedance or cross coupling when this pin is in the Open state.
3, 22
CRD_C4A,
CRD_C4B
O
Auxiliary mixed analog/digital line to handle synchronous card connected when used to the card pin
C4. An accelerator circuit makes sure the output positive going rise time is fully within the ISO/EMV
specifications.
4, 21
CRD_C8A,
CRD_C8B
O
Auxiliary mixed analog/digital line to handle synchronous card connected when used to the card pin
C8. An accelerator circuit makes sure the output positive going rise time is fully within the ISO/EMV
specifications.
5, 20
CRD_IOA,
CRD_IOB
I/O
This pin handles the connection to the serial I/O pin of the card connector. A bi-directional level
translator adapts the serial I/O signal between the card and the mC. An internal active pull down
device forces this pin to GROUND during either the CRD_VCC start up sequence, or when
CRD_VCC = 0V. The output current is internally limited to 15mA. When operating in a synchronous
mode I/O is transmitted through the SPI bus (MOSI bit b2) to CRD_I/O. In that case I/O is
disconnected and no longer used.
6, 19
CRD_RSTA,
CRD_RSTB
O
This pin is connected to the RESET pin of the card connector. A level translator adapts the RESET
signal from the mC (through the SPI bus) to the external card. The output current is internally limited
to 15mA. The CRD_RST is validated when CS = LOW, and is hard wired to GROUND by and
internal active pull down circuit when the card is deactivated.
7, 18
CRD_CLKA,
CRD_CLKB
O
Clock pin connected to the card pin C3. An internal active pull down device forces this pin to
GROUND during the CRD_VCC start up sequence, or when CRD_VCC = 0V. The rise and fall
slopes, either FAST or SLOW, of this signal can be programmed by the SPI bus. Refer to Table 2.
8, 17
CRD_VCCA,
CRD_VCCB
Power
Power supply to the external card (card pin C1). An external capacitor Cout = 10 mF minimum is
required. In the event of a CRD_VCC under-voltage issue, the NCN6804 detects the situation and
feedback the information in the STATUS bit (MISO bit b0). The device does not take any further
action; particularly the DC/DC converter is neither stopped nor re-programmed by the NCN6804. It is
up to the external mC to handle the situation. However, when CRD_VCC is overloaded, the NCN6804
shuts off the DC/DC converter, runs a Power Down ISO7816 sequence and reports the fault in the
STATUS register (MISO register bit b0).
9
L1A
Power
The low side of the external inductor A.
10
GNDPA
Power
DC/DC converter A power ground pin.
11
L2A
Power
The high side of the external inductor A.
12
VDDPA
Power
DC/DC converter A power supply input (Cbypass_min = 4.7 mF).
13
VDDPB
Power
DC/DC converter B power supply input (Cbypass_min = 4.7 mF).
14
L2B
Power
The high side of the external inductor B.
15
GNDPB
Power
DC/DC converter B power ground pin.
16
L1B
Power
The low side of the external inductor B.
24
INT
O
This pin is activated LOW when a card has been inserted and detected by the CRD_DETA or
CRD_DETB pins in either of the external ports. Similarly an interrupt is generated when the
CRD_VCCA or B output is overloaded, or when the card has been extracted whatever be the
transaction status (running or stand by). The INT signal is reset to HIGH according to Table 7. On the
other hand, the pin is forced to logic HIGH when the power supply voltage VDDPA or B drops below
2 V.
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4
NCN6804
PIN FUNCTION AND DESCRIPTION
PIN
Name
Type
Description
25
I/O
I/O
This pin is connected to an external micro-controller (mC) interface. A bi-directional level translator
adapts the serial I/O signal between the smart card and the mC. The level translator is enabled when
CS = LOW, the sub address has been selected and the system operates in the Asynchronous mode.
When a Synchronous card is in use this pin is disconnected and the data and transaction take place
through the MOSI and the MISO registers. The internal pull up resistor connected on the mC side is
activated and visible by the selected chip only.
26
CLK_IN
I
This pin (high impedance) can be connected to either the mC master clock or to a crystal oscillator
clock to drive the external smart cards. The signal is fed to the internal clock selector circuit and
translated to the CRD_CLKA or CRD_CLKB pins at either the same frequency, or divided by 2, 4 or
8, depending upon the programming mode. Refer to table 2. Synchronous case: clock managed
through the SPI bus – CLK_IN is disconnected. Note: The chip guarantees the EMV 50% Duty Cycle
when the clock divider ratio is 1/2, 1/4, or 1/8, even when the CLK_IN signal is out of the 45% to 55%
range specified by ISO and EMV specifications.
27
CS
I
This pin synchronizes and enables the SPI communication. All the NCN6804 functions, both
programming and card transaction, are disabled when CS = HIGH.
28
CLK_SPI
29
MISO
O
Master In Slave Out: SPI Data Output from the NCN6804. This STATUS byte carries the state of the
interface, the serial transfer being achieved according to the programmed mode (Table 2), using the
same CLK_SPI signal and during the same MOSI time frame. An external 4.7 kW pull down resistor
might be necessary to avoid misunderstanding of the pin 29 voltage during the High Z state.
30
MOSI
I
Master Out Slave In: SPI Data Input from the mC. This byte contains the address of the selected chip
among the two possible (bit b6), together with the programming code for a given interface. See Table
2.
31
EN_RPU
I
This pin is used to activate the I/O internal pull-up resistor such as:
EN_RPU = Low => I/O Pull-up resistor disconnected
EN_RPU = High => I/O Pull-up resistor connected
When two or more NCN6804 chips share the same I/O bus, one chip only shall have the internal
pull-up resistor enabled to avoid any overload of the I/O line. Moreover, when Asynchronous and
Synchronous cards are handled by the interfaces, the activated I/O pull-up resistor must preferably
be the one associated with the asynchronous circuit. On the other hand, since no internal pull-up
bias resistor is built in the chip, pin 31 must be connected to the right voltage level to make sure the
logic function is satisfied.
32
VDD
Power
This pin is connected to the system controller power supply (Cbypass_min = 100 nF). When VDD is
below 2.5 V the CRD_VCCA or B is disabled. The NCN6804 goes into a shutdown mode.
33
GNDD
Power
Digital/analog Ground. This pin is the Exposed Pad and is the Ground for the digital/analog circuit
section. It needs to be connected to the PCB Ground.
Clock Signal to synchronize the SPI data transfer. This clock is fully independent from the CLK_IN
signal and does not play any role with the data transaction (I/O – CRD_I/O).
ATTRIBUTES
Characteristics
Values
ESD protection
Human Body Model, Smart Card Pins (Card Interface Pins (Card A
and B)) (Note 1)
Human Body Model, CRD_DETA/B Pins (2, 23) (Note 1)
Human Body Model, All Other Pins (Note 1)
Moisture sensitivity (Note 2) QFN-32
8 kV
4 kV
2 kV
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
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NCN6804
MAXIMUM RATINGS (Note 3)
Rating
DC/DC Converter Power Supply Voltage (VDDPA/B)
Symbol
Value
Unit
Vsup
(Note 4)
-0.5 ≤ Vsup ≤ 6
V
VDD
-0.5 ≤ VDD ≤ 6
V
CRD_VCC
-0.5 ≤ CRD_VCC ≤ 6
V
Digital Input Pins
Vin
Iin
-0.5 ≤ Vin ≤ (VDD + 0.5)
but < 6.0 ± 5
V
mA
Digital Output Pins (I/O, MISO, INT)
Vout
Iout
-0.5 ≤ Vout ≤ (VDD+ 0.5)
but < 6.0 ± 10
V
mA
Smart Card Output Pins
Vout
-0.5 Vout ≤ (CRD_VCC + 0.5)
but< 6.0
V
Smart Card Output Pins Excepted CRD_CLK
Iout
15 (Internally Limited)
mA
CRD_CLK Pin
Iout
70 (Internally Limited)
mA
Inductor Current
ILmax
500 (Internally Limited)
mA
QFN-32 5x5 mm2 package
Power Dissipation @ TA = +85°C
Thermal Resistance Junction-to-Air
PD
RqjA
1650
40
mW
°C/W
Operating Ambient Temperature Range
TA
-40 to +85
°C
Operating Junction Temperature Range
TJ
-40 to +125
°C
TJmax
+125
°C
Tstg
-65 to + 150
°C
Power Supply from Microcontroller Side (VDD)
External Card Power Supply (Card A and B)
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
4. Vsup = VDDPA/B = VDDPA and VDDPB
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NCN6804
POWER SUPPLY SECTION (-40°C to +85°C, unless otherwise noted)
Pin
Symbol
12, 13
Vsup
Power Supply (VDDPA/B) (Note 5)
12, 13
Isup
DC Operating current – All Card Pins Unloaded, CLK_IN=Low
Vsup = 2.7 V, CRD_VCCA or B = 5 V
Vsup = 5.5 V, CRD_VCCA or B = 5 V
12, 13
Isupst
Rating
Min
VDD
Operating Voltage (Note 5)
32
IVDD
Operating Current – CLK_IN = CLK_SPI = MOSI = High, CS = I/O =Low
50
IVDD_SD
32
UVLOVDD
Under voltage lockout
1.8
8, 17
CRD_VCC
Output Card Supply Voltage @ 2.7 V< VCC < 5.5 V
CRD_VCCA/B = 1.8 V @ Iload = 35 mA
CRD_VCCA/B = 3.0 V @ Iload = 60 mA
CRD_VCCA/B = 5.0 V @ Iload = 65 mA
1.66
2.76
4.65
8, 17
8, 17
8, 17
8, 17
ICRD_VCC_OV
DVCRD_VCC
CRD_VCCTON
V
mA
2.7
Shutdown Current – CS = High
Maximum Continuous Output Current
@ CRD_VCC = 1.8 V
@ CRD_VCC = 3.0 V
@ CRD_VCC = 5.0 V
Unit
5.5
mA
32
ICRD_VCC
Max
0.5
0.5
Standby Supply Current, no card inserted
INT=CLK_IN=CLK_SPI=CS= I/O = MOSI = EN_RPU = H
Vsup = 5.5 V
32
8, 17
Typ
2.7
5.5
V
150
mA
60
mA
2.5
V
V
1.80
3.00
5.00
1.94
3.24
5.35
mA
35
60
65
Output Over-Current Limit :
Vsup = 2.7 V, CRD_VCCA/B = 1.8 V, 3.0 V, 5.0 V
Vsup= 5.5 V, CRD_VCCA/B = 1.8 V, 3.0 V, 5.0 V
Output Card Supply Voltage Ripple @ Vsup = 3.6V, L = 22 mH,
Cout = 10 mF (Ceramic X7R), ICRD_VCC= ISO Maximum Current (Note 6)
CRD_VCCA/B = 5.0 V
CRD_VCCA/B = 3.0 V
CRD_VCCA/B = 1.8 V
mA
200
260
mV
60
45
40
ms
Output Card Turn On Time
Vsup = 2.7 V, CRD_VCCA/B = 5.0 V
Lout = 22 mH, Cout = 10 mF Ceramic
CRD_VCCTOFF Output Card Turn Off Time
VCCA/P = 2.7 V, CRD_VCCA/B = 5.0 V
Lout = 22 mH, Cout = 10 mF Ceramic, CRD_VCCOFF < 0.4 V
NOTE:
500
ms
100
250
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. VDD and Vsup have separated pads for noise and EMI immunity improvement – by similarity with the NCN6001 VDD and Vsup have to be
equal and connected to the same power supply (VDD = Vsup = VDDPA/B)
6. Ceramic X7R, SMD type capacitors are mandatory to achieve the CRD_VCC ripple specifications. The ceramic capacitor has to be chosen
according to its ESR (very low ESR) and DC bias features. The capacitance value can strongly vary with the DC voltage applied (see Figure
22).
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NCN6804
DIGITAL INPUT/OUTPUT SECTION CLK_IN, I/O, CLK_SPI, MOSI, MISO, CS, INT, EN_RPU (-40 °C to +85°C)
Pin
Symbol
26
FCLK_IN
Rating
Min
Typ
Input Asynchronous Clock Duty Cycle = 50%
@ VDD = 3.0 V
@ VDD = 5.0 V
Max
Unit
MHz
30
40
26
Ftr
Ftf
Input Clock Rise time
Input Clock Fall time
2
2
28
FCLK_SPI
Input SPI clock
15
MHz
28
trspi, tfspi
Input CLK_SPI Rise/Falltime
12
ns
30
trmosi,
tfmosi
Input MOSI Rise/Falltime
12
ns
29
trmiso,
tfmiso
Output MISO Rise/Falltime @ CS = 30 pF
12
ns
27
trstr, tfstr
Input CS Rise/Falltime
12
ns
25
tRIO
tFIO
RINT
INT Pull Up Resistor
25,26,2
7,28,30
VIH
Positive going Input High Level Voltage Threshold (CLK_IN, MOSI,
CLK_SPI, CS, EN_RPU)
25,26,2
7,28,30
VIL
Negative going Input Low Level Voltage (CLK_IN, MOSI, CLK_SPI,
CS, EN RPU)
24, 29
VOH
Output High Voltage
INT, MISO @ IOH = -10 mA (source)
VOL
ms
I/O Data Transfer Switching Time, both directions (I/O & CRD_IOA/B)
@ Cs = 30 pF
I/O Rise time (see Note 7)
I/O Fall time
24
24, 29
ns
0.8
0.8
20
45
80
kW
0.70 * VDD
VDD
V
0
0.3 *VDD
V
V
VDD– 1.0
Output Low Voltage
INT, MISO @ IOL = 200 mA (sink)
V
0.40
28
tdclk_spi
Delay Between 2 Consecutive CLK_SPI Burst Sequence
33
25
Rpu_I/O
I/0 Pullup Resistor
12
NOTE:
ns
18
24
kW
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions are not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Since a 18 kW (Typical) pullup resistor is provided by the NCN6804, the external MPU can use an Open Drain connection. On the other hand
NMOS smart cards can be used straightforward.
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8
NCN6804
SMART CARD INTERFACE SECTION (-40°C to +85°C temperature range unless otherwise noted)
Note: Digital inputs undershoot v 0.30V to ground, digital inputs overshoot < VDD + 0.30V
Pin
Symbol
Max
Unit
CRD_VCC
0.40
V
V
100
100
ns
ns
CRD_VCC
0.4
100
100
V
V
ns
ns
CRD_VCC-0.5
20
CRD_VCC
0.4
MHz
V
V
45
55
%
tress
tfcs
Rise & Fall time
@ CRD_VCCA/B = 1.8 V, 3.0 V or 5.0 V
Clock programmed as FST_SLP
Output CRD_CLKA/B Risetime @ Cout = 30 pF
Output CRD_CLKA/B Falltime @ Cout = 30 pF
4
4
ns
ns
trills
tulsa
Rise & Fall time @ CRD_VCCA/B = 1.80V to 5.0V
Clock programmed as SLO_SLP
Output CRD_CLKA/B Risetime @ Cout = 30 pF
Output CRD_CLKA/B Falltime @ Cout = 30 pF
16
16
ns
ns
6,19
VOH
VOL
tR
tF
3, 4
21, 22
VOH
VOL
tR
tF
7, 18
Rating
Min
CRD_RSTA/B @ CRD_VCCA/B = 1.8 V, 3.0 V, 5.0 V
Output RESET VOH @ Irst = -200 mA
Output RESET VOL @ Irst = 200 mA
CRD_RSTA/B @ CRD_VCCA/B = 1.8 V, 3.0 V, 5.0 V
Output RESET Risetime @ Cout = 30 pF
Output RESET Falltime @Cout = 30 pF
CRD_C4A/B, CRD_C8A/B
@ CRD_VCCA/B = 1.8 V, 3.0 V, 5.0 V
Output VOH @ Irst = -200 mA
Output VOL @ Irst = 200 mA
Output Rise time @ Cout = 30 pF
Output Fall time @Cout = 30 pF
Typ
CRD_VCC – 0.5
CRD_VCC -0.5
CRD_CLKA/B as a function of CRD_VCCA/B
5,20
FCRDCLK
VOH
VOL
CRD_VCCA/B = 1.8 V, 3.0 V or 5.0V
Output Frequency
Output VOH @ Icrd_clk = -200mA
Output VOL @ Icrd_clk = 200mA
FCRDDC
CRD_CLKA/B Output Duty Cycle
CRD_VCCA/B = 1.8 V, 3.0 V or 5.0 V
VIH
CRD_IOA/B Input Voltage High Level
@ CRD_VCCA/B = 1.8 V, 3 V and 5 V
CRD_VCC*0.6
CRD_VCC+0.3
VIL
CRD_IOA/B Input Voltage Low Level
@ CRD_VCCA/B = 1.8 V, 3 V and 5 V
-0.30
0.80
VOH
Output VOH @ Icrd_I/O = -20mA, VIH = VDD
@ CRD_VCCA/B = 1.8 V, 3 V and 5 V
CRD_VCC – 0.5
CRD_VCC
VOL
Output VOL @ Icrd_I/O = 500 mA, VIL = 0 V
@ CRD_VCCA/B = 1.8 V, 3 V and 5 V
V
V
V
tR
tF
5, 20
CRD_IOA/B Rise Time, @ Cout = 30 pF
CRD_IOA/B Fall Time, @ Cout = 30 pF
0.8
0.8
ms
ms
CRD_IOA/B Pull Up Resistor
12
18
24
kW
TCRDIN
TCRDOFF
Card Detection digital filter delay:
Card Insertion
Card Extraction
25
25
50
50
150
150
ms
ms
VIHDET
2, 23
V
RCRDPU
2, 23
2, 23
0.40
0
VILDET
Card Insertion or Extraction Positive going Input
High Voltage
0.70 * VCC
VCC
V
Card Insertion or Extraction Negative going Input
Low Voltage
0
0.30 * VCC
V
3, 4, 5, 6,
19, 20,
21, 22
Icrd
Output peak Max Current under Card Static Operation
Mode @ CRD_VCC = 1.8V, 3.0V, 5.0V
CRD_I/OA/B, CRD_RSTA/B, CRD_C4A/B,
CRD_C8A/B
15
mA
7, 18
Icrd_clk
Output peak Max Current under Card Static Operation
Mode @ CRD_VCC = 1.8 V, 3.0 V, 5.0 V
CRD_CLKA/B
70
mA
NOTE:
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
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NCN6804
PROGRAMMING
Write Register"WRT_REG (Is Low Only)
Similar to the NCN6001, the NCN6804's WRT_REG register handles 3 command bits [b5:b7] and 5 data bits [b0:b4] as
depicted in Tables 1 and 2. These bits are concatenated into 1 byte [MSB0,LSB0] in order to accelerate the programming
sequence. The register can be updated when CS is low only.
The WRT_RGT has been defined to be compatible with the NCN6001 write register.
Table 1. WRT_REG BIT DEFINITIONS
b0
b1
If (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then
Case 00
CRD_VCCA = 0 V
Case 01
CRD_VCCA = 1.8 V
Case 10
CRD_VCCA = 3.0 V
Case 11
CRD_VCCA = 5.0 V
Else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then
Case 00
CRD_VCCB = 0 V
Case 01
CRD_VCCB = 1.8 V
Case 10
CRD_VCCB = 3.0 V
Case 11
CRD_VCCB = 5.0 V
Else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then
b1 drives CRD_C4A or B (respectively)
b0 drives CRD_C8A or B (respectively)
Else if (b7 + b6 + b5) =101 then
Case 00
CRD_DET = NO
Case 01
CRD_DET = NC
Case 10
SPI_MODE = Special
Case 11
SPI_MODE = Normal
Else if (b7 + b6 + b5) =100 then
NA (Not Applicable)
End if
8. When operating in Asynchronous mode, b6 is compared with the external voltage level present pin S1 (Pin 1).
9. The CRD_RST pin reflects the content of the MOSI WRT_REG [b4] during the chip programming sequence. Since the bit shall be Low
to address the chip's internal register, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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NCN6804
Table 1. WRT_REG BIT DEFINITIONS
b2
b3
If (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then
Case 00
CRD_CLKA = Low
Case 01
CRD_CLKA = CLK_IN
Case 10
CRD_CLKA = CLK_IN / 2
Case 11
CRD_CLKA = CLK_IN / 4
Else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then
Case 00
CRD_CLKB = Low
Case 01
CRD_CLKB = CLK_IN
Case 10
CRD_CLKB = CLK_IN / 2
Case 11
CRD_CLKB = CLK_IN / 4
Else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then
b3 drives CRD_CLKA or B (respectively)
b2 drives CRD_IOA or B (respectively)
Else if (b7 + b6 + b5) =101 then
Case 00
CRD_CLKA & B = SLO_SLP
Case 01
CRD_CLKA & B = FST_SLP
Case 10
NA
Case 11
NA
Else if (b7 + b6 + b5) =100 then
NA (Not Applicable)
End if
b4
If (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 100 then b4 Drives CRD_RSTA or B Pin
b5
b6
b7
000
001
010
011
100
101
110
111
Select NCN6804 device # 1 Asynchronous Card A (Note 8)
Select NCN6804 device # 1 Asynchronous Card B (Note 8)
Select NCN6804 device # 2 Asynchronous Card A (Note 8)
Select NCN6804 device # 2 Asynchronous Card B (Note 8)
NA
Set Card Detection Switch polarity, Set SPI_MODE normal or special , Set CRD_CLKA & B slopes Fast or Slow
Select External Synchronous Card A
Select External Synchronous Card B
8. When operating in Asynchronous mode, b6 is compared with the external voltage level present pin S1 (Pin 1).
9. The CRD_RST pin reflects the content of the MOSI WRT_REG [b4] during the chip programming sequence. Since the bit shall be Low
to address the chip's internal register, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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NCN6804
Table 2. WRT_REG BIT DEFINITIONS AND FUNCTIONS
ADRESS
PARAMETERS
MSB0
LSB0
MOSI bits[
b3 : b2]
MOSI bits
[b1 : b0 ]
MOSI bits
[b3 : b0 ]
b7
b6
b5
b4
b3
b2
b1
b0
CRD_CLK
CRD_VCC
0
S1
A/B
CRD_RST
0
0
0
0
Low
0
0
S1
A/B
CRD_RST
0
1
0
1
1/1
1.8V
0
S1
A/B
CRD_RST
1
0
1
0
1/2
3.0V
0
S1
A/B
CRD_RST
1
1
1
1
1/4
5.0V
1
1
A/B
CRD_RST
CRD_CLK
CRD_I/O
CRD_C4
CRD_C8
Synchronous
1
0
1
X
X
0
0
0
NO
1
0
1
X
X
0
0
1
NC
1
0
1
X
X
0
1
0
Special
1
0
1
X
X
0
1
1
Normal
1
0
1
X
X
1
0
0
SLO_SLP
1
0
1
X
X
1
0
1
FST_SLP
10. Card A: b5 = 0, Card B: b5 = 1, Device # 1: b6 = 0 ⇔ pin S1 connected to GND, Device # 2: b6 = 1 ⇔ pin S1 connected to VDD
11. Address 101 and bits [b0:b4] not documented in the table are not applicable with no effect on the device programming and configuration.
The sign X in the table means that either 1 or 0 can be used.
Read Register ³ READ_REG
either on the Positive going (SPI_MODE = Special) or upon
the Negative going slope (SPI_MODE = Normal) of the
CLK_SPI signal.
The external microcontroller shall discard the three high
bits since they carry no valid data.
The READ_REG register (1 byte) contains the data read
from the card interface. The selected chip register is
transferred to the MISO Pin during the MOSI sequence
(CS = Low).
Table 3 gives a definition of the bits.
Depending upon the programmed SPI_MODE, the
content of READ_REG is transferred on the MISO line
Table 3. MOSI AND MISO BITS IDENTIFICATIONS AND FUNCTIONS
MOSI
b7
b6
b5
b4
b3
b2
b1
b0
Operating Mode
.
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
CRD_RST
CRD_RST
CRD_RST
CRD_RST
CRD_RST
CRD_RST
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_I/O
CRD_I/O
CRD_VCC
CRD_VCC
CRD_VCC
CRD_VCC
CRD_C4
CRD_C4
CRD_VCC
CRD_VCC
CRD_VCC
CRD_VCC
CRD_C8
CRD_C8
Async. Card A, Program Chip
Async. Card B, Program Chip
Async. Card A, Program Chip
Async. Card B, Program Chip
Sync. Card A, Sets Card Bits
Sync. Card B, Sets Card Bits
MISO
z
z
z
Card Detect
CRD_I/O
CRD_C4
CRD_C8
PWR Monitor
Read Back Data
When a command is sent to A for example by selecting the
address %000 the corresponding MISO byte has the state of
the interface A (Card detectA, b4; I/OA, b3; C4A, b2; C8A,
b1; CRD_VCCA ok, b0) – that is the state loaded while
sending the previous MOSI command A or B.
When a command is sent to B for example by selecting the
address %001 the corresponding MISO byte has the state of
the interface B (Card detectB, b4; I/OB, b3; C4B, b2; C8B,
b1; CRD_VCCB ok, b0) – that is the state loaded while
sending the previous MOSI command A or B.
When b5 = LOW the interface A is selected and the
transaction or communication takes place through this
interface according to Table 2. The programming applies to
Card A only.
When b5 = HIGH the interface B is selected and the
transaction or communication takes place through this
interface according to Table 1. The programming applies to
Card B only.
CRD_VCCA and CRD_CLKA can be maintained
applied to card A when the device is switched from A to B.
This mode of operating is of course the same when the
device is switched from B to A: CRD_VCCB and
CRD_CLKB can be maintained applied to card B.
The device configuration is programmed using the
address {101} similarly to the NCN6001. In that case, the
programming is applied simultaneously to Card A and
Card B.
Card A or Card B Selection - Multiplexed Mode
The bit b5 in the MOSI sequence enables the selection of
the NCN6804's interface A or B (see Table 2) to the
exception of the addresses {100} decoded with no effect on
the device and {101} used to program device general
configuration. Then:
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NCN6804
Asynchronous Mode
function. In particular, using a low impedance probe (< 1
MW) might lead to uncontrolled operation during the debug.
Depending upon the programmed condition, the card can
be detected either by a Normally Open (default condition) or
a Normally Close switch (see Table 2). On the other hand,
the meaning of the feedback message contained in the MISO
register bit b4 depends upon the SPI mode of operation as
defined here below:
SPI Normal Mode: the MISO bit b4 is High when a card is
inserted, whatever be the polarity of the card detect switch.
SPI Special Mode: the MISO bit b4 copies the logic state of
the Card detect switch as depicted here below, whatever be
the polarity of the switch used to handle the detection:
CRD_DETA/B = Low ⇒ MISO / b4 = LOW
CRD_DETA/B = High ⇒ MISO / b4 = HIGH
In this mode, the S1 pin is used to define the physical
address (by comparison with the bit b6 (MOSI)) of the
interfaces when a bank of up to 2 NCN6804 (total of 4
interfaces) shares the same digital bus.
Synchronous Mode
In this mode, the CLK_IN clock input and the I/O
input/output are not used. The clock and the data are
provided and transferred through the SPI bus using MOSI
and MISO as shown Table 2.
When this operating mode is used and if two NCN6804
devices want to be implemented, it is no longer possible to
share the same CS signal. Consequently in this particular
case and when the devices operate in a multiple interface
mode a dedicated CS signal must be provided to each
NCN6804 device.
Since bits [b4 – b0] of the MOSI register contain the smart
card data, programming the CRD_VCC output voltage shall
be done by sending a previous MOSI message according to
Table 2 using the address [b7, b6, b5] = [0, S1, A/B]. For
example if a synchronous card is used, prior to make a
transaction with it, it will be powered-up for example at 5
V by sending the command %00000011 (address S1 = 0 and
card A selected).
The CRD_RSTA/B pin reflects the content of the MOSI
WRT_REG [b4] during the chip programming sequence.
Since this bit shall be LOW to address the internal register
of the chip, care must be observed as this signal will be
immediately transferred tot he CRD_RSTA/B pin.
CRD_VCC Operation
The dual NCN6804 interface has 2 built-in DC/DC
converters. Each of them can be programmed to provide one
of the three possible values, 1.8 V, 3.0 V or 5.0 V, assuming
the input voltage VDDPA or B is within the 2.7 V to 5.5 V
range. Card A and Card B can be independently powered-up
or down. Consequently if necessary for example the device
can be switched from card A to card B while the card A
power voltage is maintained (this is of course true from A to
B or from B to A). CRD_VCCA & B are voltage regulated
and protected against overload by a current overload
detection system. The DC/DC converter operates as a
buck/boost converter. The power conversion mode is
automatically switched to handle one of these two modes of
operation depending upon the voltage difference between
the CRD_VCCA or B and VDDPA or B respectively.
The CRD_VCCA or B output current range is given
Table 5; these values comply with the smart card ISO7816
standard and related.
Startup Default Conditions
At startup, when power supply is turned on, the internal
POR (Power On Reset) circuit sets the chip in the default
conditions as defined below (Table 4).
Table 4. STARTUP DEFAULT CONDITIONS
CRD_DETA/B
Normally Open
CRD_VCCA/B
OFF
CRD_CLKA/B
tr & tf = SLOW
CRD_CLKA/B
LOW
Protocol
Special Mode
I/O Pull-up resistor
Connected
INT
High
Table 5. CRD_VCCA OR B OUTPUT VOLTAGE
DEFINITION
CRD_VCCA or B
Current range
per Card
Cumulated
Current Range
(Card A and Card
B)
1.8 V
0 to 35+ mA
0 to 70 + mA
3.0 V
0 to 60+ mA
0 to 120 + mA
5.0 V
0 to 65+ mA
0 to 130 + mA
Whatever is the CRD_VCCA or B output voltage, a
built-in comparator makes sure the voltage is within the
ISO7816-3/EMV specifications. If the voltage is no longer
within the minimum/maximum values, the DC/DC is
switched off, the powerdown sequence takes place and an
interrupt is presented at the INT Pin 24.
Card Detection
The card is detected by the external switch connected to
pin 23 for Card B and pin 2 for Card A. The internal circuit
provides a positive bias of this pin and the polarity of the
insertion/extraction is programmable by the MOSI protocol
as depicted Table 2.
The bias current is 1mA typical and cares must be observed
to avoid leakage to ground from this pin to maintain the logic
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NCN6804
Powerup Sequence
At powerup, the CRD_VCCA/B turn-on time depends
upon the current capability of the DC/DC converter
associated with the external inductor L and the reservoir
capacitor connected across CRD_VCCA or B and
GROUND. During this sequence, the average input current
is 300 mA typical (see Figure 4), assuming the system is
fully loaded during the start up.
Even if enabled by the built-in sequencer the activation
sequence is under the control and responsibility of the
application software.
On the other hand, at turn off, the CRD_VCCA/B fall time
depends upon the external reservoir capacitor and the peak
current absorbed by the internal NMOS transistor built
across CRD_VCCA/B and Ground. These behaviors are
depicted Figure 5.
Since these parameters have finite values, depending
upon the external constraints, the designer must take care of
these limits if the tON or tOFF provided by the datasheet does
not meet his requirements.
The Powerup Sequence makes sure all the card related
signals are Low during the CRD_VCCA/B positive going
slope. These lines are validated when CRD_VCCA/B is
above the minimum voltage specified by the EMV standard
depending upon the programmed CRD_VCC A or B value
(see CRD_VCC Power Supply section on page NO TAG).
CS
CRD_VCC
CRD_IO
ATR
CRD_CLK
CRD_C4
CRD_C8
CRD_RST
Figure 3. Startup CRD_VCC Sequence
Figure 5. CRD_VCC Typical Turn-on and Turn-off
Times
Figure 4. Measured Typical Startup CRD_VCC
Sequence
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NCN6804
CRD_RST
CRD_CLK
CRD_C4
CRD_I/O
CRD_VCC
Figure 7. Typical Power Down Sequence
(Typical Delay Between Each Signal is 500 ns)
Figure 6. Figure 7: Start Up Sequence with ATR.
Since the internal digital filter is activated for any card
insertion or extraction, the physical power-down sequence
will be activated 50 ms (typical) after the card has been
extracted. Of course, such a delay does not exist when the
micro-controller intentionally launches the power down.
Powerdown Sequence
The NCN6804 provides an automatic Power Down
sequence, according to the ISO7816-3 specifications. When
a power down sequence is enabled the communication
session terminates immediately. The sequence is launched
under a micro-controller decision, when the card is
extracted, or when the CRD_VCCA/B voltage is overloaded
as described by the ISO/CEI 7816-3 sequence depicted here
after (see Figure 8):
³ CRD_ RST is forced to Low
³ CRD_CLK is forced to Low, unless it is already in this
state
³ CRD_C4 & CRD_C8 are forced to Low
³ Then CRD_IO is forced to Low
³ Finally the CRD_VCC supply is powered down
Data I/O Level Shifter
The level shifter accommodates the voltage difference
that might exist between the micro-controller and the smart
card. A pulsed accelerator circuit provides the fast positive
going transient according to the ISO7816-3 specifications.
The basic I/O level shifter is depicted Figure 8.
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NCN6804
VCC
9
6
EN_RPU
U1
PMOS
VCC
200 ns
Q1
R1
CRD_VCC
200 ns
13
Q2
R2
18 k
18 k
I/O
CRD_IO
1
20
Q3
Q4
CARD ENABLE
SYNC
Q5
LOGIC AND
LEVEL SHIFT
POR
SEQ 1
GND
CRD_VCC
MOSI/b2
Q5
VCC
From MOSI
decoding
GND
MOSI/b3
Figure 8. Basic I/O Internal Circuit
The transaction is valid when the Chip Select pin is Low,
the I/O signal being Open Drain or Totem Pole on either
sides.
Since the device can operate either in a single or a multiple
card system provisions have been made to avoid CRD_IOA
or B current overload. Depending upon the selected mode of
operation (Async. or Sync), the card I/O line is respectively
connected to either I/O Pin 25, or to the MOSI register byte
bit 2. On the other hand, the logic level present at the card I/O
is feedback to the micro-controller via the MISO register
bit 3. The logic levels present at Pin 31 (EN_RPU) controls
the connection of the internal pullup as depicted Table 6.
Figure 9. Typical I/O rise & fall time (CRD_IOA or B/
Cout > 30 pF and open-drain)
Table 6. I/O PULLUP RESISTOR TABLE
EN_RPU
I/O Pullup Resistor
Device Operation
Low
Open, 18 kW
Disconnected
Applicable in the
Multidevice Mode
Case
High
Internal 18 kW Pullup
Active
NOTE:
Interrupt
When the system is powered up, the INT Pin is set to
HIGH upon Power On Reset (POR) signal. The interrupt
Pin 24 is forced LOW when a card is inserted or extracted
in either of the external ports, or when a fault is developed
across the CRD_VCC output voltage A or B. This signal is
neither combined with CS signal, nor with the chip address.
The INT signal is clear to HIGH upon one of the conditions
Table 7.
Single Device
Mode
18 kW typical value
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NCN6804
Table 7. INTERRUPT RESET LOGIC TABLE
Interrupt Source
(INT set to LOW)
CS
Interrupt Clearance (INT reset to HIGH) CRD_VCCA/B / {b1, b0}
programming
Chip Address
Card Insertion
L
{0,1}, {1,0} or {11}
{b7:b5} = 0XX
Card Extraction
L
{0,0}
{b7:b5} = 0XX
Over Load
L
{0,0}
{b7:b5} = 0XX
In order to know the source of the interrupt (card A or card
B), the software has to poll the MISO register by sending a
MOSI A command (address {b7, b6, b5} = {0, X, 0})
followed by a MOSI B command (address {b7, b6, b5} = {0,
X, 1}) (or conversely). The corresponding MISO content
provides the previous state of the interface A or B that is the
T0
T1
T2
T3
T4
information related to the cause of the interrupt. For each
case the MISO status obtained will be compared with the
MISO state prior to the interrupt. When 2 NCN6804 devices
share the same digital SPI bus, it is up to the software to poll
the devices using again the MISO register to identify the
reason of the interrupt.
T5
T6 T7
T8
T9
T10
T11
T12
CS
INT
CRD_DET
MOSI_b0
MOSI_b1
{b1,b0} = {0,1}, {1,0} or {1,1}
CRD_VCC > 0 V
{b1,b0} = {0,0} CRD_VCC > 0 V
OVER LOAD
CRD_VCC
Figure 10. Basic Interrupt Function
Table 8. INTERRUPT FUNCTION OPERATION
T0
A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line.
T1
The mC sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register.
T2
The mC acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T3
The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the
PWR_DOWN sequence is activated by the NCN6001.
T4
The interrupt pin is clear by the zero volt programmed to the interface.
T5
Same as T0
T6
The mC start the DC/DC converter, the interrupt is cleared (same as T2)
T7
An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low.
T8
The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L).
T9
The card is re-inserted before the interrupt is acknowledged by the mC: the INT pin stays Low.
T10
The mC acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T11
The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or
transaction can take place.
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NCN6804
SPI Port
generated by the NCN6804, using the CLK_SPI and CS
lines to synchronize the bits carried out by the data byte. The
basic timings are given in Figure 11 and 12. The system runs
with two internal registers associated with MOSI and MISO
data:
WRT_REG is a write only register dedicated to the
MOSI data.
READ_REG is a read only register dedicated to the
MISO data.
The product communicates to the external micro
controller by means of a serial link using a Synchronous Port
Interface protocol, the CLK_SPI being Low or High during
the idle state. The NCN6804 is not intended to operate as a
Master controller, but executes commands coming from the
MPU.
The CLK_SPI, CS and MOSI signals are under the
microcontroller's responsibility. The MISO signal is
CS
SPI_CLK
MPU Asserts Chip Select
MPU Enables
Clock
MPU Sends Bit
NCN6804 Reads Bit
MOSI
tclr
RST_COUNTER
NCN6001 Sends Bit
from READ_REG
MPU Reads Bit
MISO
Figure 11. Basic SPI Timings and Protocol
To accommodate the simultaneous MISO transmit, an
internal logic identifies the chip address on the fly (reading
and decoding the three first bits) and validate the right data
present on the line. Consequently, the data format is MSB
first to read the first three signal as bits b5, b6 and b7. The
chip address is decoded from this logic value and validates
the chip according to the S1 pin conditions: see Figure 12.
When the CS line is High, no data can be written or read
on the SPI port. The two data lines become active when
CS = Low, the internal shift register is cleared and the
communication is synchronized by the negative going edge
of the CS signal. THe data presents on the MOSI line are
considered valid on the negative going edge of the CLK_SPI
clock and is transferred to the shift register on the next
positive edge of the same CLK_SPI clock.
CS
MPU Asserts Chip Set
B7
SPI_CLK
MOSI
B6
B5
CHIP
ADDRESS
B3
B2
B1
B0
COMMAND AND CONTROL
MSB
LSB
ADDRESS
DECODE
MISO
B4
MPU Enables Clock
The Chip Address is decoded on the third clock pulse.
MISO Line = High Impedance
The MISO signal is activated and data transferred
Figure 12. Chip Address Decoding Protocol and MISO Sequence
When the bit transfer is completed, the content of the internal shift register is latched on the positive going edge of the CS
signal and the NCN6804 related functions are updated accordingly.
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NCN6804
Select Chip from SYNCHRONOUS Bank
Chip Nx
tdclk
Chip Ny
CS
SPI_CLK
MPU Enables B7
Clock
B6
B5
CHIP
ADDRESS
MOSI
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
AND CONTROL
MSB
LSB
MSB
LSB
SET_RST
SET_CLK
SET_VCC
ADDRESS
DECODE
MISO
Special Mode
MISO Line = High Impedance
MISO Line = High Impedance
MISO
Normal Mode
Normal Mode: MISO is synchronized with
the SPI_CLK Negative going slope
Special Mode: MISO
is synchronized with
the SPI_CLK Positive
going slope
Figure 13. Basic Multi Command SPI Bytes
Since the 2 dual circuits present in the Asynchronous
Bank have an individual physical address, the system can
control 2 of these chips by sending the data content within
the same CS frame as depicted in Figure 13. The bits are
decoded on the fly and the related sub blocks are updated
accordingly. According to the SPI general specification, no
code or activity will be transferred to any chip when the CS
is High.
When 2 SPI dual bytes are sequentially transferred on the
MOSI line, the CLK_SPI sequence must be separated by at
least one half positive period of this clock (see tdclk
parameter).
The oscillograms given Figures 14 and 15 illustrate the
SPI communication protocol.
Figure 14. Programming Sequence
Special mode
Standard mode
Figure 15. MISO Read Out Sequences
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NCN6804
DC/DC Operation
Figure 16). The operation is fully automatic and, beside the
output voltage programming, does not need any further
adjustment.
The power conversion is based on a full bridge structure
able to handle either step up or step down power supply (see
VCC
CRD_VCC
6
10 mF
C1
13
Q1
Q7
GND
CMD_1.8V
CMD_5.0V
CMD_STOP
L1
10
G_Q1
MIXED LOGIC/ANALOG BLOCK
CMD_3.0V
C2
10 mF
Q2
GND
12
22 mH
Q3
Q5
Q6
Q4
GND
G_Q3
G_HIZ
11
PWR_GND
GND
G_Q4
G_Q2
G_Q7
Figure 16. Basic DC/DC Converter
In order to achieve the 250 ms maximum time to discharge
CRD_VCCA or B to 400 mV called by the EMV
specifications, an active pull down NMOS is provided to
discharge the external CRD_VCCA/B reservoir capacitor.
This timing is guaranteed for a 10 mF maximum load
reservoir capacitor value (see Figure 4).
The system operates with a two cycle concept (all
comments are referenced to Figures 16 and 17):
1. Cycle 1 Q1 and Q4 are switched ON and the
inductor L1 is charged by the energy supplied by
the external battery. During this phase, the pair
Q2/Q3 and the pair Q5/Q6 are switched OFF. The
current flowing the two MOSFET Q1 and Q4 is
internally monitored and will be switched OFF
when the Ipeak value (depending upon the
programmed output voltage value) is reached. At
this point, Cycle 1 is completed and Cycle 2 takes
place. The ON time is a function of the battery
voltage and the value of the inductor network (L
and Zr) connected across pins 10/11. A 4 _s
timeout structure ensures the system does run in a
continuous Cycle 1 loop.
2. Cycle 2 Q2 and Q3 are switched ON and the
energy stored into the inductor L1 is dumped into
the external load through Q2. During this phase,
the pair Q1/Q4 and the pair Q5/Q6 are switched
OFF. The current flow period is constant (900 ns
typical) and Cycle 1 repeats after this time if the
CRD_VCC voltage is below the specified value.
When the output voltage reaches the specified value
(1.8 V, 3.0 V or 5.0 V), Q2 and Q3 are switched OFF
immediately to avoid over voltage on the output load. In the
meantime, the two extra NMOS Q5 and Q6 are switched ON
to fully discharge any current stored into the inductor,
avoiding ringing and voltage spikes over the system.
Figure 17 illustrates the theoretical waveforms present in
the DC/DC converter.
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NCN6804
Charge CRD_VCC
ton
CRD_VCC Charged
Next CRD_VCC Charge
(Time is Not to Scale)
toff
Q1/Q4
Q2/Q3
Q5/Q6
Ipeak
IL
CRD_VCC Voltage Regulated
Vripple
CRD_VCC
Figure 17. Theoretical DC/DC Operating Waveforms
When the CRD_VCC is programmed to zero volt, or when
the card is extracted from the socket, the active pull down Q7
rapidly discharges the output reservoir capacitor, making
sure the output voltage is below 0.4 V when the card slides
across the ISO contacts.
Based on the experiments carried out during the
NCN6804 characterization, the best comprise, at time of
printing this document, is to use two 4.7 mF/10 V/
ceramic/X7R capacitors in parallel to achieve the
CRD_VCC filtering. The ESR will not extend 50 mW over
the temperature range and the combination of standard parts
provides an acceptable –20% to +20% tolerance, together
with a low cost. Obviously, the capacitor must be SMD type
to achieve the extremely low ESR and ESL necessary for
this application. Figure 18 illustrates the CRD_VCC ripple
observed in the NCN6804 demoboard depending upon the
type of capacitor used to filter the output voltage.
During the operation, the inductor is subject to high peak
current as depicted Figure 19 and the magnetic core must
sustain this level of current without damage. In particular,
the ferrite material shall not be saturated to avoid
uncontrolled current spike during the charge up cycle.
Moreover, since the DC/DC efficiency depends upon the
losses developed into the active and passive components,
selecting a low ESR inductor is preferred to reduce these
losses to a minimum.
Figure 19. Typical Inductor Current
According to the ISO7816-3 and EMV specifications, it
is recommended the interface limits the CRD_VCC output
current to 200 mA maximum, under short circuit conditions.
The NCN6804 supports such a parameter, the limit being
depending upon the input and output voltages as depicted
Figure 20.
Figure 18. Typical CRD_VCC Ripple Voltage (5 V, 3 V
and 1.8 V) – cms Capacitor COUT = 10 mF, 1210, X7R,
16 V
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NCN6804
6
1.2E+7
10 mF, X7R, 1210, 16 V
5.0 V
1E+7
CAPACITANCE (pF)
CRD_VCC (V)
5
4
3
3.0 V
2
8E+6
6E+6
10 mF, X7R,
0805, 10 V
4E+6
1.8 V
1
10 mF, X5R, 1206, 16 V
10 mF, Y5V, 0805, 16 V
2E+6
0
0
50
100
150
0
200
ICRD_VCC (mA)
1.25
2.5
3.75
DC BIAS VOLTAGE (V)
5
6.25
Figure 21. Variation of the Capacitance Value of
Different CMS Capacitors with the DC Voltage
Applied Across its Terminals
Figure 20. Output Current Limit: Output voltage
CRD_VCC (1.8 V, 3.0 V, 5.0 V)
On the other hand, the circuit is designed to make sure no
over current exist over the full temperature range. As a
matter of fact, the output current limit is reduced when the
temperature increases.
Smart Card Clock Divider
The main purpose of the built in clock generator is three
folds:
1. Adapts the voltage level shifter to cope with the
different voltages that might exist between the
MPU and the Smart Card
2. Provides a frequency division to adapt the Smart
Card operating frequency from the external clock
source.
3. Controls the clock state according to the smart
card specification.
In addition, the NCN6804 adjusts the signal coming from
the mC to get the Duty Cycle window as defined by the
ISO7816-3 specification.
The byte content of the SPI port b2 and b3 fulfills the
programming functions when CS is Low as depicted
Figures 22 and 23. The clock input stage (CLOCK_IN) can
handle a 40 MHz frequency maximum signal, the divider
being capable to provide a 1:4 ratio. Of course, the ratio
must be defined by the engineer to cope with the Smart Card
considered in a given application and, in any case, the output
clock [CRD_CLKA/B] shall be limited to 20 MHz
maximum. In order to minimize the dI/dt and dV/dV
developed in the CRD_CLKA/B line, the output stage
includes a special function to adapt the slope of the clock
signal for different applications. This function is
programmed by the MOSI register (see Table 2) whatever be
the clock division.
DC-T O-DC Converter External PASSIF Component
Selection
To be functional the NCN6804's DC-to-DC converters
need external passive components carefully selected. The
performance and specification compliance of the NCN6804
are guaranteed by the DC/DC converter input capacitor, by
the inductor and the reservoir capacitor characteristics. The
input capacitor enables the decoupling and filtering of the
input power supply voltage (VBAT) and its value has to be
high enough to guarantee a good operating stability of the
converter. A CMS very low ESR capacitor shall be
preferably used with a minimum value of 4.7 mF
recommended, 10 mF will be preferred - this will strongly
depend on how the capacitance value varies with the DC
voltage applied across the capacitor terminals (see
Figure 21). The inductor shall be sized to handle the 500 mA
peak current (Min. Isat) flowing during the DC/DC operation
and will have to offer a low parasitic series resistor in order
to maintain a good efficiency (Ex: Coilcraft,
1008PS-223KLC). The reservoir output capacitor shall be
also ceramic surface mount capacitor with very low ESR
(lower than 50 mW) and good temperature characteristics
(X7R type). 10 mF is the recommended capacitance value
under 5 V, 3 V and 1.8 V to get the better operating
performance with a low CRD_VCC ripple level. The CMS
capacitor shall be selected accordingly that is with a
capacitance value of 10 mF covering the range 1.8 V – 5 V
(see Figure 21). This value constitutes a good compromise
for a good CRD_VCC ripple and CRD_VCC turn-on and
turn-of f times.
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NCN6804
In order to avoid any duty cycle out of the smart card
ISO7816-3 specification, the divider is synchronized by the
last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio (see Figure 22). Consequently,
the output CRD_CLKA/B frequency division can be
delayed by four CLOCK_IN pulses and the micro controller
software must take this delay into account prior to launch a
new data transaction. On the other hand, the output signal
Duty Cycle cannot be guaranteed 50% if the division ratio
is 1 and if the input Duty Cycle signal is not within the 46%
– 56% range.
The input signals CLK_IN and MOSI/b3 are
automatically routed to the level shifter and control block
according to the mode of operation.
CLOCK_IN
CLOCK : 1
Internal
CLOCK
Divider
CLOCK : 2
CLOCK : 4
B2
These bits program
CLOCK = 1:1 ratio
B3
Clock is updated upon
CLOCK: 4 rising edge
CRD_CLK
CLOCK programming is activated
by the B2 + B3 logic state
Figure 22. Typical Clock Divider Synchronization
VCC
CRD_VCC
CLK_IN
U1
DIGITAL_MUX
ASYNC
B2
B
Programming
CRD_CLK
Division
B3
OUT
SYNC
LEVEL SHIFTER
AND CONTROL
CRD_CLK
SEL
A
SYNC
B0
Programming
CRD_CLK Slope
B1
NOTE: Bits [B0...B3] come from SPI data
Figure 23. Basic Clock Divider and Level Shifter
The input clock can be divided by 1/1, ½, or ¼,, depending
upon the specific application, prior to be applied to the smart
card driver. On the other hand, the positive and negative
going slopes of the output clock (CRD_CLKA/B) can be
programmed to optimize the operation of the chip: see
Table 2. The slope of the output clock can be programmed
on the fly, independently of either the CRD_VCCA/B
voltage or the operating frequency, but cares must be
observed as the CRD_RSTA/B will reflect the logic state
present at MOSI / b4 register.
Table 9. Output Clock Rise and Fall Time Selection
B0
B1
CRD_CLK
Division Ratio
CRD_CLK
SLO_SLP
CRD_CLK
FST_SLP
0
0
-
Output Clock = Low
Output Clock = Low
0
1
1
10 ns (typ.)
2 ns (typ.)
1
0
1/2
10 ns (typ.)
2 ns (typ.)
1
1
1/4
10 ns (typ.)
2 ns (typ.)
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NCN6804
Input Schmitt Triggers
Battery Voltage: Both the Over and Undervoltage are
detected by the NCN6804, the READ_REG register being
updated accordingly. The external MPU can read the register
through the MISO pin to take whatever is appropriate to
cope with the situation.
All the Logic Input pins have built in Schmitt trigger
circuits to protect the NCN6804 against uncontrolled
operation. The typical dynamic characteristics of the related
pins are depicted Figure 24.
ESD Protection
OUTPUT
The NCN6804 dual smart card interface features an
HBM ESD voltage protection (JEDEC standard) in excess
of 8 kV for all the CRD pins (CRD_IOA/B, CRD_CLKA/B,
CRD_RSTA/B, CRD_VCCA/B and GND). CRD_DETA/B
have a protection of 4 kV HBM. All the other pins
(microcontroller side) sustain at least 2 kV.
These values are guaranteed for the device in its full
integrity without considering the external capacitors added
to the circuit for a proper operating. Consequently in the
operating conditions it is able to sustain much more than
8 kV on its CRD pins making it perfectly protected against
electrostatic discharge well over the HBM ESD voltages
required by the ISO7816 standard.
VBAT
ON
OFF
INPUT
0.3 VBAT
0.7 VBAT
VBA
T
Figure 24. Typical Schmitt Trigger Characteristic
Printed Circuit Board Layout
Security Features
Careful layout routing will be applied to achieve a good
and efficient operating of the device in its application
environment and to fully exploit its performance. The
bypass capacitors have to be connected as close as possible
to the device pins (CRD_VCCA/B, VDD or VDDPA/B) in
order to reduce as much as possible parasitic behaviors
(ripple and noise). It is recommended to use ceramic
capacitors (very low ESR).
The exposed pad of the QFN-32 package will be
connected to the ground. A relatively large ground plane is
recommended. Figure 25 shows a example of PCB device
implementation and component routing.
In order to protect both the interface and the external smart
card, the NCN6804 provides security features to prevent
irreversible failures as described here after.
Pin Current Limitation: In the case of a short circuit to
ground, the current forced by the device is limited to 15 mA
for any pins, except CRD_CLK A/B pin which is limited to
70 mA. No feedback is provided to the external MPU.
DC/DC Operation: The internal circuit continuously senses
the CRD_VCCA/B voltage; in the case of either over or
undervoltage situation it updates the READ_REG register
accordingly and forces the INT Pin to Low. This register can
be readout by the MPU.
CRD_VCCA Reservoir Capacitor
10 mF, 1210, X7R, 16 V
LA 22 mH
VDD Decoupling
Capacitor 100 nF
VDDPA/B Decoupling
Capacitor 10 mF
LB 22 mH
Figure 25. Example of PCB Device Implementation
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NCN6804
PACKAGE DIMENSIONS
QFN32, 5x5, 0.5P
MN SUFFIX
CASE 488AM-01
ISSUE O
PIN ONE
LOCATION
ÉÉ
ÉÉ
0.15 C
2X
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
SEATING
PLANE
A1
SIDE VIEW
C
L
SOLDERING FOOTPRINT*
5.30
EXPOSED PAD
32 X
D2
9
16
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
----0.300 0.400 0.500
K
3.20
32 X
17
8
32 X
0.63
E2
1
24
32
3.20
5.30
25
32 X b
0.10 C A B
e
0.05 C
32 X
0.28
28 X
0.50 PITCH
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
Sales Representative
NCN6804/D