NBXSBB020, NBXSBA020 3.3 V, 280 MHz LVPECL Clock Oscillator The NBXSBB020/NBXSBA020 single frequency crystal oscillator (XO) is designed to meet today’s requirements for 3.3 V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide 280 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor’s PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Frequency stability options available as either 50 PPM NBXSBA020 or 20 PPM NBXSBB020. http://onsemi.com 6 PIN CLCC LN SUFFIX CASE 848AB Features • • • • • • • • LVPECL Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz) Output Frequency − 280 MHz Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range 3.3 V ±10% Total Frequency Stability − ±20 PPM* or ±50 PPM Applications • Servers VDD 6 CLK CLK 5 4 MARKING DIAGRAMS NBXSBB020 280 AAWLYYWWG NBXSBB020 = NBXSBB020 (±20 PPM)* NBXSBA020 = NBXSBA020 (±50 PPM) 280 = Output Frequency (MHz) AA = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION Package Shipping† NBXSBB020LN1TAG* CLCC−6 (Pb−Free) 1000/ Tape & Reel NBXSBA020LN1TAG CLCC−6 (Pb−Free) 1000/ Tape & Reel NBXSBA020LNHTAG CLCC−6 (Pb−Free) 100/ Tape & Reel Device PLL Clock Multiplier Crystal 1 OE 2 NC NBXSBA020 280 AAWLYYWWG 3 GND †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Figure 1. Simplified Logic Diagram * Please contact sales office for availability © Semiconductor Components Industries, LLC, 2010 February, 2010 − Rev. 5 1 Publication Order Number: NBXSBB020/D NBXSBB020, NBXSBA020 OE 1 6 VDD NC 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin No. Symbol I/O Description 1 OE LVTTL/LVCMOS Control Input 2 NC N/A No Connect. 3 GND Power Supply Ground 0 V. 4 CLK LVPECL Output Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD − 2 V. 5 CLK LVPECL Output Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD − 2 V. 6 VDD Power Supply Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. Positive power supply voltage. Voltage should not exceed 3.3 V ±10%. Table 2. OUTPUT ENABLE TRI−STATE FUNCTION OE Pin Output Pins Open Active HIGH Level Active LOW Level High Z Table 3. ATTRIBUTES Characteristic Value Internal Default State Resistor ESD Protection 170 kW Human Body Model Machine Model 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Rating Units VDD Positive Power Supply Parameter Condition 1 GND = 0 V Condition 2 4.6 V Iout LVPECL Output Current Continuous Surge 25 50 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −55 to +120 °C Tsol Wave Solder 260 °C See Figure 5 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NBXSBB020, NBXSBA020 Table 5. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2) Symbol Characteristic Conditions Min. Typ. Max. Units 75 100 mA IDD Power Supply Current (Note 2) VIH OE and FSEL Input HIGH Voltage 2000 VDD mV VIL OE and FSEL Input LOW Voltage GND − 300 800 mV IIH Input HIGH Current OE FSEL −100 −100 +100 +100 mA IIL Input LOW Current OE FSEL −100 −100 +100 +100 mA VDD−1195 2105 VDD−945 2355 mV VDD = 3.3 V VDD−1945 1355 VDD−1600 1700 mV VDD = 3.3 V VOH VOL VOUTPP Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Output Voltage Amplitude (Note 2) 700 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Measurement taken with outputs terminated with 50 ohm to VDD−2 V. See Figure 4. http://onsemi.com 3 NBXSBB020, NBXSBA020 Table 6. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic fCLKOUT Output Clock Frequency Df FNOISE Typ. Max. 280 Units MHz 0°C to +70°C −40°C to +85°C (Note 4) Phase−Noise Performance 100 Hz of Carrier −102 dBc/Hz fCLKout = 280 MHz (See Figure 3) 1 kHz of Carrier −114 dBc/Hz Spurious Noise tjit(F) RMS Phase Jitter tjitter Cycle to Cycle, RMS Cycle to Cycle, Peak−to−Peak tDUTY_CYCLE Min. Frequency Stability − NBXSBB020 Frequency Stability − NBXSBA020 NSP tOE/OD Conditions ±20 ±50 PPM 10 kHz of Carrier −123 dBc/Hz 100 kHz of Carrier −123 dBc/Hz 1 MHz of Carrier −132 dBc/Hz 10 MHz of Carrier −157 dBc/Hz (Note 5) −60 dBc 12 kHz to 20 MHz 0.4 0.9 ps 1000 Cycles 2 8 ps 1000 Cycles 13 30 ps Period, RMS 10,000 Cycles 1 4 ps Period, Peak−to−Peak 10,000 Cycles 10 20 ps 200 ns 50 52 % Output Enable/Disable Time Output Clock Duty Cycle (Measured at Cross Point) 48 tR Output Rise Time (20% and 80%) 250 400 ps tF Output Fall Time (80% and 20%) 250 400 ps 1 5 ms 3 ppm 1 ppm tstart Start−up Time Aging 1st Year Every Year After 1st NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Measurement taken with outputs terminated with 50 ohm to VDD−2 V. See Figure 4. 4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging. 5. Guaranteed by design and verified at qualification. Not tested in production. http://onsemi.com 4 NBXSBB020, NBXSBA020 Figure 3. Typical Phase Noise Plot http://onsemi.com 5 NBXSBB020, NBXSBA020 Table 7. RELIABILITY COMPLIANCE ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Parameter Standard Method Shock Mechanical MIL−STD−833, Method 2002, Condition B Solderability Mechanical MIL−STD−833, Method 2003 Vibration Mechanical MIL−STD−833, Method 2007, Condition A Solvent Resistance Mechanical MIL−STD−202, Method 215 Thermal Shock Environment MIL−STD−833, Method 1011, Condition A Moisture Level Sensitivity Environment MSL1 260°C per IPC/JEDEC J−STD−020D NBXSBB020/NBXSBA020 Zo = 50 W CLK D Receiver Device Driver Device CLK D Zo = 50 W 50 W 50 W VTT VTT = VDD − 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) temp. 260°C 20 − 40 sec. max. peak Temperature (°C) 260 6°C/sec. max. 3°C/sec. max. 217 ramp−up 175 150 cooling pre−heat reflow 60180 sec. Time 60150 sec. Figure 5. Recommended Reflow Soldering Profile http://onsemi.com 6 NBXSBB020, NBXSBA020 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB−01 ISSUE C 4X A D D1 0.15 C E2 TERMINAL 1 INDICATOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. B H E1 DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e L R E D2 TOP VIEW A3 A2 0.10 C A SIDE VIEW A1 C SEATING PLANE 2 3 0.08 1.30 6.17 6.66 4.37 4.65 1.17 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.27 1.37 0.70 REF SOLDERING FOOTPRINT* D3 1 MIN 1.70 e 6X 1.50 R E3 0.10 C A B 0.05 C 6X b 6 5 4 6X L 2.54 PITCH BOTTOM VIEW 5.06 6X 1.50 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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