ONSEMI NBXDBA009LN1TAG

NBXDBA009
3.3 V, 75 MHz / 150 MHz
LVPECL Clock Oscillator
The NBXDBA009 dual frequency crystal oscillator (XO) is
designed to meet today’s requirements for 3.3 V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable 75 MHz
or 150 MHz, ultra low jitter and phase noise LVPECL differential
output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000.
Features
•
•
•
•
•
•
•
•
•
LVPECL Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz)
Selectable Output Frequency − 75 MHz (default) / 150 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range 3.3 V ±10%
Total Frequency Stability − $50 PPM
This is a Pb−Free Device
Applications
• SAS Gen2
• Serial ATA
VDD
6
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MARKING DIAGRAM
NBXDBA009
75/150
AWLYYWWG
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXDBA009
75/150
A
WL
YY
WW
G
= NBXDBA009 (±50 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NBXDBA009LN1TAG
CLCC−6
(Pb−Free)
1000/
Tape & Reel
NBXDBA009LNHTAG
CLCC−6
(Pb−Free)
100/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
CLK CLK
5 4
PLL
Clock
Multiplier
Crystal
1
OE
2
FSEL
3
GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 1
1
Publication Order Number:
NBXDBA009/D
NBXDBA009
OE
1
6
VDD
FSEL
2
5
CLK
GND
3
4
CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin No.
Symbol
I/O
1
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
Description
2
FSEL
LVTTL/LVCMOS
Control Input
Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Frequency Select pin description Table 3.
3
GND
Power Supply
4
CLK
LVPECL Output
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD − 2 V.
5
CLK
LVPECL Output
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD − 2 V.
6
VDD
Power Supply
Ground 0 V
Positive power supply voltage. Voltage should not exceed 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
Table 3. OUTPUT FREQUENCY SELECT
OE Pin
Output Pins
FSEL Pin
Output Frequency (MHz)
Open
Active
75
HIGH Level
Active
Open
(pin will float high)
LOW Level
High Z
HIGH Level
75
LOW Level
150
Table 4. ATTRIBUTES
Characteristic
Value
Input Default State Resistor
ESD Protection
170 kW
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VDD
Positive Power Supply
GND = 0 V
4.6
V
Iout
LVPECL Output Current
Continuous
Surge
25
50
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−55 to +120
°C
Tsol
Wave Solder
260
°C
See Figure 6
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NBXDBA009
Table 6. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
79
100
mA
IDD
Power Supply Current
VIH
OE and FSEL Input HIGH Voltage
2000
VDD
mV
VIL
OE and FSEL Input LOW Voltage
GND − 300
800
mV
IIH
Input HIGH Current
OE
FSEL
−100
−100
+100
+100
mA
IIL
Input LOW Current
OE
FSEL
−100
−100
+100
+100
mA
VDD−1195
2105
VDD−945
2355
mV
VDD = 3.3 V
VDD−1945
1355
VDD−1600
1700
mV
VDD = 3.3 V
VOH
VOL
VOUTPP
Output HIGH Voltage
Output LOW Voltage
Output Voltage Amplitude
660
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to VDD−2 V. See Figure 5.
Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
fCLKOUT
Df
FNOISE
Characteristic
Output Clock Frequency
Typ.
75
FSEL = LOW
150
(Note 4)
Max.
Units
MHz
±50
ppm
Phase−Noise Performance
100 Hz of Carrier
−108/−102
dBc/Hz
fCLKout = 75 MHz/150 MHz
(See Figures 3 and 4)
1 kHz of Carrier
−122/−116
dBc/Hz
10 kHz of Carrier
−129/−122
dBc/Hz
100 kHz of Carrier
−129/−122
dBc/Hz
1 MHz of Carrier
−137/−131
dBc/Hz
10 MHz of Carrier
−161/−158
12 kHz to 20 MHz
0.4
Cycle to Cycle, RMS
1000 Cycles
Cycle to Cycle, Peak−to−Peak
1000 Cycles
Period, RMS
Period, Peak−to−Peak
RMS Phase Jitter
tjitter
tDUTY_CYCLE
Min.
FSEL = HIGH
Frequency Stability − NBXDBA009
tjit(F)
tOE/OD
Conditions
dBc/Hz
0.9
ps
2.3
8
ps
13
30
ps
10,000 Cycles
1.3
4
ps
10,000 Cycles
8.7
20
ps
200
ns
50
52
%
ps
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
48
tR
Output Rise Time (20% and 80%)
250
400
tF
Output Fall Time (80% and 20%)
250
400
ps
1
5
ms
3
ppm
1
ppm
tstart
Start−up Time
1st Year
Aging
Every Year After
1st
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to VDD−2 V. See Figure 5.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
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3
NBXDBA009
Figure 3. Typical Phase Noise Plot at 75 MHz
Figure 4. Typical Phase Noise Plot at 150 MHz
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4
NBXDBA009
Table 8. RELIABILITY COMPLIANCE
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter
Standard
Method
Shock
Mechanical
MIL−STD−833, Method 2002, Condition B
Solderability
Mechanical
MIL−STD−833, Method 2003
Vibration
Mechanical
MIL−STD−833, Method 2007, Condition A
Solvent Resistance
Mechanical
MIL−STD−202, Method 215
Thermal Shock
Environment
MIL−STD−833, Method 1011, Condition A
Moisture Level Sensitivity
Environment
MSL1 260°C per IPC/JEDEC J−STD−020D
NBXDBA009
Zo = 50 W
CLK
D
Receiver
Device
Driver
Device
CLK
D
Zo = 50 W
50 W
50 W
VTT
VTT = VDD − 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
temp. 260°C
20 − 40 sec. max.
peak
Temperature (°C)
260
6°C/sec. max.
3°C/sec. max.
217
ramp−up
175
150
cooling
pre−heat
reflow
60180 sec.
Time
60150 sec.
Figure 6. Recommended Reflow Soldering Profile
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5
NBXDBA009
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P
CASE 848AB−01
ISSUE C
A
D
4X
0.15 C
E2
TERMINAL 1
INDICATOR
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
B
D1
H E1
DIM
A
A1
A2
A3
b
D
D1
D2
D3
E
E1
E2
E3
e
H
L
R
E
D2
TOP VIEW
A3
A2
0.10 C
A
SIDE VIEW
A1
C
6.17
6.66
4.37
4.65
1.17
SOLDERING FOOTPRINT*
2
3
e
6X
R
1.50
E3
0.10 C A B
0.05 C
0.08
1.30
MILLIMETERS
NOM
MAX
1.80
1.90
0.70 REF
0.36 REF
0.10
0.12
1.40
1.50
7.00 BSC
6.20
6.23
6.81
6.96
5.08 BSC
5.00 BSC
4.40
4.43
4.80
4.95
3.49 BSC
2.54 BSC
1.80 REF
1.27
1.37
0.70 REF
SEATING
PLANE
D3
1
MIN
1.70
6X
b
6
5
4
6X
5.06
L
BOTTOM VIEW
2.54
PITCH
6X
1.50
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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6
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For additional information, please contact your local
Sales Representative
NBXDBA009/D